[llvm] r237275 - MC: Modernize MCOperand API naming. NFC.
Jim Grosbach
grosbach at apple.com
Wed May 13 11:37:01 PDT 2015
Author: grosbach
Date: Wed May 13 13:37:00 2015
New Revision: 237275
URL: http://llvm.org/viewvc/llvm-project?rev=237275&view=rev
Log:
MC: Modernize MCOperand API naming. NFC.
MCOperand::Create*() methods renamed to MCOperand::create*().
Modified:
llvm/trunk/include/llvm/MC/MCInst.h
llvm/trunk/include/llvm/MC/MCInstBuilder.h
llvm/trunk/lib/MC/MCDisassembler/MCExternalSymbolizer.cpp
llvm/trunk/lib/Target/AArch64/AArch64AsmPrinter.cpp
llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp
llvm/trunk/lib/Target/AArch64/AArch64MCInstLower.cpp
llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
llvm/trunk/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
llvm/trunk/lib/Target/AArch64/Disassembler/AArch64ExternalSymbolizer.cpp
llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp
llvm/trunk/lib/Target/ARM/ARMMCInstLower.cpp
llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
llvm/trunk/lib/Target/ARM/Thumb1InstrInfo.cpp
llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp
llvm/trunk/lib/Target/BPF/BPFMCInstLower.cpp
llvm/trunk/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp
llvm/trunk/lib/Target/Hexagon/HexagonMCInstLower.cpp
llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp
llvm/trunk/lib/Target/MSP430/MSP430MCInstLower.cpp
llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
llvm/trunk/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsNaClELFStreamer.cpp
llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp
llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp
llvm/trunk/lib/Target/Mips/MipsMCInstLower.cpp
llvm/trunk/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
llvm/trunk/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
llvm/trunk/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp
llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cpp
llvm/trunk/lib/Target/PowerPC/PPCMCInstLower.cpp
llvm/trunk/lib/Target/R600/AMDGPUMCInstLower.cpp
llvm/trunk/lib/Target/R600/AsmParser/AMDGPUAsmParser.cpp
llvm/trunk/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
llvm/trunk/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp
llvm/trunk/lib/Target/Sparc/SparcAsmPrinter.cpp
llvm/trunk/lib/Target/Sparc/SparcMCInstLower.cpp
llvm/trunk/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp
llvm/trunk/lib/Target/SystemZ/Disassembler/SystemZDisassembler.cpp
llvm/trunk/lib/Target/SystemZ/SystemZMCInstLower.cpp
llvm/trunk/lib/Target/X86/AsmParser/X86AsmInstrumentation.cpp
llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp
llvm/trunk/lib/Target/X86/AsmParser/X86Operand.h
llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.cpp
llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
llvm/trunk/lib/Target/X86/X86MCInstLower.cpp
llvm/trunk/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp
llvm/trunk/lib/Target/XCore/XCoreMCInstLower.cpp
llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp
llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.cpp
llvm/trunk/utils/TableGen/PseudoLoweringEmitter.cpp
Modified: llvm/trunk/include/llvm/MC/MCInst.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCInst.h?rev=237275&r1=237274&r2=237275&view=diff
==============================================================================
--- llvm/trunk/include/llvm/MC/MCInst.h (original)
+++ llvm/trunk/include/llvm/MC/MCInst.h Wed May 13 13:37:00 2015
@@ -108,31 +108,31 @@ public:
InstVal = Val;
}
- static MCOperand CreateReg(unsigned Reg) {
+ static MCOperand createReg(unsigned Reg) {
MCOperand Op;
Op.Kind = kRegister;
Op.RegVal = Reg;
return Op;
}
- static MCOperand CreateImm(int64_t Val) {
+ static MCOperand createImm(int64_t Val) {
MCOperand Op;
Op.Kind = kImmediate;
Op.ImmVal = Val;
return Op;
}
- static MCOperand CreateFPImm(double Val) {
+ static MCOperand createFPImm(double Val) {
MCOperand Op;
Op.Kind = kFPImmediate;
Op.FPImmVal = Val;
return Op;
}
- static MCOperand CreateExpr(const MCExpr *Val) {
+ static MCOperand createExpr(const MCExpr *Val) {
MCOperand Op;
Op.Kind = kExpr;
Op.ExprVal = Val;
return Op;
}
- static MCOperand CreateInst(const MCInst *Val) {
+ static MCOperand createInst(const MCInst *Val) {
MCOperand Op;
Op.Kind = kInst;
Op.InstVal = Val;
Modified: llvm/trunk/include/llvm/MC/MCInstBuilder.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCInstBuilder.h?rev=237275&r1=237274&r2=237275&view=diff
==============================================================================
--- llvm/trunk/include/llvm/MC/MCInstBuilder.h (original)
+++ llvm/trunk/include/llvm/MC/MCInstBuilder.h Wed May 13 13:37:00 2015
@@ -30,31 +30,31 @@ public:
/// \brief Add a new register operand.
MCInstBuilder &addReg(unsigned Reg) {
- Inst.addOperand(MCOperand::CreateReg(Reg));
+ Inst.addOperand(MCOperand::createReg(Reg));
return *this;
}
/// \brief Add a new integer immediate operand.
MCInstBuilder &addImm(int64_t Val) {
- Inst.addOperand(MCOperand::CreateImm(Val));
+ Inst.addOperand(MCOperand::createImm(Val));
return *this;
}
/// \brief Add a new floating point immediate operand.
MCInstBuilder &addFPImm(double Val) {
- Inst.addOperand(MCOperand::CreateFPImm(Val));
+ Inst.addOperand(MCOperand::createFPImm(Val));
return *this;
}
/// \brief Add a new MCExpr operand.
MCInstBuilder &addExpr(const MCExpr *Val) {
- Inst.addOperand(MCOperand::CreateExpr(Val));
+ Inst.addOperand(MCOperand::createExpr(Val));
return *this;
}
/// \brief Add a new MCInst operand.
MCInstBuilder &addInst(const MCInst *Val) {
- Inst.addOperand(MCOperand::CreateInst(Val));
+ Inst.addOperand(MCOperand::createInst(Val));
return *this;
}
Modified: llvm/trunk/lib/MC/MCDisassembler/MCExternalSymbolizer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCDisassembler/MCExternalSymbolizer.cpp?rev=237275&r1=237274&r2=237275&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCDisassembler/MCExternalSymbolizer.cpp (original)
+++ llvm/trunk/lib/MC/MCDisassembler/MCExternalSymbolizer.cpp Wed May 13 13:37:00 2015
@@ -136,7 +136,7 @@ bool MCExternalSymbolizer::tryAddingSymb
if (!Expr)
return false;
- MI.addOperand(MCOperand::CreateExpr(Expr));
+ MI.addOperand(MCOperand::createExpr(Expr));
return true;
}
Modified: llvm/trunk/lib/Target/AArch64/AArch64AsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64AsmPrinter.cpp?rev=237275&r1=237274&r2=237275&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64AsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64AsmPrinter.cpp Wed May 13 13:37:00 2015
@@ -467,7 +467,7 @@ void AArch64AsmPrinter::EmitInstruction(
case AArch64::TCRETURNri: {
MCInst TmpInst;
TmpInst.setOpcode(AArch64::BR);
- TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
+ TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
EmitToStreamer(*OutStreamer, TmpInst);
return;
}
@@ -500,24 +500,24 @@ void AArch64AsmPrinter::EmitInstruction(
MCInst Adrp;
Adrp.setOpcode(AArch64::ADRP);
- Adrp.addOperand(MCOperand::CreateReg(AArch64::X0));
+ Adrp.addOperand(MCOperand::createReg(AArch64::X0));
Adrp.addOperand(SymTLSDesc);
EmitToStreamer(*OutStreamer, Adrp);
MCInst Ldr;
Ldr.setOpcode(AArch64::LDRXui);
- Ldr.addOperand(MCOperand::CreateReg(AArch64::X1));
- Ldr.addOperand(MCOperand::CreateReg(AArch64::X0));
+ Ldr.addOperand(MCOperand::createReg(AArch64::X1));
+ Ldr.addOperand(MCOperand::createReg(AArch64::X0));
Ldr.addOperand(SymTLSDescLo12);
- Ldr.addOperand(MCOperand::CreateImm(0));
+ Ldr.addOperand(MCOperand::createImm(0));
EmitToStreamer(*OutStreamer, Ldr);
MCInst Add;
Add.setOpcode(AArch64::ADDXri);
- Add.addOperand(MCOperand::CreateReg(AArch64::X0));
- Add.addOperand(MCOperand::CreateReg(AArch64::X0));
+ Add.addOperand(MCOperand::createReg(AArch64::X0));
+ Add.addOperand(MCOperand::createReg(AArch64::X0));
Add.addOperand(SymTLSDescLo12);
- Add.addOperand(MCOperand::CreateImm(AArch64_AM::getShiftValue(0)));
+ Add.addOperand(MCOperand::createImm(AArch64_AM::getShiftValue(0)));
EmitToStreamer(*OutStreamer, Add);
// Emit a relocation-annotation. This expands to no code, but requests
@@ -529,7 +529,7 @@ void AArch64AsmPrinter::EmitInstruction(
MCInst Blr;
Blr.setOpcode(AArch64::BLR);
- Blr.addOperand(MCOperand::CreateReg(AArch64::X1));
+ Blr.addOperand(MCOperand::createReg(AArch64::X1));
EmitToStreamer(*OutStreamer, Blr);
return;
Modified: llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp?rev=237275&r1=237274&r2=237275&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp Wed May 13 13:37:00 2015
@@ -2366,7 +2366,7 @@ bool llvm::rewriteAArch64FrameIndex(Mach
void AArch64InstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
NopInst.setOpcode(AArch64::HINT);
- NopInst.addOperand(MCOperand::CreateImm(0));
+ NopInst.addOperand(MCOperand::createImm(0));
}
/// useMachineCombiner - return true when a target supports MachineCombiner
bool AArch64InstrInfo::useMachineCombiner() const {
Modified: llvm/trunk/lib/Target/AArch64/AArch64MCInstLower.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64MCInstLower.cpp?rev=237275&r1=237274&r2=237275&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64MCInstLower.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64MCInstLower.cpp Wed May 13 13:37:00 2015
@@ -73,7 +73,7 @@ MCOperand AArch64MCInstLower::lowerSymbo
if (!MO.isJTI() && MO.getOffset())
Expr = MCBinaryExpr::CreateAdd(
Expr, MCConstantExpr::Create(MO.getOffset(), Ctx), Ctx);
- return MCOperand::CreateExpr(Expr);
+ return MCOperand::createExpr(Expr);
}
MCOperand AArch64MCInstLower::lowerSymbolOperandELF(const MachineOperand &MO,
@@ -148,7 +148,7 @@ MCOperand AArch64MCInstLower::lowerSymbo
RefKind = static_cast<AArch64MCExpr::VariantKind>(RefFlags);
Expr = AArch64MCExpr::Create(Expr, RefKind, Ctx);
- return MCOperand::CreateExpr(Expr);
+ return MCOperand::createExpr(Expr);
}
MCOperand AArch64MCInstLower::LowerSymbolOperand(const MachineOperand &MO,
@@ -169,16 +169,16 @@ bool AArch64MCInstLower::lowerOperand(co
// Ignore all implicit register operands.
if (MO.isImplicit())
return false;
- MCOp = MCOperand::CreateReg(MO.getReg());
+ MCOp = MCOperand::createReg(MO.getReg());
break;
case MachineOperand::MO_RegisterMask:
// Regmasks are like implicit defs.
return false;
case MachineOperand::MO_Immediate:
- MCOp = MCOperand::CreateImm(MO.getImm());
+ MCOp = MCOperand::createImm(MO.getImm());
break;
case MachineOperand::MO_MachineBasicBlock:
- MCOp = MCOperand::CreateExpr(
+ MCOp = MCOperand::createExpr(
MCSymbolRefExpr::Create(MO.getMBB()->getSymbol(), Ctx));
break;
case MachineOperand::MO_GlobalAddress:
Modified: llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp?rev=237275&r1=237274&r2=237275&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp Wed May 13 13:37:00 2015
@@ -1098,16 +1098,16 @@ public:
void addExpr(MCInst &Inst, const MCExpr *Expr) const {
// Add as immediates when possible. Null MCExpr = 0.
if (!Expr)
- Inst.addOperand(MCOperand::CreateImm(0));
+ Inst.addOperand(MCOperand::createImm(0));
else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
- Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
+ Inst.addOperand(MCOperand::createImm(CE->getValue()));
else
- Inst.addOperand(MCOperand::CreateExpr(Expr));
+ Inst.addOperand(MCOperand::createExpr(Expr));
}
void addRegOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateReg(getReg()));
+ Inst.addOperand(MCOperand::createReg(getReg()));
}
void addGPR32as64Operands(MCInst &Inst, unsigned N) const {
@@ -1119,26 +1119,26 @@ public:
uint32_t Reg = RI->getRegClass(AArch64::GPR32RegClassID).getRegister(
RI->getEncodingValue(getReg()));
- Inst.addOperand(MCOperand::CreateReg(Reg));
+ Inst.addOperand(MCOperand::createReg(Reg));
}
void addVectorReg64Operands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
assert(
AArch64MCRegisterClasses[AArch64::FPR128RegClassID].contains(getReg()));
- Inst.addOperand(MCOperand::CreateReg(AArch64::D0 + getReg() - AArch64::Q0));
+ Inst.addOperand(MCOperand::createReg(AArch64::D0 + getReg() - AArch64::Q0));
}
void addVectorReg128Operands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
assert(
AArch64MCRegisterClasses[AArch64::FPR128RegClassID].contains(getReg()));
- Inst.addOperand(MCOperand::CreateReg(getReg()));
+ Inst.addOperand(MCOperand::createReg(getReg()));
}
void addVectorRegLoOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateReg(getReg()));
+ Inst.addOperand(MCOperand::createReg(getReg()));
}
template <unsigned NumRegs>
@@ -1149,7 +1149,7 @@ public:
unsigned FirstReg = FirstRegs[NumRegs - 1];
Inst.addOperand(
- MCOperand::CreateReg(FirstReg + getVectorListStart() - AArch64::Q0));
+ MCOperand::createReg(FirstReg + getVectorListStart() - AArch64::Q0));
}
template <unsigned NumRegs>
@@ -1160,32 +1160,32 @@ public:
unsigned FirstReg = FirstRegs[NumRegs - 1];
Inst.addOperand(
- MCOperand::CreateReg(FirstReg + getVectorListStart() - AArch64::Q0));
+ MCOperand::createReg(FirstReg + getVectorListStart() - AArch64::Q0));
}
void addVectorIndex1Operands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
+ Inst.addOperand(MCOperand::createImm(getVectorIndex()));
}
void addVectorIndexBOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
+ Inst.addOperand(MCOperand::createImm(getVectorIndex()));
}
void addVectorIndexHOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
+ Inst.addOperand(MCOperand::createImm(getVectorIndex()));
}
void addVectorIndexSOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
+ Inst.addOperand(MCOperand::createImm(getVectorIndex()));
}
void addVectorIndexDOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
+ Inst.addOperand(MCOperand::createImm(getVectorIndex()));
}
void addImmOperands(MCInst &Inst, unsigned N) const {
@@ -1200,16 +1200,16 @@ public:
assert(N == 2 && "Invalid number of operands!");
if (isShiftedImm()) {
addExpr(Inst, getShiftedImmVal());
- Inst.addOperand(MCOperand::CreateImm(getShiftedImmShift()));
+ Inst.addOperand(MCOperand::createImm(getShiftedImmShift()));
} else {
addExpr(Inst, getImm());
- Inst.addOperand(MCOperand::CreateImm(0));
+ Inst.addOperand(MCOperand::createImm(0));
}
}
void addCondCodeOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateImm(getCondCode()));
+ Inst.addOperand(MCOperand::createImm(getCondCode()));
}
void addAdrpLabelOperands(MCInst &Inst, unsigned N) const {
@@ -1218,7 +1218,7 @@ public:
if (!MCE)
addExpr(Inst, getImm());
else
- Inst.addOperand(MCOperand::CreateImm(MCE->getValue() >> 12));
+ Inst.addOperand(MCOperand::createImm(MCE->getValue() >> 12));
}
void addAdrLabelOperands(MCInst &Inst, unsigned N) const {
@@ -1231,119 +1231,119 @@ public:
const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
if (!MCE) {
- Inst.addOperand(MCOperand::CreateExpr(getImm()));
+ Inst.addOperand(MCOperand::createExpr(getImm()));
return;
}
- Inst.addOperand(MCOperand::CreateImm(MCE->getValue() / Scale));
+ Inst.addOperand(MCOperand::createImm(MCE->getValue() / Scale));
}
void addSImm9Operands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
const MCConstantExpr *MCE = cast<MCConstantExpr>(getImm());
- Inst.addOperand(MCOperand::CreateImm(MCE->getValue()));
+ Inst.addOperand(MCOperand::createImm(MCE->getValue()));
}
void addSImm7s4Operands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
const MCConstantExpr *MCE = cast<MCConstantExpr>(getImm());
- Inst.addOperand(MCOperand::CreateImm(MCE->getValue() / 4));
+ Inst.addOperand(MCOperand::createImm(MCE->getValue() / 4));
}
void addSImm7s8Operands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
const MCConstantExpr *MCE = cast<MCConstantExpr>(getImm());
- Inst.addOperand(MCOperand::CreateImm(MCE->getValue() / 8));
+ Inst.addOperand(MCOperand::createImm(MCE->getValue() / 8));
}
void addSImm7s16Operands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
const MCConstantExpr *MCE = cast<MCConstantExpr>(getImm());
- Inst.addOperand(MCOperand::CreateImm(MCE->getValue() / 16));
+ Inst.addOperand(MCOperand::createImm(MCE->getValue() / 16));
}
void addImm0_7Operands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
const MCConstantExpr *MCE = cast<MCConstantExpr>(getImm());
- Inst.addOperand(MCOperand::CreateImm(MCE->getValue()));
+ Inst.addOperand(MCOperand::createImm(MCE->getValue()));
}
void addImm1_8Operands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
const MCConstantExpr *MCE = cast<MCConstantExpr>(getImm());
- Inst.addOperand(MCOperand::CreateImm(MCE->getValue()));
+ Inst.addOperand(MCOperand::createImm(MCE->getValue()));
}
void addImm0_15Operands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
const MCConstantExpr *MCE = cast<MCConstantExpr>(getImm());
- Inst.addOperand(MCOperand::CreateImm(MCE->getValue()));
+ Inst.addOperand(MCOperand::createImm(MCE->getValue()));
}
void addImm1_16Operands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
const MCConstantExpr *MCE = cast<MCConstantExpr>(getImm());
assert(MCE && "Invalid constant immediate operand!");
- Inst.addOperand(MCOperand::CreateImm(MCE->getValue()));
+ Inst.addOperand(MCOperand::createImm(MCE->getValue()));
}
void addImm0_31Operands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
const MCConstantExpr *MCE = cast<MCConstantExpr>(getImm());
- Inst.addOperand(MCOperand::CreateImm(MCE->getValue()));
+ Inst.addOperand(MCOperand::createImm(MCE->getValue()));
}
void addImm1_31Operands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
const MCConstantExpr *MCE = cast<MCConstantExpr>(getImm());
- Inst.addOperand(MCOperand::CreateImm(MCE->getValue()));
+ Inst.addOperand(MCOperand::createImm(MCE->getValue()));
}
void addImm1_32Operands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
const MCConstantExpr *MCE = cast<MCConstantExpr>(getImm());
- Inst.addOperand(MCOperand::CreateImm(MCE->getValue()));
+ Inst.addOperand(MCOperand::createImm(MCE->getValue()));
}
void addImm0_63Operands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
const MCConstantExpr *MCE = cast<MCConstantExpr>(getImm());
- Inst.addOperand(MCOperand::CreateImm(MCE->getValue()));
+ Inst.addOperand(MCOperand::createImm(MCE->getValue()));
}
void addImm1_63Operands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
const MCConstantExpr *MCE = cast<MCConstantExpr>(getImm());
- Inst.addOperand(MCOperand::CreateImm(MCE->getValue()));
+ Inst.addOperand(MCOperand::createImm(MCE->getValue()));
}
void addImm1_64Operands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
const MCConstantExpr *MCE = cast<MCConstantExpr>(getImm());
- Inst.addOperand(MCOperand::CreateImm(MCE->getValue()));
+ Inst.addOperand(MCOperand::createImm(MCE->getValue()));
}
void addImm0_127Operands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
const MCConstantExpr *MCE = cast<MCConstantExpr>(getImm());
- Inst.addOperand(MCOperand::CreateImm(MCE->getValue()));
+ Inst.addOperand(MCOperand::createImm(MCE->getValue()));
}
void addImm0_255Operands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
const MCConstantExpr *MCE = cast<MCConstantExpr>(getImm());
- Inst.addOperand(MCOperand::CreateImm(MCE->getValue()));
+ Inst.addOperand(MCOperand::createImm(MCE->getValue()));
}
void addImm0_65535Operands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
const MCConstantExpr *MCE = cast<MCConstantExpr>(getImm());
- Inst.addOperand(MCOperand::CreateImm(MCE->getValue()));
+ Inst.addOperand(MCOperand::createImm(MCE->getValue()));
}
void addImm32_63Operands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
const MCConstantExpr *MCE = cast<MCConstantExpr>(getImm());
- Inst.addOperand(MCOperand::CreateImm(MCE->getValue()));
+ Inst.addOperand(MCOperand::createImm(MCE->getValue()));
}
void addLogicalImm32Operands(MCInst &Inst, unsigned N) const {
@@ -1351,14 +1351,14 @@ public:
const MCConstantExpr *MCE = cast<MCConstantExpr>(getImm());
uint64_t encoding =
AArch64_AM::encodeLogicalImmediate(MCE->getValue() & 0xFFFFFFFF, 32);
- Inst.addOperand(MCOperand::CreateImm(encoding));
+ Inst.addOperand(MCOperand::createImm(encoding));
}
void addLogicalImm64Operands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
const MCConstantExpr *MCE = cast<MCConstantExpr>(getImm());
uint64_t encoding = AArch64_AM::encodeLogicalImmediate(MCE->getValue(), 64);
- Inst.addOperand(MCOperand::CreateImm(encoding));
+ Inst.addOperand(MCOperand::createImm(encoding));
}
void addLogicalImm32NotOperands(MCInst &Inst, unsigned N) const {
@@ -1366,7 +1366,7 @@ public:
const MCConstantExpr *MCE = cast<MCConstantExpr>(getImm());
int64_t Val = ~MCE->getValue() & 0xFFFFFFFF;
uint64_t encoding = AArch64_AM::encodeLogicalImmediate(Val, 32);
- Inst.addOperand(MCOperand::CreateImm(encoding));
+ Inst.addOperand(MCOperand::createImm(encoding));
}
void addLogicalImm64NotOperands(MCInst &Inst, unsigned N) const {
@@ -1374,14 +1374,14 @@ public:
const MCConstantExpr *MCE = cast<MCConstantExpr>(getImm());
uint64_t encoding =
AArch64_AM::encodeLogicalImmediate(~MCE->getValue(), 64);
- Inst.addOperand(MCOperand::CreateImm(encoding));
+ Inst.addOperand(MCOperand::createImm(encoding));
}
void addSIMDImmType10Operands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
const MCConstantExpr *MCE = cast<MCConstantExpr>(getImm());
uint64_t encoding = AArch64_AM::encodeAdvSIMDModImmType10(MCE->getValue());
- Inst.addOperand(MCOperand::CreateImm(encoding));
+ Inst.addOperand(MCOperand::createImm(encoding));
}
void addBranchTarget26Operands(MCInst &Inst, unsigned N) const {
@@ -1395,7 +1395,7 @@ public:
return;
}
assert(MCE && "Invalid constant immediate operand!");
- Inst.addOperand(MCOperand::CreateImm(MCE->getValue() >> 2));
+ Inst.addOperand(MCOperand::createImm(MCE->getValue() >> 2));
}
void addPCRelLabel19Operands(MCInst &Inst, unsigned N) const {
@@ -1409,7 +1409,7 @@ public:
return;
}
assert(MCE && "Invalid constant immediate operand!");
- Inst.addOperand(MCOperand::CreateImm(MCE->getValue() >> 2));
+ Inst.addOperand(MCOperand::createImm(MCE->getValue() >> 2));
}
void addBranchTarget14Operands(MCInst &Inst, unsigned N) const {
@@ -1423,52 +1423,52 @@ public:
return;
}
assert(MCE && "Invalid constant immediate operand!");
- Inst.addOperand(MCOperand::CreateImm(MCE->getValue() >> 2));
+ Inst.addOperand(MCOperand::createImm(MCE->getValue() >> 2));
}
void addFPImmOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateImm(getFPImm()));
+ Inst.addOperand(MCOperand::createImm(getFPImm()));
}
void addBarrierOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateImm(getBarrier()));
+ Inst.addOperand(MCOperand::createImm(getBarrier()));
}
void addMRSSystemRegisterOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateImm(SysReg.MRSReg));
+ Inst.addOperand(MCOperand::createImm(SysReg.MRSReg));
}
void addMSRSystemRegisterOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateImm(SysReg.MSRReg));
+ Inst.addOperand(MCOperand::createImm(SysReg.MSRReg));
}
void addSystemPStateFieldOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateImm(SysReg.PStateField));
+ Inst.addOperand(MCOperand::createImm(SysReg.PStateField));
}
void addSysCROperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateImm(getSysCR()));
+ Inst.addOperand(MCOperand::createImm(getSysCR()));
}
void addPrefetchOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateImm(getPrefetch()));
+ Inst.addOperand(MCOperand::createImm(getPrefetch()));
}
void addShifterOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
unsigned Imm =
AArch64_AM::getShifterImm(getShiftExtendType(), getShiftExtendAmount());
- Inst.addOperand(MCOperand::CreateImm(Imm));
+ Inst.addOperand(MCOperand::createImm(Imm));
}
void addExtendOperands(MCInst &Inst, unsigned N) const {
@@ -1476,7 +1476,7 @@ public:
AArch64_AM::ShiftExtendType ET = getShiftExtendType();
if (ET == AArch64_AM::LSL) ET = AArch64_AM::UXTW;
unsigned Imm = AArch64_AM::getArithExtendImm(ET, getShiftExtendAmount());
- Inst.addOperand(MCOperand::CreateImm(Imm));
+ Inst.addOperand(MCOperand::createImm(Imm));
}
void addExtend64Operands(MCInst &Inst, unsigned N) const {
@@ -1484,15 +1484,15 @@ public:
AArch64_AM::ShiftExtendType ET = getShiftExtendType();
if (ET == AArch64_AM::LSL) ET = AArch64_AM::UXTX;
unsigned Imm = AArch64_AM::getArithExtendImm(ET, getShiftExtendAmount());
- Inst.addOperand(MCOperand::CreateImm(Imm));
+ Inst.addOperand(MCOperand::createImm(Imm));
}
void addMemExtendOperands(MCInst &Inst, unsigned N) const {
assert(N == 2 && "Invalid number of operands!");
AArch64_AM::ShiftExtendType ET = getShiftExtendType();
bool IsSigned = ET == AArch64_AM::SXTW || ET == AArch64_AM::SXTX;
- Inst.addOperand(MCOperand::CreateImm(IsSigned));
- Inst.addOperand(MCOperand::CreateImm(getShiftExtendAmount() != 0));
+ Inst.addOperand(MCOperand::createImm(IsSigned));
+ Inst.addOperand(MCOperand::createImm(getShiftExtendAmount() != 0));
}
// For 8-bit load/store instructions with a register offset, both the
@@ -1503,8 +1503,8 @@ public:
assert(N == 2 && "Invalid number of operands!");
AArch64_AM::ShiftExtendType ET = getShiftExtendType();
bool IsSigned = ET == AArch64_AM::SXTW || ET == AArch64_AM::SXTX;
- Inst.addOperand(MCOperand::CreateImm(IsSigned));
- Inst.addOperand(MCOperand::CreateImm(hasShiftExtendAmount()));
+ Inst.addOperand(MCOperand::createImm(IsSigned));
+ Inst.addOperand(MCOperand::createImm(hasShiftExtendAmount()));
}
template<int Shift>
@@ -1513,7 +1513,7 @@ public:
const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
uint64_t Value = CE->getValue();
- Inst.addOperand(MCOperand::CreateImm((Value >> Shift) & 0xffff));
+ Inst.addOperand(MCOperand::createImm((Value >> Shift) & 0xffff));
}
template<int Shift>
@@ -1522,7 +1522,7 @@ public:
const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
uint64_t Value = CE->getValue();
- Inst.addOperand(MCOperand::CreateImm((~Value >> Shift) & 0xffff));
+ Inst.addOperand(MCOperand::createImm((~Value >> Shift) & 0xffff));
}
void print(raw_ostream &OS) const override;
@@ -4110,7 +4110,7 @@ bool AArch64AsmParser::parseDirectiveTLS
MCInst Inst;
Inst.setOpcode(AArch64::TLSDESCCALL);
- Inst.addOperand(MCOperand::CreateExpr(Expr));
+ Inst.addOperand(MCOperand::createExpr(Expr));
getParser().getStreamer().EmitInstruction(Inst, STI);
return false;
Modified: llvm/trunk/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp?rev=237275&r1=237274&r2=237275&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp Wed May 13 13:37:00 2015
@@ -261,7 +261,7 @@ static DecodeStatus DecodeFPR128Register
return Fail;
unsigned Register = FPR128DecoderTable[RegNo];
- Inst.addOperand(MCOperand::CreateReg(Register));
+ Inst.addOperand(MCOperand::createReg(Register));
return Success;
}
@@ -290,7 +290,7 @@ static DecodeStatus DecodeFPR64RegisterC
return Fail;
unsigned Register = FPR64DecoderTable[RegNo];
- Inst.addOperand(MCOperand::CreateReg(Register));
+ Inst.addOperand(MCOperand::createReg(Register));
return Success;
}
@@ -311,7 +311,7 @@ static DecodeStatus DecodeFPR32RegisterC
return Fail;
unsigned Register = FPR32DecoderTable[RegNo];
- Inst.addOperand(MCOperand::CreateReg(Register));
+ Inst.addOperand(MCOperand::createReg(Register));
return Success;
}
@@ -332,7 +332,7 @@ static DecodeStatus DecodeFPR16RegisterC
return Fail;
unsigned Register = FPR16DecoderTable[RegNo];
- Inst.addOperand(MCOperand::CreateReg(Register));
+ Inst.addOperand(MCOperand::createReg(Register));
return Success;
}
@@ -353,7 +353,7 @@ static DecodeStatus DecodeFPR8RegisterCl
return Fail;
unsigned Register = FPR8DecoderTable[RegNo];
- Inst.addOperand(MCOperand::CreateReg(Register));
+ Inst.addOperand(MCOperand::createReg(Register));
return Success;
}
@@ -374,7 +374,7 @@ static DecodeStatus DecodeGPR64RegisterC
return Fail;
unsigned Register = GPR64DecoderTable[RegNo];
- Inst.addOperand(MCOperand::CreateReg(Register));
+ Inst.addOperand(MCOperand::createReg(Register));
return Success;
}
@@ -386,7 +386,7 @@ static DecodeStatus DecodeGPR64spRegiste
unsigned Register = GPR64DecoderTable[RegNo];
if (Register == AArch64::XZR)
Register = AArch64::SP;
- Inst.addOperand(MCOperand::CreateReg(Register));
+ Inst.addOperand(MCOperand::createReg(Register));
return Success;
}
@@ -407,7 +407,7 @@ static DecodeStatus DecodeGPR32RegisterC
return Fail;
unsigned Register = GPR32DecoderTable[RegNo];
- Inst.addOperand(MCOperand::CreateReg(Register));
+ Inst.addOperand(MCOperand::createReg(Register));
return Success;
}
@@ -420,7 +420,7 @@ static DecodeStatus DecodeGPR32spRegiste
unsigned Register = GPR32DecoderTable[RegNo];
if (Register == AArch64::WZR)
Register = AArch64::WSP;
- Inst.addOperand(MCOperand::CreateReg(Register));
+ Inst.addOperand(MCOperand::createReg(Register));
return Success;
}
@@ -441,7 +441,7 @@ static DecodeStatus DecodeVectorRegister
return Fail;
unsigned Register = VectorDecoderTable[RegNo];
- Inst.addOperand(MCOperand::CreateReg(Register));
+ Inst.addOperand(MCOperand::createReg(Register));
return Success;
}
@@ -461,7 +461,7 @@ static DecodeStatus DecodeQQRegisterClas
if (RegNo > 31)
return Fail;
unsigned Register = QQDecoderTable[RegNo];
- Inst.addOperand(MCOperand::CreateReg(Register));
+ Inst.addOperand(MCOperand::createReg(Register));
return Success;
}
@@ -484,7 +484,7 @@ static DecodeStatus DecodeQQQRegisterCla
if (RegNo > 31)
return Fail;
unsigned Register = QQQDecoderTable[RegNo];
- Inst.addOperand(MCOperand::CreateReg(Register));
+ Inst.addOperand(MCOperand::createReg(Register));
return Success;
}
@@ -508,7 +508,7 @@ static DecodeStatus DecodeQQQQRegisterCl
if (RegNo > 31)
return Fail;
unsigned Register = QQQQDecoderTable[RegNo];
- Inst.addOperand(MCOperand::CreateReg(Register));
+ Inst.addOperand(MCOperand::createReg(Register));
return Success;
}
@@ -528,7 +528,7 @@ static DecodeStatus DecodeDDRegisterClas
if (RegNo > 31)
return Fail;
unsigned Register = DDDecoderTable[RegNo];
- Inst.addOperand(MCOperand::CreateReg(Register));
+ Inst.addOperand(MCOperand::createReg(Register));
return Success;
}
@@ -551,7 +551,7 @@ static DecodeStatus DecodeDDDRegisterCla
if (RegNo > 31)
return Fail;
unsigned Register = DDDDecoderTable[RegNo];
- Inst.addOperand(MCOperand::CreateReg(Register));
+ Inst.addOperand(MCOperand::createReg(Register));
return Success;
}
@@ -575,7 +575,7 @@ static DecodeStatus DecodeDDDDRegisterCl
if (RegNo > 31)
return Fail;
unsigned Register = DDDDDecoderTable[RegNo];
- Inst.addOperand(MCOperand::CreateReg(Register));
+ Inst.addOperand(MCOperand::createReg(Register));
return Success;
}
@@ -584,14 +584,14 @@ static DecodeStatus DecodeFixedPointScal
const void *Decoder) {
// scale{5} is asserted as 1 in tblgen.
Imm |= 0x20;
- Inst.addOperand(MCOperand::CreateImm(64 - Imm));
+ Inst.addOperand(MCOperand::createImm(64 - Imm));
return Success;
}
static DecodeStatus DecodeFixedPointScaleImm64(llvm::MCInst &Inst, unsigned Imm,
uint64_t Addr,
const void *Decoder) {
- Inst.addOperand(MCOperand::CreateImm(64 - Imm));
+ Inst.addOperand(MCOperand::createImm(64 - Imm));
return Success;
}
@@ -607,21 +607,21 @@ static DecodeStatus DecodePCRelLabel19(l
if (!Dis->tryAddingSymbolicOperand(Inst, ImmVal * 4, Addr,
Inst.getOpcode() != AArch64::LDRXl, 0, 4))
- Inst.addOperand(MCOperand::CreateImm(ImmVal));
+ Inst.addOperand(MCOperand::createImm(ImmVal));
return Success;
}
static DecodeStatus DecodeMemExtend(llvm::MCInst &Inst, unsigned Imm,
uint64_t Address, const void *Decoder) {
- Inst.addOperand(MCOperand::CreateImm((Imm >> 1) & 1));
- Inst.addOperand(MCOperand::CreateImm(Imm & 1));
+ Inst.addOperand(MCOperand::createImm((Imm >> 1) & 1));
+ Inst.addOperand(MCOperand::createImm(Imm & 1));
return Success;
}
static DecodeStatus DecodeMRSSystemRegister(llvm::MCInst &Inst, unsigned Imm,
uint64_t Address,
const void *Decoder) {
- Inst.addOperand(MCOperand::CreateImm(Imm));
+ Inst.addOperand(MCOperand::createImm(Imm));
// Every system register in the encoding space is valid with the syntax
// S<op0>_<op1>_<Cn>_<Cm>_<op2>, so decoding system registers always succeeds.
@@ -631,7 +631,7 @@ static DecodeStatus DecodeMRSSystemRegis
static DecodeStatus DecodeMSRSystemRegister(llvm::MCInst &Inst, unsigned Imm,
uint64_t Address,
const void *Decoder) {
- Inst.addOperand(MCOperand::CreateImm(Imm));
+ Inst.addOperand(MCOperand::createImm(Imm));
return Success;
}
@@ -654,20 +654,20 @@ static DecodeStatus DecodeFMOVLaneInstru
}
// Add the lane
- Inst.addOperand(MCOperand::CreateImm(1));
+ Inst.addOperand(MCOperand::createImm(1));
return Success;
}
static DecodeStatus DecodeVecShiftRImm(llvm::MCInst &Inst, unsigned Imm,
unsigned Add) {
- Inst.addOperand(MCOperand::CreateImm(Add - Imm));
+ Inst.addOperand(MCOperand::createImm(Add - Imm));
return Success;
}
static DecodeStatus DecodeVecShiftLImm(llvm::MCInst &Inst, unsigned Imm,
unsigned Add) {
- Inst.addOperand(MCOperand::CreateImm((Imm + Add) & (Add - 1)));
+ Inst.addOperand(MCOperand::createImm((Imm + Add) & (Add - 1)));
return Success;
}
@@ -787,7 +787,7 @@ static DecodeStatus DecodeThreeAddrSRegI
break;
}
- Inst.addOperand(MCOperand::CreateImm(shift));
+ Inst.addOperand(MCOperand::createImm(shift));
return Success;
}
@@ -819,8 +819,8 @@ static DecodeStatus DecodeMoveImmInstruc
Inst.getOpcode() == AArch64::MOVKXi)
Inst.addOperand(Inst.getOperand(0));
- Inst.addOperand(MCOperand::CreateImm(imm));
- Inst.addOperand(MCOperand::CreateImm(shift));
+ Inst.addOperand(MCOperand::createImm(imm));
+ Inst.addOperand(MCOperand::createImm(shift));
return Success;
}
@@ -838,7 +838,7 @@ static DecodeStatus DecodeUnsignedLdStIn
return Fail;
case AArch64::PRFMui:
// Rt is an immediate in prefetch.
- Inst.addOperand(MCOperand::CreateImm(Rt));
+ Inst.addOperand(MCOperand::createImm(Rt));
break;
case AArch64::STRBBui:
case AArch64::LDRBBui:
@@ -881,7 +881,7 @@ static DecodeStatus DecodeUnsignedLdStIn
DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
if (!Dis->tryAddingSymbolicOperand(Inst, offset, Addr, Fail, 0, 4))
- Inst.addOperand(MCOperand::CreateImm(offset));
+ Inst.addOperand(MCOperand::createImm(offset));
return Success;
}
@@ -956,7 +956,7 @@ static DecodeStatus DecodeSignedLdStInst
return Fail;
case AArch64::PRFUMi:
// Rt is an immediate in prefetch.
- Inst.addOperand(MCOperand::CreateImm(Rt));
+ Inst.addOperand(MCOperand::createImm(Rt));
break;
case AArch64::STURBBi:
case AArch64::LDURBBi:
@@ -1057,7 +1057,7 @@ static DecodeStatus DecodeSignedLdStInst
}
DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
- Inst.addOperand(MCOperand::CreateImm(offset));
+ Inst.addOperand(MCOperand::createImm(offset));
bool IsLoad = fieldFromInstruction(insn, 22, 1);
bool IsIndexed = fieldFromInstruction(insn, 10, 2) != 0;
@@ -1268,7 +1268,7 @@ static DecodeStatus DecodePairLdStInstru
}
DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
- Inst.addOperand(MCOperand::CreateImm(offset));
+ Inst.addOperand(MCOperand::createImm(offset));
// You shouldn't load to the same register twice in an instruction...
if (IsLoad && Rt == Rt2)
@@ -1335,7 +1335,7 @@ static DecodeStatus DecodeAddSubERegInst
break;
}
- Inst.addOperand(MCOperand::CreateImm(extend));
+ Inst.addOperand(MCOperand::createImm(extend));
return Success;
}
@@ -1366,7 +1366,7 @@ static DecodeStatus DecodeLogicalImmInst
if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 32))
return Fail;
}
- Inst.addOperand(MCOperand::CreateImm(imm));
+ Inst.addOperand(MCOperand::createImm(imm));
return Success;
}
@@ -1383,7 +1383,7 @@ static DecodeStatus DecodeModImmInstruct
else
DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder);
- Inst.addOperand(MCOperand::CreateImm(imm));
+ Inst.addOperand(MCOperand::createImm(imm));
switch (Inst.getOpcode()) {
default:
@@ -1396,13 +1396,13 @@ static DecodeStatus DecodeModImmInstruct
case AArch64::MOVIv4i32:
case AArch64::MVNIv2i32:
case AArch64::MVNIv4i32:
- Inst.addOperand(MCOperand::CreateImm((cmode & 6) << 2));
+ Inst.addOperand(MCOperand::createImm((cmode & 6) << 2));
break;
case AArch64::MOVIv2s_msl:
case AArch64::MOVIv4s_msl:
case AArch64::MVNIv2s_msl:
case AArch64::MVNIv4s_msl:
- Inst.addOperand(MCOperand::CreateImm(cmode & 1 ? 0x110 : 0x108));
+ Inst.addOperand(MCOperand::createImm(cmode & 1 ? 0x110 : 0x108));
break;
}
@@ -1421,8 +1421,8 @@ static DecodeStatus DecodeModImmTiedInst
DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder);
DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder);
- Inst.addOperand(MCOperand::CreateImm(imm));
- Inst.addOperand(MCOperand::CreateImm((cmode & 6) << 2));
+ Inst.addOperand(MCOperand::createImm(imm));
+ Inst.addOperand(MCOperand::createImm((cmode & 6) << 2));
return Success;
}
@@ -1441,7 +1441,7 @@ static DecodeStatus DecodeAdrInstruction
DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
if (!Dis->tryAddingSymbolicOperand(Inst, imm, Addr, Fail, 0, 4))
- Inst.addOperand(MCOperand::CreateImm(imm));
+ Inst.addOperand(MCOperand::createImm(imm));
return Success;
}
@@ -1477,8 +1477,8 @@ static DecodeStatus DecodeBaseAddSubImm(
}
if (!Dis->tryAddingSymbolicOperand(Inst, Imm, Addr, Fail, 0, 4))
- Inst.addOperand(MCOperand::CreateImm(ImmVal));
- Inst.addOperand(MCOperand::CreateImm(12 * ShifterVal));
+ Inst.addOperand(MCOperand::createImm(ImmVal));
+ Inst.addOperand(MCOperand::createImm(12 * ShifterVal));
return Success;
}
@@ -1494,7 +1494,7 @@ static DecodeStatus DecodeUnconditionalB
imm |= ~((1LL << 26) - 1);
if (!Dis->tryAddingSymbolicOperand(Inst, imm * 4, Addr, true, 0, 4))
- Inst.addOperand(MCOperand::CreateImm(imm));
+ Inst.addOperand(MCOperand::createImm(imm));
return Success;
}
@@ -1508,8 +1508,8 @@ static DecodeStatus DecodeSystemPStateIn
uint64_t pstate_field = (op1 << 3) | op2;
- Inst.addOperand(MCOperand::CreateImm(pstate_field));
- Inst.addOperand(MCOperand::CreateImm(crm));
+ Inst.addOperand(MCOperand::createImm(pstate_field));
+ Inst.addOperand(MCOperand::createImm(crm));
bool ValidNamed;
const AArch64Disassembler *Dis =
@@ -1537,9 +1537,9 @@ static DecodeStatus DecodeTestAndBranch(
DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
else
DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
- Inst.addOperand(MCOperand::CreateImm(bit));
+ Inst.addOperand(MCOperand::createImm(bit));
if (!Dis->tryAddingSymbolicOperand(Inst, dst * 4, Addr, true, 0, 4))
- Inst.addOperand(MCOperand::CreateImm(dst));
+ Inst.addOperand(MCOperand::createImm(dst));
return Success;
}
Modified: llvm/trunk/lib/Target/AArch64/Disassembler/AArch64ExternalSymbolizer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/Disassembler/AArch64ExternalSymbolizer.cpp?rev=237275&r1=237274&r2=237275&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/Disassembler/AArch64ExternalSymbolizer.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/Disassembler/AArch64ExternalSymbolizer.cpp Wed May 13 13:37:00 2015
@@ -214,7 +214,7 @@ bool AArch64ExternalSymbolizer::tryAddin
Expr = MCConstantExpr::Create(0, Ctx);
}
- MI.addOperand(MCOperand::CreateExpr(Expr));
+ MI.addOperand(MCOperand::createExpr(Expr));
return true;
}
Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=237275&r1=237274&r2=237275&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Wed May 13 13:37:00 2015
@@ -1334,7 +1334,7 @@ void ARMAsmPrinter::EmitInstruction(cons
case ARM::t2MOVi16_ga_pcrel: {
MCInst TmpInst;
TmpInst.setOpcode(Opc == ARM::MOVi16_ga_pcrel? ARM::MOVi16 : ARM::t2MOVi16);
- TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
+ TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
unsigned TF = MI->getOperand(1).getTargetFlags();
const GlobalValue *GV = MI->getOperand(1).getGlobal();
@@ -1351,13 +1351,13 @@ void ARMAsmPrinter::EmitInstruction(cons
MCBinaryExpr::CreateAdd(LabelSymExpr,
MCConstantExpr::Create(PCAdj, OutContext),
OutContext), OutContext), OutContext);
- TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
+ TmpInst.addOperand(MCOperand::createExpr(PCRelExpr));
// Add predicate operands.
- TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
- TmpInst.addOperand(MCOperand::CreateReg(0));
+ TmpInst.addOperand(MCOperand::createImm(ARMCC::AL));
+ TmpInst.addOperand(MCOperand::createReg(0));
// Add 's' bit operand (always reg0 for this)
- TmpInst.addOperand(MCOperand::CreateReg(0));
+ TmpInst.addOperand(MCOperand::createReg(0));
EmitToStreamer(*OutStreamer, TmpInst);
return;
}
@@ -1366,8 +1366,8 @@ void ARMAsmPrinter::EmitInstruction(cons
MCInst TmpInst;
TmpInst.setOpcode(Opc == ARM::MOVTi16_ga_pcrel
? ARM::MOVTi16 : ARM::t2MOVTi16);
- TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
- TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
+ TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
+ TmpInst.addOperand(MCOperand::createReg(MI->getOperand(1).getReg()));
unsigned TF = MI->getOperand(2).getTargetFlags();
const GlobalValue *GV = MI->getOperand(2).getGlobal();
@@ -1384,12 +1384,12 @@ void ARMAsmPrinter::EmitInstruction(cons
MCBinaryExpr::CreateAdd(LabelSymExpr,
MCConstantExpr::Create(PCAdj, OutContext),
OutContext), OutContext), OutContext);
- TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
+ TmpInst.addOperand(MCOperand::createExpr(PCRelExpr));
// Add predicate operands.
- TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
- TmpInst.addOperand(MCOperand::CreateReg(0));
+ TmpInst.addOperand(MCOperand::createImm(ARMCC::AL));
+ TmpInst.addOperand(MCOperand::createReg(0));
// Add 's' bit operand (always reg0 for this)
- TmpInst.addOperand(MCOperand::CreateReg(0));
+ TmpInst.addOperand(MCOperand::createReg(0));
EmitToStreamer(*OutStreamer, TmpInst);
return;
}
@@ -1557,14 +1557,14 @@ void ARMAsmPrinter::EmitInstruction(cons
unsigned Opc = MI->getOpcode() == ARM::BR_JTr ?
ARM::MOVr : ARM::tMOVr;
TmpInst.setOpcode(Opc);
- TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
- TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
+ TmpInst.addOperand(MCOperand::createReg(ARM::PC));
+ TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
// Add predicate operands.
- TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
- TmpInst.addOperand(MCOperand::CreateReg(0));
+ TmpInst.addOperand(MCOperand::createImm(ARMCC::AL));
+ TmpInst.addOperand(MCOperand::createReg(0));
// Add 's' bit operand (always reg0 for this)
if (Opc == ARM::MOVr)
- TmpInst.addOperand(MCOperand::CreateReg(0));
+ TmpInst.addOperand(MCOperand::createReg(0));
EmitToStreamer(*OutStreamer, TmpInst);
// Make sure the Thumb jump table is 4-byte aligned.
@@ -1582,19 +1582,19 @@ void ARMAsmPrinter::EmitInstruction(cons
if (MI->getOperand(1).getReg() == 0) {
// literal offset
TmpInst.setOpcode(ARM::LDRi12);
- TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
- TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
- TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
+ TmpInst.addOperand(MCOperand::createReg(ARM::PC));
+ TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
+ TmpInst.addOperand(MCOperand::createImm(MI->getOperand(2).getImm()));
} else {
TmpInst.setOpcode(ARM::LDRrs);
- TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
- TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
- TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
- TmpInst.addOperand(MCOperand::CreateImm(0));
+ TmpInst.addOperand(MCOperand::createReg(ARM::PC));
+ TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
+ TmpInst.addOperand(MCOperand::createReg(MI->getOperand(1).getReg()));
+ TmpInst.addOperand(MCOperand::createImm(0));
}
// Add predicate operands.
- TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
- TmpInst.addOperand(MCOperand::CreateReg(0));
+ TmpInst.addOperand(MCOperand::createImm(ARMCC::AL));
+ TmpInst.addOperand(MCOperand::createReg(0));
EmitToStreamer(*OutStreamer, TmpInst);
// Output the data for the jump table itself
Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp?rev=237275&r1=237274&r2=237275&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp Wed May 13 13:37:00 2015
@@ -36,16 +36,16 @@ ARMInstrInfo::ARMInstrInfo(const ARMSubt
void ARMInstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
if (hasNOP()) {
NopInst.setOpcode(ARM::HINT);
- NopInst.addOperand(MCOperand::CreateImm(0));
- NopInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
- NopInst.addOperand(MCOperand::CreateReg(0));
+ NopInst.addOperand(MCOperand::createImm(0));
+ NopInst.addOperand(MCOperand::createImm(ARMCC::AL));
+ NopInst.addOperand(MCOperand::createReg(0));
} else {
NopInst.setOpcode(ARM::MOVr);
- NopInst.addOperand(MCOperand::CreateReg(ARM::R0));
- NopInst.addOperand(MCOperand::CreateReg(ARM::R0));
- NopInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
- NopInst.addOperand(MCOperand::CreateReg(0));
- NopInst.addOperand(MCOperand::CreateReg(0));
+ NopInst.addOperand(MCOperand::createReg(ARM::R0));
+ NopInst.addOperand(MCOperand::createReg(ARM::R0));
+ NopInst.addOperand(MCOperand::createImm(ARMCC::AL));
+ NopInst.addOperand(MCOperand::createReg(0));
+ NopInst.addOperand(MCOperand::createReg(0));
}
}
Modified: llvm/trunk/lib/Target/ARM/ARMMCInstLower.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMCInstLower.cpp?rev=237275&r1=237274&r2=237275&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMMCInstLower.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMMCInstLower.cpp Wed May 13 13:37:00 2015
@@ -61,7 +61,7 @@ MCOperand ARMAsmPrinter::GetSymbolRef(co
MCConstantExpr::Create(MO.getOffset(),
OutContext),
OutContext);
- return MCOperand::CreateExpr(Expr);
+ return MCOperand::createExpr(Expr);
}
@@ -74,13 +74,13 @@ bool ARMAsmPrinter::lowerOperand(const M
if (MO.isImplicit() && MO.getReg() != ARM::CPSR)
return false;
assert(!MO.getSubReg() && "Subregs should be eliminated!");
- MCOp = MCOperand::CreateReg(MO.getReg());
+ MCOp = MCOperand::createReg(MO.getReg());
break;
case MachineOperand::MO_Immediate:
- MCOp = MCOperand::CreateImm(MO.getImm());
+ MCOp = MCOperand::createImm(MO.getImm());
break;
case MachineOperand::MO_MachineBasicBlock:
- MCOp = MCOperand::CreateExpr(MCSymbolRefExpr::Create(
+ MCOp = MCOperand::createExpr(MCSymbolRefExpr::Create(
MO.getMBB()->getSymbol(), OutContext));
break;
case MachineOperand::MO_GlobalAddress: {
@@ -105,7 +105,7 @@ bool ARMAsmPrinter::lowerOperand(const M
APFloat Val = MO.getFPImm()->getValueAPF();
bool ignored;
Val.convert(APFloat::IEEEdouble, APFloat::rmTowardZero, &ignored);
- MCOp = MCOperand::CreateFPImm(Val.convertToDouble());
+ MCOp = MCOperand::createFPImm(Val.convertToDouble());
break;
}
case MachineOperand::MO_RegisterMask:
Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=237275&r1=237274&r2=237275&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Wed May 13 13:37:00 2015
@@ -1749,62 +1749,62 @@ public:
void addExpr(MCInst &Inst, const MCExpr *Expr) const {
// Add as immediates when possible. Null MCExpr = 0.
if (!Expr)
- Inst.addOperand(MCOperand::CreateImm(0));
+ Inst.addOperand(MCOperand::createImm(0));
else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
- Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
+ Inst.addOperand(MCOperand::createImm(CE->getValue()));
else
- Inst.addOperand(MCOperand::CreateExpr(Expr));
+ Inst.addOperand(MCOperand::createExpr(Expr));
}
void addCondCodeOperands(MCInst &Inst, unsigned N) const {
assert(N == 2 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
+ Inst.addOperand(MCOperand::createImm(unsigned(getCondCode())));
unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
- Inst.addOperand(MCOperand::CreateReg(RegNum));
+ Inst.addOperand(MCOperand::createReg(RegNum));
}
void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateImm(getCoproc()));
+ Inst.addOperand(MCOperand::createImm(getCoproc()));
}
void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateImm(getCoproc()));
+ Inst.addOperand(MCOperand::createImm(getCoproc()));
}
void addCoprocOptionOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateImm(CoprocOption.Val));
+ Inst.addOperand(MCOperand::createImm(CoprocOption.Val));
}
void addITMaskOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateImm(ITMask.Mask));
+ Inst.addOperand(MCOperand::createImm(ITMask.Mask));
}
void addITCondCodeOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
+ Inst.addOperand(MCOperand::createImm(unsigned(getCondCode())));
}
void addCCOutOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateReg(getReg()));
+ Inst.addOperand(MCOperand::createReg(getReg()));
}
void addRegOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateReg(getReg()));
+ Inst.addOperand(MCOperand::createReg(getReg()));
}
void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
assert(N == 3 && "Invalid number of operands!");
assert(isRegShiftedReg() &&
"addRegShiftedRegOperands() on non-RegShiftedReg!");
- Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg));
- Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg));
- Inst.addOperand(MCOperand::CreateImm(
+ Inst.addOperand(MCOperand::createReg(RegShiftedReg.SrcReg));
+ Inst.addOperand(MCOperand::createReg(RegShiftedReg.ShiftReg));
+ Inst.addOperand(MCOperand::createImm(
ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
}
@@ -1812,16 +1812,16 @@ public:
assert(N == 2 && "Invalid number of operands!");
assert(isRegShiftedImm() &&
"addRegShiftedImmOperands() on non-RegShiftedImm!");
- Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg));
+ Inst.addOperand(MCOperand::createReg(RegShiftedImm.SrcReg));
// Shift of #32 is encoded as 0 where permitted
unsigned Imm = (RegShiftedImm.ShiftImm == 32 ? 0 : RegShiftedImm.ShiftImm);
- Inst.addOperand(MCOperand::CreateImm(
+ Inst.addOperand(MCOperand::createImm(
ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, Imm)));
}
void addShifterImmOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) |
+ Inst.addOperand(MCOperand::createImm((ShifterImm.isASR << 5) |
ShifterImm.Imm));
}
@@ -1830,7 +1830,7 @@ public:
const SmallVectorImpl<unsigned> &RegList = getRegList();
for (SmallVectorImpl<unsigned>::const_iterator
I = RegList.begin(), E = RegList.end(); I != E; ++I)
- Inst.addOperand(MCOperand::CreateReg(*I));
+ Inst.addOperand(MCOperand::createReg(*I));
}
void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
@@ -1844,7 +1844,7 @@ public:
void addRotImmOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
// Encoded as val>>3. The printer handles display as 8, 16, 24.
- Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3));
+ Inst.addOperand(MCOperand::createImm(RotImm.Imm >> 3));
}
void addModImmOperands(MCInst &Inst, unsigned N) const {
@@ -1854,21 +1854,21 @@ public:
if (isImm())
return addImmOperands(Inst, N);
- Inst.addOperand(MCOperand::CreateImm(ModImm.Bits | (ModImm.Rot << 7)));
+ Inst.addOperand(MCOperand::createImm(ModImm.Bits | (ModImm.Rot << 7)));
}
void addModImmNotOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
uint32_t Enc = ARM_AM::getSOImmVal(~CE->getValue());
- Inst.addOperand(MCOperand::CreateImm(Enc));
+ Inst.addOperand(MCOperand::createImm(Enc));
}
void addModImmNegOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
uint32_t Enc = ARM_AM::getSOImmVal(-CE->getValue());
- Inst.addOperand(MCOperand::CreateImm(Enc));
+ Inst.addOperand(MCOperand::createImm(Enc));
}
void addBitfieldOperands(MCInst &Inst, unsigned N) const {
@@ -1879,7 +1879,7 @@ public:
// Make a 32-bit mask w/ the referenced bits clear and all other bits set.
uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >>
(32 - (lsb + width)));
- Inst.addOperand(MCOperand::CreateImm(Mask));
+ Inst.addOperand(MCOperand::createImm(Mask));
}
void addImmOperands(MCInst &Inst, unsigned N) const {
@@ -1890,20 +1890,20 @@ public:
void addFBits16Operands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
- Inst.addOperand(MCOperand::CreateImm(16 - CE->getValue()));
+ Inst.addOperand(MCOperand::createImm(16 - CE->getValue()));
}
void addFBits32Operands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
- Inst.addOperand(MCOperand::CreateImm(32 - CE->getValue()));
+ Inst.addOperand(MCOperand::createImm(32 - CE->getValue()));
}
void addFPImmOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
- Inst.addOperand(MCOperand::CreateImm(Val));
+ Inst.addOperand(MCOperand::createImm(Val));
}
void addImm8s4Operands(MCInst &Inst, unsigned N) const {
@@ -1911,7 +1911,7 @@ public:
// FIXME: We really want to scale the value here, but the LDRD/STRD
// instruction don't encode operands that way yet.
const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
- Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
+ Inst.addOperand(MCOperand::createImm(CE->getValue()));
}
void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const {
@@ -1919,7 +1919,7 @@ public:
// The immediate is scaled by four in the encoding and is stored
// in the MCInst as such. Lop off the low two bits here.
const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
- Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
+ Inst.addOperand(MCOperand::createImm(CE->getValue() / 4));
}
void addImm0_508s4NegOperands(MCInst &Inst, unsigned N) const {
@@ -1927,7 +1927,7 @@ public:
// The immediate is scaled by four in the encoding and is stored
// in the MCInst as such. Lop off the low two bits here.
const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
- Inst.addOperand(MCOperand::CreateImm(-(CE->getValue() / 4)));
+ Inst.addOperand(MCOperand::createImm(-(CE->getValue() / 4)));
}
void addImm0_508s4Operands(MCInst &Inst, unsigned N) const {
@@ -1935,7 +1935,7 @@ public:
// The immediate is scaled by four in the encoding and is stored
// in the MCInst as such. Lop off the low two bits here.
const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
- Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
+ Inst.addOperand(MCOperand::createImm(CE->getValue() / 4));
}
void addImm1_16Operands(MCInst &Inst, unsigned N) const {
@@ -1943,7 +1943,7 @@ public:
// The constant encodes as the immediate-1, and we store in the instruction
// the bits as encoded, so subtract off one here.
const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
- Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
+ Inst.addOperand(MCOperand::createImm(CE->getValue() - 1));
}
void addImm1_32Operands(MCInst &Inst, unsigned N) const {
@@ -1951,7 +1951,7 @@ public:
// The constant encodes as the immediate-1, and we store in the instruction
// the bits as encoded, so subtract off one here.
const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
- Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
+ Inst.addOperand(MCOperand::createImm(CE->getValue() - 1));
}
void addImmThumbSROperands(MCInst &Inst, unsigned N) const {
@@ -1960,7 +1960,7 @@ public:
// zero.
const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
unsigned Imm = CE->getValue();
- Inst.addOperand(MCOperand::CreateImm((Imm == 32 ? 0 : Imm)));
+ Inst.addOperand(MCOperand::createImm((Imm == 32 ? 0 : Imm)));
}
void addPKHASRImmOperands(MCInst &Inst, unsigned N) const {
@@ -1969,7 +1969,7 @@ public:
// the instruction as well.
const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
int Val = CE->getValue();
- Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val));
+ Inst.addOperand(MCOperand::createImm(Val == 32 ? 0 : Val));
}
void addT2SOImmNotOperands(MCInst &Inst, unsigned N) const {
@@ -1977,7 +1977,7 @@ public:
// The operand is actually a t2_so_imm, but we have its bitwise
// negation in the assembly source, so twiddle it here.
const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
- Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
+ Inst.addOperand(MCOperand::createImm(~CE->getValue()));
}
void addT2SOImmNegOperands(MCInst &Inst, unsigned N) const {
@@ -1985,7 +1985,7 @@ public:
// The operand is actually a t2_so_imm, but we have its
// negation in the assembly source, so twiddle it here.
const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
- Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
+ Inst.addOperand(MCOperand::createImm(-CE->getValue()));
}
void addImm0_4095NegOperands(MCInst &Inst, unsigned N) const {
@@ -1993,18 +1993,18 @@ public:
// The operand is actually an imm0_4095, but we have its
// negation in the assembly source, so twiddle it here.
const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
- Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
+ Inst.addOperand(MCOperand::createImm(-CE->getValue()));
}
void addUnsignedOffset_b8s2Operands(MCInst &Inst, unsigned N) const {
if(const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm())) {
- Inst.addOperand(MCOperand::CreateImm(CE->getValue() >> 2));
+ Inst.addOperand(MCOperand::createImm(CE->getValue() >> 2));
return;
}
const MCSymbolRefExpr *SR = dyn_cast<MCSymbolRefExpr>(Imm.Val);
assert(SR && "Unknown value type!");
- Inst.addOperand(MCOperand::CreateExpr(SR));
+ Inst.addOperand(MCOperand::createExpr(SR));
}
void addThumbMemPCOperands(MCInst &Inst, unsigned N) const {
@@ -2012,40 +2012,40 @@ public:
if (isImm()) {
const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
if (CE) {
- Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
+ Inst.addOperand(MCOperand::createImm(CE->getValue()));
return;
}
const MCSymbolRefExpr *SR = dyn_cast<MCSymbolRefExpr>(Imm.Val);
assert(SR && "Unknown value type!");
- Inst.addOperand(MCOperand::CreateExpr(SR));
+ Inst.addOperand(MCOperand::createExpr(SR));
return;
}
assert(isMem() && "Unknown value type!");
assert(isa<MCConstantExpr>(Memory.OffsetImm) && "Unknown value type!");
- Inst.addOperand(MCOperand::CreateImm(Memory.OffsetImm->getValue()));
+ Inst.addOperand(MCOperand::createImm(Memory.OffsetImm->getValue()));
}
void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt())));
+ Inst.addOperand(MCOperand::createImm(unsigned(getMemBarrierOpt())));
}
void addInstSyncBarrierOptOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateImm(unsigned(getInstSyncBarrierOpt())));
+ Inst.addOperand(MCOperand::createImm(unsigned(getInstSyncBarrierOpt())));
}
void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
+ Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
}
void addMemPCRelImm12Operands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
int32_t Imm = Memory.OffsetImm->getValue();
- Inst.addOperand(MCOperand::CreateImm(Imm));
+ Inst.addOperand(MCOperand::createImm(Imm));
}
void addAdrLabelOperands(MCInst &Inst, unsigned N) const {
@@ -2055,19 +2055,19 @@ public:
// If we have an immediate that's not a constant, treat it as a label
// reference needing a fixup.
if (!isa<MCConstantExpr>(getImm())) {
- Inst.addOperand(MCOperand::CreateExpr(getImm()));
+ Inst.addOperand(MCOperand::createExpr(getImm()));
return;
}
const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
int Val = CE->getValue();
- Inst.addOperand(MCOperand::CreateImm(Val));
+ Inst.addOperand(MCOperand::createImm(Val));
}
void addAlignedMemoryOperands(MCInst &Inst, unsigned N) const {
assert(N == 2 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
- Inst.addOperand(MCOperand::CreateImm(Memory.Alignment));
+ Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
+ Inst.addOperand(MCOperand::createImm(Memory.Alignment));
}
void addDupAlignedMemoryNoneOperands(MCInst &Inst, unsigned N) const {
@@ -2129,9 +2129,9 @@ public:
Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
Memory.ShiftImm, Memory.ShiftType);
}
- Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
- Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
- Inst.addOperand(MCOperand::CreateImm(Val));
+ Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
+ Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
+ Inst.addOperand(MCOperand::createImm(Val));
}
void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const {
@@ -2144,8 +2144,8 @@ public:
if (Val == INT32_MIN) Val = 0;
if (Val < 0) Val = -Val;
Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
- Inst.addOperand(MCOperand::CreateReg(0));
- Inst.addOperand(MCOperand::CreateImm(Val));
+ Inst.addOperand(MCOperand::createReg(0));
+ Inst.addOperand(MCOperand::createImm(Val));
}
void addAddrMode3Operands(MCInst &Inst, unsigned N) const {
@@ -2154,9 +2154,9 @@ public:
// reference needing a fixup. If it is a constant, it's something else
// and we reject it.
if (isImm()) {
- Inst.addOperand(MCOperand::CreateExpr(getImm()));
- Inst.addOperand(MCOperand::CreateReg(0));
- Inst.addOperand(MCOperand::CreateImm(0));
+ Inst.addOperand(MCOperand::createExpr(getImm()));
+ Inst.addOperand(MCOperand::createReg(0));
+ Inst.addOperand(MCOperand::createImm(0));
return;
}
@@ -2172,9 +2172,9 @@ public:
// here.
Val = ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0);
}
- Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
- Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
- Inst.addOperand(MCOperand::CreateImm(Val));
+ Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
+ Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
+ Inst.addOperand(MCOperand::createImm(Val));
}
void addAM3OffsetOperands(MCInst &Inst, unsigned N) const {
@@ -2182,8 +2182,8 @@ public:
if (Kind == k_PostIndexRegister) {
int32_t Val =
ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0);
- Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
- Inst.addOperand(MCOperand::CreateImm(Val));
+ Inst.addOperand(MCOperand::createReg(PostIdxReg.RegNum));
+ Inst.addOperand(MCOperand::createImm(Val));
return;
}
@@ -2195,8 +2195,8 @@ public:
if (Val == INT32_MIN) Val = 0;
if (Val < 0) Val = -Val;
Val = ARM_AM::getAM3Opc(AddSub, Val);
- Inst.addOperand(MCOperand::CreateReg(0));
- Inst.addOperand(MCOperand::CreateImm(Val));
+ Inst.addOperand(MCOperand::createReg(0));
+ Inst.addOperand(MCOperand::createImm(Val));
}
void addAddrMode5Operands(MCInst &Inst, unsigned N) const {
@@ -2205,8 +2205,8 @@ public:
// reference needing a fixup. If it is a constant, it's something else
// and we reject it.
if (isImm()) {
- Inst.addOperand(MCOperand::CreateExpr(getImm()));
- Inst.addOperand(MCOperand::CreateImm(0));
+ Inst.addOperand(MCOperand::createExpr(getImm()));
+ Inst.addOperand(MCOperand::createImm(0));
return;
}
@@ -2217,8 +2217,8 @@ public:
if (Val == INT32_MIN) Val = 0;
if (Val < 0) Val = -Val;
Val = ARM_AM::getAM5Opc(AddSub, Val);
- Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
- Inst.addOperand(MCOperand::CreateImm(Val));
+ Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
+ Inst.addOperand(MCOperand::createImm(Val));
}
void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const {
@@ -2227,29 +2227,29 @@ public:
// reference needing a fixup. If it is a constant, it's something else
// and we reject it.
if (isImm()) {
- Inst.addOperand(MCOperand::CreateExpr(getImm()));
- Inst.addOperand(MCOperand::CreateImm(0));
+ Inst.addOperand(MCOperand::createExpr(getImm()));
+ Inst.addOperand(MCOperand::createImm(0));
return;
}
int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
- Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
- Inst.addOperand(MCOperand::CreateImm(Val));
+ Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
+ Inst.addOperand(MCOperand::createImm(Val));
}
void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const {
assert(N == 2 && "Invalid number of operands!");
// The lower two bits are always zero and as such are not encoded.
int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
- Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
- Inst.addOperand(MCOperand::CreateImm(Val));
+ Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
+ Inst.addOperand(MCOperand::createImm(Val));
}
void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const {
assert(N == 2 && "Invalid number of operands!");
int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
- Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
- Inst.addOperand(MCOperand::CreateImm(Val));
+ Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
+ Inst.addOperand(MCOperand::createImm(Val));
}
void addMemPosImm8OffsetOperands(MCInst &Inst, unsigned N) const {
@@ -2265,14 +2265,14 @@ public:
// If this is an immediate, it's a label reference.
if (isImm()) {
addExpr(Inst, getImm());
- Inst.addOperand(MCOperand::CreateImm(0));
+ Inst.addOperand(MCOperand::createImm(0));
return;
}
// Otherwise, it's a normal memory reg+offset.
int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
- Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
- Inst.addOperand(MCOperand::CreateImm(Val));
+ Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
+ Inst.addOperand(MCOperand::createImm(Val));
}
void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const {
@@ -2280,26 +2280,26 @@ public:
// If this is an immediate, it's a label reference.
if (isImm()) {
addExpr(Inst, getImm());
- Inst.addOperand(MCOperand::CreateImm(0));
+ Inst.addOperand(MCOperand::createImm(0));
return;
}
// Otherwise, it's a normal memory reg+offset.
int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
- Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
- Inst.addOperand(MCOperand::CreateImm(Val));
+ Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
+ Inst.addOperand(MCOperand::createImm(Val));
}
void addMemTBBOperands(MCInst &Inst, unsigned N) const {
assert(N == 2 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
- Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
+ Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
+ Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
}
void addMemTBHOperands(MCInst &Inst, unsigned N) const {
assert(N == 2 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
- Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
+ Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
+ Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
}
void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const {
@@ -2307,50 +2307,50 @@ public:
unsigned Val =
ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
Memory.ShiftImm, Memory.ShiftType);
- Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
- Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
- Inst.addOperand(MCOperand::CreateImm(Val));
+ Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
+ Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
+ Inst.addOperand(MCOperand::createImm(Val));
}
void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const {
assert(N == 3 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
- Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
- Inst.addOperand(MCOperand::CreateImm(Memory.ShiftImm));
+ Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
+ Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
+ Inst.addOperand(MCOperand::createImm(Memory.ShiftImm));
}
void addMemThumbRROperands(MCInst &Inst, unsigned N) const {
assert(N == 2 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
- Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
+ Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
+ Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
}
void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const {
assert(N == 2 && "Invalid number of operands!");
int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
- Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
- Inst.addOperand(MCOperand::CreateImm(Val));
+ Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
+ Inst.addOperand(MCOperand::createImm(Val));
}
void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const {
assert(N == 2 && "Invalid number of operands!");
int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 2) : 0;
- Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
- Inst.addOperand(MCOperand::CreateImm(Val));
+ Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
+ Inst.addOperand(MCOperand::createImm(Val));
}
void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const {
assert(N == 2 && "Invalid number of operands!");
int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue()) : 0;
- Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
- Inst.addOperand(MCOperand::CreateImm(Val));
+ Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
+ Inst.addOperand(MCOperand::createImm(Val));
}
void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const {
assert(N == 2 && "Invalid number of operands!");
int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
- Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
- Inst.addOperand(MCOperand::CreateImm(Val));
+ Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
+ Inst.addOperand(MCOperand::createImm(Val));
}
void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const {
@@ -2361,7 +2361,7 @@ public:
bool isAdd = Imm >= 0;
if (Imm == INT32_MIN) Imm = 0;
Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8;
- Inst.addOperand(MCOperand::CreateImm(Imm));
+ Inst.addOperand(MCOperand::createImm(Imm));
}
void addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const {
@@ -2373,65 +2373,65 @@ public:
if (Imm == INT32_MIN) Imm = 0;
// Immediate is scaled by 4.
Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8;
- Inst.addOperand(MCOperand::CreateImm(Imm));
+ Inst.addOperand(MCOperand::createImm(Imm));
}
void addPostIdxRegOperands(MCInst &Inst, unsigned N) const {
assert(N == 2 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
- Inst.addOperand(MCOperand::CreateImm(PostIdxReg.isAdd));
+ Inst.addOperand(MCOperand::createReg(PostIdxReg.RegNum));
+ Inst.addOperand(MCOperand::createImm(PostIdxReg.isAdd));
}
void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const {
assert(N == 2 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
+ Inst.addOperand(MCOperand::createReg(PostIdxReg.RegNum));
// The sign, shift type, and shift amount are encoded in a single operand
// using the AM2 encoding helpers.
ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub;
unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm,
PostIdxReg.ShiftTy);
- Inst.addOperand(MCOperand::CreateImm(Imm));
+ Inst.addOperand(MCOperand::createImm(Imm));
}
void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask())));
+ Inst.addOperand(MCOperand::createImm(unsigned(getMSRMask())));
}
void addBankedRegOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateImm(unsigned(getBankedReg())));
+ Inst.addOperand(MCOperand::createImm(unsigned(getBankedReg())));
}
void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags())));
+ Inst.addOperand(MCOperand::createImm(unsigned(getProcIFlags())));
}
void addVecListOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
+ Inst.addOperand(MCOperand::createReg(VectorList.RegNum));
}
void addVecListIndexedOperands(MCInst &Inst, unsigned N) const {
assert(N == 2 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
- Inst.addOperand(MCOperand::CreateImm(VectorList.LaneIndex));
+ Inst.addOperand(MCOperand::createReg(VectorList.RegNum));
+ Inst.addOperand(MCOperand::createImm(VectorList.LaneIndex));
}
void addVectorIndex8Operands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
+ Inst.addOperand(MCOperand::createImm(getVectorIndex()));
}
void addVectorIndex16Operands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
+ Inst.addOperand(MCOperand::createImm(getVectorIndex()));
}
void addVectorIndex32Operands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
+ Inst.addOperand(MCOperand::createImm(getVectorIndex()));
}
void addNEONi8splatOperands(MCInst &Inst, unsigned N) const {
@@ -2439,7 +2439,7 @@ public:
// The immediate encodes the type of constant as well as the value.
// Mask in that this is an i8 splat.
const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
- Inst.addOperand(MCOperand::CreateImm(CE->getValue() | 0xe00));
+ Inst.addOperand(MCOperand::createImm(CE->getValue() | 0xe00));
}
void addNEONi16splatOperands(MCInst &Inst, unsigned N) const {
@@ -2448,7 +2448,7 @@ public:
const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
unsigned Value = CE->getValue();
Value = ARM_AM::encodeNEONi16splat(Value);
- Inst.addOperand(MCOperand::CreateImm(Value));
+ Inst.addOperand(MCOperand::createImm(Value));
}
void addNEONi16splatNotOperands(MCInst &Inst, unsigned N) const {
@@ -2457,7 +2457,7 @@ public:
const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
unsigned Value = CE->getValue();
Value = ARM_AM::encodeNEONi16splat(~Value & 0xffff);
- Inst.addOperand(MCOperand::CreateImm(Value));
+ Inst.addOperand(MCOperand::createImm(Value));
}
void addNEONi32splatOperands(MCInst &Inst, unsigned N) const {
@@ -2466,7 +2466,7 @@ public:
const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
unsigned Value = CE->getValue();
Value = ARM_AM::encodeNEONi32splat(Value);
- Inst.addOperand(MCOperand::CreateImm(Value));
+ Inst.addOperand(MCOperand::createImm(Value));
}
void addNEONi32splatNotOperands(MCInst &Inst, unsigned N) const {
@@ -2475,7 +2475,7 @@ public:
const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
unsigned Value = CE->getValue();
Value = ARM_AM::encodeNEONi32splat(~Value);
- Inst.addOperand(MCOperand::CreateImm(Value));
+ Inst.addOperand(MCOperand::createImm(Value));
}
void addNEONinvByteReplicateOperands(MCInst &Inst, unsigned N) const {
@@ -2489,7 +2489,7 @@ public:
"always must be replaced with VMOVv8i8 or VMOVv16i8.");
unsigned B = ((~Value) & 0xff);
B |= 0xe00; // cmode = 0b1110
- Inst.addOperand(MCOperand::CreateImm(B));
+ Inst.addOperand(MCOperand::createImm(B));
}
void addNEONi32vmovOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
@@ -2502,7 +2502,7 @@ public:
Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
else if (Value > 0xffffff)
Value = (Value >> 24) | 0x600;
- Inst.addOperand(MCOperand::CreateImm(Value));
+ Inst.addOperand(MCOperand::createImm(Value));
}
void addNEONvmovByteReplicateOperands(MCInst &Inst, unsigned N) const {
@@ -2516,7 +2516,7 @@ public:
"always must be replaced with VMOVv8i8 or VMOVv16i8.");
unsigned B = Value & 0xff;
B |= 0xe00; // cmode = 0b1110
- Inst.addOperand(MCOperand::CreateImm(B));
+ Inst.addOperand(MCOperand::createImm(B));
}
void addNEONi32vmovNegOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
@@ -2529,7 +2529,7 @@ public:
Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
else if (Value > 0xffffff)
Value = (Value >> 24) | 0x600;
- Inst.addOperand(MCOperand::CreateImm(Value));
+ Inst.addOperand(MCOperand::createImm(Value));
}
void addNEONi64splatOperands(MCInst &Inst, unsigned N) const {
@@ -2541,7 +2541,7 @@ public:
for (unsigned i = 0; i < 8; ++i, Value >>= 8) {
Imm |= (Value & 1) << i;
}
- Inst.addOperand(MCOperand::CreateImm(Imm | 0x1e00));
+ Inst.addOperand(MCOperand::createImm(Imm | 0x1e00));
}
void print(raw_ostream &OS) const override;
@@ -6705,8 +6705,8 @@ bool ARMAsmParser::processInstruction(MC
TmpInst.addOperand(Inst.getOperand(0));
TmpInst.addOperand(Inst.getOperand(1));
TmpInst.addOperand(Inst.getOperand(1));
- TmpInst.addOperand(MCOperand::CreateReg(0));
- TmpInst.addOperand(MCOperand::CreateImm(0));
+ TmpInst.addOperand(MCOperand::createReg(0));
+ TmpInst.addOperand(MCOperand::createImm(0));
TmpInst.addOperand(Inst.getOperand(2));
TmpInst.addOperand(Inst.getOperand(3));
Inst = TmpInst;
@@ -6723,8 +6723,8 @@ bool ARMAsmParser::processInstruction(MC
TmpInst.addOperand(Inst.getOperand(1));
TmpInst.addOperand(Inst.getOperand(0));
TmpInst.addOperand(Inst.getOperand(1));
- TmpInst.addOperand(MCOperand::CreateReg(0));
- TmpInst.addOperand(MCOperand::CreateImm(0));
+ TmpInst.addOperand(MCOperand::createReg(0));
+ TmpInst.addOperand(MCOperand::createImm(0));
TmpInst.addOperand(Inst.getOperand(2));
TmpInst.addOperand(Inst.getOperand(3));
Inst = TmpInst;
@@ -6743,7 +6743,7 @@ bool ARMAsmParser::processInstruction(MC
// Immediate (mod_imm) will be in its encoded form, we must unencode it
// before passing it to the ADR instruction.
unsigned Enc = Inst.getOperand(2).getImm();
- TmpInst.addOperand(MCOperand::CreateImm(
+ TmpInst.addOperand(MCOperand::createImm(
ARM_AM::rotr32(Enc & 0xFF, (Enc & 0xF00) >> 7)));
} else {
// Turn PC-relative expression into absolute expression.
@@ -6760,7 +6760,7 @@ bool ARMAsmParser::processInstruction(MC
getContext());
const MCExpr *FixupAddr = MCBinaryExpr::CreateAdd(ReadPC, OpExpr,
getContext());
- TmpInst.addOperand(MCOperand::CreateExpr(FixupAddr));
+ TmpInst.addOperand(MCOperand::createExpr(FixupAddr));
}
TmpInst.addOperand(Inst.getOperand(3));
TmpInst.addOperand(Inst.getOperand(4));
@@ -6826,7 +6826,7 @@ bool ARMAsmParser::processInstruction(MC
TmpInst.addOperand(Inst.getOperand(3)); // alignment
TmpInst.addOperand(Inst.getOperand(4)); // Rm
TmpInst.addOperand(Inst.getOperand(0)); // Vd
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing));
TmpInst.addOperand(Inst.getOperand(1)); // lane
TmpInst.addOperand(Inst.getOperand(5)); // CondCode
@@ -6850,9 +6850,9 @@ bool ARMAsmParser::processInstruction(MC
TmpInst.addOperand(Inst.getOperand(3)); // alignment
TmpInst.addOperand(Inst.getOperand(4)); // Rm
TmpInst.addOperand(Inst.getOperand(0)); // Vd
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing));
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing * 2));
TmpInst.addOperand(Inst.getOperand(1)); // lane
TmpInst.addOperand(Inst.getOperand(5)); // CondCode
@@ -6876,11 +6876,11 @@ bool ARMAsmParser::processInstruction(MC
TmpInst.addOperand(Inst.getOperand(3)); // alignment
TmpInst.addOperand(Inst.getOperand(4)); // Rm
TmpInst.addOperand(Inst.getOperand(0)); // Vd
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing));
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing * 2));
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing * 3));
TmpInst.addOperand(Inst.getOperand(1)); // lane
TmpInst.addOperand(Inst.getOperand(5)); // CondCode
@@ -6900,7 +6900,7 @@ bool ARMAsmParser::processInstruction(MC
TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
TmpInst.addOperand(Inst.getOperand(2)); // Rn
TmpInst.addOperand(Inst.getOperand(3)); // alignment
- TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
+ TmpInst.addOperand(MCOperand::createReg(0)); // Rm
TmpInst.addOperand(Inst.getOperand(0)); // Vd
TmpInst.addOperand(Inst.getOperand(1)); // lane
TmpInst.addOperand(Inst.getOperand(4)); // CondCode
@@ -6922,9 +6922,9 @@ bool ARMAsmParser::processInstruction(MC
TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
TmpInst.addOperand(Inst.getOperand(2)); // Rn
TmpInst.addOperand(Inst.getOperand(3)); // alignment
- TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
+ TmpInst.addOperand(MCOperand::createReg(0)); // Rm
TmpInst.addOperand(Inst.getOperand(0)); // Vd
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing));
TmpInst.addOperand(Inst.getOperand(1)); // lane
TmpInst.addOperand(Inst.getOperand(4)); // CondCode
@@ -6946,11 +6946,11 @@ bool ARMAsmParser::processInstruction(MC
TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
TmpInst.addOperand(Inst.getOperand(2)); // Rn
TmpInst.addOperand(Inst.getOperand(3)); // alignment
- TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
+ TmpInst.addOperand(MCOperand::createReg(0)); // Rm
TmpInst.addOperand(Inst.getOperand(0)); // Vd
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing));
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing * 2));
TmpInst.addOperand(Inst.getOperand(1)); // lane
TmpInst.addOperand(Inst.getOperand(4)); // CondCode
@@ -6972,13 +6972,13 @@ bool ARMAsmParser::processInstruction(MC
TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
TmpInst.addOperand(Inst.getOperand(2)); // Rn
TmpInst.addOperand(Inst.getOperand(3)); // alignment
- TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
+ TmpInst.addOperand(MCOperand::createReg(0)); // Rm
TmpInst.addOperand(Inst.getOperand(0)); // Vd
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing));
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing * 2));
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing * 3));
TmpInst.addOperand(Inst.getOperand(1)); // lane
TmpInst.addOperand(Inst.getOperand(4)); // CondCode
@@ -7018,7 +7018,7 @@ bool ARMAsmParser::processInstruction(MC
TmpInst.addOperand(Inst.getOperand(2)); // Rn
TmpInst.addOperand(Inst.getOperand(3)); // alignment
TmpInst.addOperand(Inst.getOperand(0)); // Vd
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing));
TmpInst.addOperand(Inst.getOperand(1)); // lane
TmpInst.addOperand(Inst.getOperand(4)); // CondCode
@@ -7040,9 +7040,9 @@ bool ARMAsmParser::processInstruction(MC
TmpInst.addOperand(Inst.getOperand(2)); // Rn
TmpInst.addOperand(Inst.getOperand(3)); // alignment
TmpInst.addOperand(Inst.getOperand(0)); // Vd
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing));
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing * 2));
TmpInst.addOperand(Inst.getOperand(1)); // lane
TmpInst.addOperand(Inst.getOperand(4)); // CondCode
@@ -7064,11 +7064,11 @@ bool ARMAsmParser::processInstruction(MC
TmpInst.addOperand(Inst.getOperand(2)); // Rn
TmpInst.addOperand(Inst.getOperand(3)); // alignment
TmpInst.addOperand(Inst.getOperand(0)); // Vd
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing));
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing * 2));
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing * 3));
TmpInst.addOperand(Inst.getOperand(1)); // lane
TmpInst.addOperand(Inst.getOperand(4)); // CondCode
@@ -7110,14 +7110,14 @@ bool ARMAsmParser::processInstruction(MC
unsigned Spacing;
TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
TmpInst.addOperand(Inst.getOperand(0)); // Vd
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing));
TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
TmpInst.addOperand(Inst.getOperand(2)); // Rn
TmpInst.addOperand(Inst.getOperand(3)); // alignment
TmpInst.addOperand(Inst.getOperand(4)); // Rm
TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing));
TmpInst.addOperand(Inst.getOperand(1)); // lane
TmpInst.addOperand(Inst.getOperand(5)); // CondCode
@@ -7137,18 +7137,18 @@ bool ARMAsmParser::processInstruction(MC
unsigned Spacing;
TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
TmpInst.addOperand(Inst.getOperand(0)); // Vd
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing));
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing * 2));
TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
TmpInst.addOperand(Inst.getOperand(2)); // Rn
TmpInst.addOperand(Inst.getOperand(3)); // alignment
TmpInst.addOperand(Inst.getOperand(4)); // Rm
TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing));
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing * 2));
TmpInst.addOperand(Inst.getOperand(1)); // lane
TmpInst.addOperand(Inst.getOperand(5)); // CondCode
@@ -7168,22 +7168,22 @@ bool ARMAsmParser::processInstruction(MC
unsigned Spacing;
TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
TmpInst.addOperand(Inst.getOperand(0)); // Vd
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing));
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing * 2));
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing * 3));
TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
TmpInst.addOperand(Inst.getOperand(2)); // Rn
TmpInst.addOperand(Inst.getOperand(3)); // alignment
TmpInst.addOperand(Inst.getOperand(4)); // Rm
TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing));
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing * 2));
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing * 3));
TmpInst.addOperand(Inst.getOperand(1)); // lane
TmpInst.addOperand(Inst.getOperand(5)); // CondCode
@@ -7204,7 +7204,7 @@ bool ARMAsmParser::processInstruction(MC
TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
TmpInst.addOperand(Inst.getOperand(2)); // Rn
TmpInst.addOperand(Inst.getOperand(3)); // alignment
- TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
+ TmpInst.addOperand(MCOperand::createReg(0)); // Rm
TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
TmpInst.addOperand(Inst.getOperand(1)); // lane
TmpInst.addOperand(Inst.getOperand(4)); // CondCode
@@ -7224,14 +7224,14 @@ bool ARMAsmParser::processInstruction(MC
unsigned Spacing;
TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
TmpInst.addOperand(Inst.getOperand(0)); // Vd
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing));
TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
TmpInst.addOperand(Inst.getOperand(2)); // Rn
TmpInst.addOperand(Inst.getOperand(3)); // alignment
- TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
+ TmpInst.addOperand(MCOperand::createReg(0)); // Rm
TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing));
TmpInst.addOperand(Inst.getOperand(1)); // lane
TmpInst.addOperand(Inst.getOperand(4)); // CondCode
@@ -7251,18 +7251,18 @@ bool ARMAsmParser::processInstruction(MC
unsigned Spacing;
TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
TmpInst.addOperand(Inst.getOperand(0)); // Vd
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing));
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing * 2));
TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
TmpInst.addOperand(Inst.getOperand(2)); // Rn
TmpInst.addOperand(Inst.getOperand(3)); // alignment
- TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
+ TmpInst.addOperand(MCOperand::createReg(0)); // Rm
TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing));
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing * 2));
TmpInst.addOperand(Inst.getOperand(1)); // lane
TmpInst.addOperand(Inst.getOperand(4)); // CondCode
@@ -7282,22 +7282,22 @@ bool ARMAsmParser::processInstruction(MC
unsigned Spacing;
TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
TmpInst.addOperand(Inst.getOperand(0)); // Vd
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing));
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing * 2));
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing * 3));
TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
TmpInst.addOperand(Inst.getOperand(2)); // Rn
TmpInst.addOperand(Inst.getOperand(3)); // alignment
- TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
+ TmpInst.addOperand(MCOperand::createReg(0)); // Rm
TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing));
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing * 2));
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing * 3));
TmpInst.addOperand(Inst.getOperand(1)); // lane
TmpInst.addOperand(Inst.getOperand(4)); // CondCode
@@ -7336,12 +7336,12 @@ bool ARMAsmParser::processInstruction(MC
unsigned Spacing;
TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
TmpInst.addOperand(Inst.getOperand(0)); // Vd
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing));
TmpInst.addOperand(Inst.getOperand(2)); // Rn
TmpInst.addOperand(Inst.getOperand(3)); // alignment
TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing));
TmpInst.addOperand(Inst.getOperand(1)); // lane
TmpInst.addOperand(Inst.getOperand(4)); // CondCode
@@ -7361,16 +7361,16 @@ bool ARMAsmParser::processInstruction(MC
unsigned Spacing;
TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
TmpInst.addOperand(Inst.getOperand(0)); // Vd
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing));
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing * 2));
TmpInst.addOperand(Inst.getOperand(2)); // Rn
TmpInst.addOperand(Inst.getOperand(3)); // alignment
TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing));
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing * 2));
TmpInst.addOperand(Inst.getOperand(1)); // lane
TmpInst.addOperand(Inst.getOperand(4)); // CondCode
@@ -7390,20 +7390,20 @@ bool ARMAsmParser::processInstruction(MC
unsigned Spacing;
TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
TmpInst.addOperand(Inst.getOperand(0)); // Vd
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing));
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing * 2));
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing * 3));
TmpInst.addOperand(Inst.getOperand(2)); // Rn
TmpInst.addOperand(Inst.getOperand(3)); // alignment
TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing));
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing * 2));
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing * 3));
TmpInst.addOperand(Inst.getOperand(1)); // lane
TmpInst.addOperand(Inst.getOperand(4)); // CondCode
@@ -7423,9 +7423,9 @@ bool ARMAsmParser::processInstruction(MC
unsigned Spacing;
TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
TmpInst.addOperand(Inst.getOperand(0)); // Vd
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing));
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing * 2));
TmpInst.addOperand(Inst.getOperand(1)); // Rn
TmpInst.addOperand(Inst.getOperand(2)); // alignment
@@ -7445,14 +7445,14 @@ bool ARMAsmParser::processInstruction(MC
unsigned Spacing;
TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
TmpInst.addOperand(Inst.getOperand(0)); // Vd
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing));
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing * 2));
TmpInst.addOperand(Inst.getOperand(1)); // Rn
TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
TmpInst.addOperand(Inst.getOperand(2)); // alignment
- TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
+ TmpInst.addOperand(MCOperand::createReg(0)); // Rm
TmpInst.addOperand(Inst.getOperand(3)); // CondCode
TmpInst.addOperand(Inst.getOperand(4));
Inst = TmpInst;
@@ -7469,9 +7469,9 @@ bool ARMAsmParser::processInstruction(MC
unsigned Spacing;
TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
TmpInst.addOperand(Inst.getOperand(0)); // Vd
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing));
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing * 2));
TmpInst.addOperand(Inst.getOperand(1)); // Rn
TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
@@ -7494,9 +7494,9 @@ bool ARMAsmParser::processInstruction(MC
unsigned Spacing;
TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
TmpInst.addOperand(Inst.getOperand(0)); // Vd
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing));
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing * 2));
TmpInst.addOperand(Inst.getOperand(1)); // Rn
TmpInst.addOperand(Inst.getOperand(2)); // alignment
@@ -7516,14 +7516,14 @@ bool ARMAsmParser::processInstruction(MC
unsigned Spacing;
TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
TmpInst.addOperand(Inst.getOperand(0)); // Vd
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing));
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing * 2));
TmpInst.addOperand(Inst.getOperand(1)); // Rn
TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
TmpInst.addOperand(Inst.getOperand(2)); // alignment
- TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
+ TmpInst.addOperand(MCOperand::createReg(0)); // Rm
TmpInst.addOperand(Inst.getOperand(3)); // CondCode
TmpInst.addOperand(Inst.getOperand(4));
Inst = TmpInst;
@@ -7540,9 +7540,9 @@ bool ARMAsmParser::processInstruction(MC
unsigned Spacing;
TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
TmpInst.addOperand(Inst.getOperand(0)); // Vd
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing));
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing * 2));
TmpInst.addOperand(Inst.getOperand(1)); // Rn
TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
@@ -7565,11 +7565,11 @@ bool ARMAsmParser::processInstruction(MC
unsigned Spacing;
TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
TmpInst.addOperand(Inst.getOperand(0)); // Vd
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing));
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing * 2));
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing * 3));
TmpInst.addOperand(Inst.getOperand(1)); // Rn
TmpInst.addOperand(Inst.getOperand(2)); // alignment
@@ -7589,16 +7589,16 @@ bool ARMAsmParser::processInstruction(MC
unsigned Spacing;
TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
TmpInst.addOperand(Inst.getOperand(0)); // Vd
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing));
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing * 2));
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing * 3));
TmpInst.addOperand(Inst.getOperand(1)); // Rn
TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
TmpInst.addOperand(Inst.getOperand(2)); // alignment
- TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
+ TmpInst.addOperand(MCOperand::createReg(0)); // Rm
TmpInst.addOperand(Inst.getOperand(3)); // CondCode
TmpInst.addOperand(Inst.getOperand(4));
Inst = TmpInst;
@@ -7615,11 +7615,11 @@ bool ARMAsmParser::processInstruction(MC
unsigned Spacing;
TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
TmpInst.addOperand(Inst.getOperand(0)); // Vd
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing));
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing * 2));
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing * 3));
TmpInst.addOperand(Inst.getOperand(1)); // Rn
TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
@@ -7642,11 +7642,11 @@ bool ARMAsmParser::processInstruction(MC
unsigned Spacing;
TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
TmpInst.addOperand(Inst.getOperand(0)); // Vd
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing));
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing * 2));
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing * 3));
TmpInst.addOperand(Inst.getOperand(1)); // Rn
TmpInst.addOperand(Inst.getOperand(2)); // alignment
@@ -7666,16 +7666,16 @@ bool ARMAsmParser::processInstruction(MC
unsigned Spacing;
TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
TmpInst.addOperand(Inst.getOperand(0)); // Vd
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing));
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing * 2));
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing * 3));
TmpInst.addOperand(Inst.getOperand(1)); // Rn
TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
TmpInst.addOperand(Inst.getOperand(2)); // alignment
- TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
+ TmpInst.addOperand(MCOperand::createReg(0)); // Rm
TmpInst.addOperand(Inst.getOperand(3)); // CondCode
TmpInst.addOperand(Inst.getOperand(4));
Inst = TmpInst;
@@ -7692,11 +7692,11 @@ bool ARMAsmParser::processInstruction(MC
unsigned Spacing;
TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
TmpInst.addOperand(Inst.getOperand(0)); // Vd
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing));
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing * 2));
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing * 3));
TmpInst.addOperand(Inst.getOperand(1)); // Rn
TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
@@ -7721,9 +7721,9 @@ bool ARMAsmParser::processInstruction(MC
TmpInst.addOperand(Inst.getOperand(1)); // Rn
TmpInst.addOperand(Inst.getOperand(2)); // alignment
TmpInst.addOperand(Inst.getOperand(0)); // Vd
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing));
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing * 2));
TmpInst.addOperand(Inst.getOperand(3)); // CondCode
TmpInst.addOperand(Inst.getOperand(4));
@@ -7743,11 +7743,11 @@ bool ARMAsmParser::processInstruction(MC
TmpInst.addOperand(Inst.getOperand(1)); // Rn
TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
TmpInst.addOperand(Inst.getOperand(2)); // alignment
- TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
+ TmpInst.addOperand(MCOperand::createReg(0)); // Rm
TmpInst.addOperand(Inst.getOperand(0)); // Vd
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing));
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing * 2));
TmpInst.addOperand(Inst.getOperand(3)); // CondCode
TmpInst.addOperand(Inst.getOperand(4));
@@ -7769,9 +7769,9 @@ bool ARMAsmParser::processInstruction(MC
TmpInst.addOperand(Inst.getOperand(2)); // alignment
TmpInst.addOperand(Inst.getOperand(3)); // Rm
TmpInst.addOperand(Inst.getOperand(0)); // Vd
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing));
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing * 2));
TmpInst.addOperand(Inst.getOperand(4)); // CondCode
TmpInst.addOperand(Inst.getOperand(5));
@@ -7792,11 +7792,11 @@ bool ARMAsmParser::processInstruction(MC
TmpInst.addOperand(Inst.getOperand(1)); // Rn
TmpInst.addOperand(Inst.getOperand(2)); // alignment
TmpInst.addOperand(Inst.getOperand(0)); // Vd
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing));
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing * 2));
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing * 3));
TmpInst.addOperand(Inst.getOperand(3)); // CondCode
TmpInst.addOperand(Inst.getOperand(4));
@@ -7816,13 +7816,13 @@ bool ARMAsmParser::processInstruction(MC
TmpInst.addOperand(Inst.getOperand(1)); // Rn
TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
TmpInst.addOperand(Inst.getOperand(2)); // alignment
- TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
+ TmpInst.addOperand(MCOperand::createReg(0)); // Rm
TmpInst.addOperand(Inst.getOperand(0)); // Vd
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing));
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing * 2));
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing * 3));
TmpInst.addOperand(Inst.getOperand(3)); // CondCode
TmpInst.addOperand(Inst.getOperand(4));
@@ -7844,11 +7844,11 @@ bool ARMAsmParser::processInstruction(MC
TmpInst.addOperand(Inst.getOperand(2)); // alignment
TmpInst.addOperand(Inst.getOperand(3)); // Rm
TmpInst.addOperand(Inst.getOperand(0)); // Vd
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing));
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing * 2));
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
Spacing * 3));
TmpInst.addOperand(Inst.getOperand(4)); // CondCode
TmpInst.addOperand(Inst.getOperand(5));
@@ -7912,14 +7912,14 @@ bool ARMAsmParser::processInstruction(MC
TmpInst.setOpcode(newOpc);
TmpInst.addOperand(Inst.getOperand(0)); // Rd
if (isNarrow)
- TmpInst.addOperand(MCOperand::CreateReg(
+ TmpInst.addOperand(MCOperand::createReg(
Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
TmpInst.addOperand(Inst.getOperand(1)); // Rn
TmpInst.addOperand(Inst.getOperand(2)); // Rm
TmpInst.addOperand(Inst.getOperand(4)); // CondCode
TmpInst.addOperand(Inst.getOperand(5));
if (!isNarrow)
- TmpInst.addOperand(MCOperand::CreateReg(
+ TmpInst.addOperand(MCOperand::createReg(
Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
Inst = TmpInst;
return true;
@@ -7949,15 +7949,15 @@ bool ARMAsmParser::processInstruction(MC
TmpInst.setOpcode(newOpc);
TmpInst.addOperand(Inst.getOperand(0)); // Rd
if (isNarrow)
- TmpInst.addOperand(MCOperand::CreateReg(
+ TmpInst.addOperand(MCOperand::createReg(
Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
TmpInst.addOperand(Inst.getOperand(1)); // Rn
if (newOpc != ARM::t2RRX)
- TmpInst.addOperand(MCOperand::CreateImm(Amount));
+ TmpInst.addOperand(MCOperand::createImm(Amount));
TmpInst.addOperand(Inst.getOperand(3)); // CondCode
TmpInst.addOperand(Inst.getOperand(4));
if (!isNarrow)
- TmpInst.addOperand(MCOperand::CreateReg(
+ TmpInst.addOperand(MCOperand::createReg(
Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
Inst = TmpInst;
return true;
@@ -7981,7 +7981,7 @@ bool ARMAsmParser::processInstruction(MC
TmpInst.addOperand(Inst.getOperand(0)); // Rd
TmpInst.addOperand(Inst.getOperand(1)); // Rn
TmpInst.addOperand(Inst.getOperand(2)); // Rm
- TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
+ TmpInst.addOperand(MCOperand::createImm(Shifter)); // Shift value and ty
TmpInst.addOperand(Inst.getOperand(3)); // CondCode
TmpInst.addOperand(Inst.getOperand(4));
TmpInst.addOperand(Inst.getOperand(5)); // cc_out
@@ -8012,7 +8012,7 @@ bool ARMAsmParser::processInstruction(MC
TmpInst.addOperand(Inst.getOperand(0)); // Rd
TmpInst.addOperand(Inst.getOperand(1)); // Rn
if (Opc == ARM::MOVsi)
- TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
+ TmpInst.addOperand(MCOperand::createImm(Shifter)); // Shift value and ty
TmpInst.addOperand(Inst.getOperand(3)); // CondCode
TmpInst.addOperand(Inst.getOperand(4));
TmpInst.addOperand(Inst.getOperand(5)); // cc_out
@@ -8025,7 +8025,7 @@ bool ARMAsmParser::processInstruction(MC
TmpInst.setOpcode(ARM::MOVsi);
TmpInst.addOperand(Inst.getOperand(0)); // Rd
TmpInst.addOperand(Inst.getOperand(1)); // Rn
- TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
+ TmpInst.addOperand(MCOperand::createImm(Shifter)); // Shift value and ty
TmpInst.addOperand(Inst.getOperand(2)); // CondCode
TmpInst.addOperand(Inst.getOperand(3));
TmpInst.addOperand(Inst.getOperand(4)); // cc_out
@@ -8042,7 +8042,7 @@ bool ARMAsmParser::processInstruction(MC
TmpInst.addOperand(Inst.getOperand(4)); // Rt
TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
TmpInst.addOperand(Inst.getOperand(1)); // Rn
- TmpInst.addOperand(MCOperand::CreateImm(4));
+ TmpInst.addOperand(MCOperand::createImm(4));
TmpInst.addOperand(Inst.getOperand(2)); // CondCode
TmpInst.addOperand(Inst.getOperand(3));
Inst = TmpInst;
@@ -8058,7 +8058,7 @@ bool ARMAsmParser::processInstruction(MC
TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
TmpInst.addOperand(Inst.getOperand(4)); // Rt
TmpInst.addOperand(Inst.getOperand(1)); // Rn
- TmpInst.addOperand(MCOperand::CreateImm(-4));
+ TmpInst.addOperand(MCOperand::createImm(-4));
TmpInst.addOperand(Inst.getOperand(2)); // CondCode
TmpInst.addOperand(Inst.getOperand(3));
Inst = TmpInst;
@@ -8074,8 +8074,8 @@ bool ARMAsmParser::processInstruction(MC
TmpInst.addOperand(Inst.getOperand(4)); // Rt
TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
TmpInst.addOperand(Inst.getOperand(1)); // Rn
- TmpInst.addOperand(MCOperand::CreateReg(0)); // am2offset
- TmpInst.addOperand(MCOperand::CreateImm(4));
+ TmpInst.addOperand(MCOperand::createReg(0)); // am2offset
+ TmpInst.addOperand(MCOperand::createImm(4));
TmpInst.addOperand(Inst.getOperand(2)); // CondCode
TmpInst.addOperand(Inst.getOperand(3));
Inst = TmpInst;
@@ -8092,7 +8092,7 @@ bool ARMAsmParser::processInstruction(MC
TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
TmpInst.addOperand(Inst.getOperand(4)); // Rt
TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12
- TmpInst.addOperand(MCOperand::CreateImm(-4));
+ TmpInst.addOperand(MCOperand::createImm(-4));
TmpInst.addOperand(Inst.getOperand(2)); // CondCode
TmpInst.addOperand(Inst.getOperand(3));
Inst = TmpInst;
@@ -8105,7 +8105,7 @@ bool ARMAsmParser::processInstruction(MC
ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
break;
Inst.setOpcode(ARM::t2ADDri);
- Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
+ Inst.addOperand(MCOperand::createReg(0)); // cc_out
break;
case ARM::t2SUBri12:
// If the immediate fits for encoding T3 (t2SUBri) and the generic "sub"
@@ -8114,7 +8114,7 @@ bool ARMAsmParser::processInstruction(MC
ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
break;
Inst.setOpcode(ARM::t2SUBri);
- Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
+ Inst.addOperand(MCOperand::createReg(0)); // cc_out
break;
case ARM::tADDi8:
// If the immediate is in the range 0-7, we want tADDi3 iff Rd was
@@ -8187,7 +8187,7 @@ bool ARMAsmParser::processInstruction(MC
// same, we need to use the 32-bit encoding if it's available.
if (Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
Inst.setOpcode(ARM::t2ADDrr);
- Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
+ Inst.addOperand(MCOperand::createReg(0)); // cc_out
return true;
}
break;
@@ -8240,7 +8240,7 @@ bool ARMAsmParser::processInstruction(MC
// the writeback tied operand.
if (hasWritebackToken)
Inst.insert(Inst.begin(),
- MCOperand::CreateReg(Inst.getOperand(0).getReg()));
+ MCOperand::createReg(Inst.getOperand(0).getReg()));
return true;
}
break;
@@ -8269,8 +8269,8 @@ bool ARMAsmParser::processInstruction(MC
assert (isThumbTwo());
Inst.setOpcode(ARM::t2LDMIA_UPD);
// Add the base register and writeback operands.
- Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
- Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
+ Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP));
+ Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP));
return true;
}
case ARM::tPUSH: {
@@ -8280,8 +8280,8 @@ bool ARMAsmParser::processInstruction(MC
assert (isThumbTwo());
Inst.setOpcode(ARM::t2STMDB_UPD);
// Add the base register and writeback operands.
- Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
- Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
+ Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP));
+ Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP));
return true;
}
case ARM::t2MOVi: {
Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp?rev=237275&r1=237274&r2=237275&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Wed May 13 13:37:00 2015
@@ -582,12 +582,12 @@ static void AddThumb1SBit(MCInst &MI, bo
if (I == MI.end()) break;
if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
if (i > 0 && OpInfo[i-1].isPredicate()) continue;
- MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
+ MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR));
return;
}
}
- MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
+ MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR));
}
// Most Thumb instructions don't have explicit predicates in the
@@ -646,22 +646,22 @@ ThumbDisassembler::AddThumbPredicate(MCI
for (unsigned i = 0; i < NumOps; ++i, ++I) {
if (I == MI.end()) break;
if (OpInfo[i].isPredicate()) {
- I = MI.insert(I, MCOperand::CreateImm(CC));
+ I = MI.insert(I, MCOperand::createImm(CC));
++I;
if (CC == ARMCC::AL)
- MI.insert(I, MCOperand::CreateReg(0));
+ MI.insert(I, MCOperand::createReg(0));
else
- MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
+ MI.insert(I, MCOperand::createReg(ARM::CPSR));
return S;
}
}
- I = MI.insert(I, MCOperand::CreateImm(CC));
+ I = MI.insert(I, MCOperand::createImm(CC));
++I;
if (CC == ARMCC::AL)
- MI.insert(I, MCOperand::CreateReg(0));
+ MI.insert(I, MCOperand::createReg(0));
else
- MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
+ MI.insert(I, MCOperand::createReg(ARM::CPSR));
return S;
}
@@ -894,7 +894,7 @@ static DecodeStatus DecodeGPRRegisterCla
return MCDisassembler::Fail;
unsigned Register = GPRDecoderTable[RegNo];
- Inst.addOperand(MCOperand::CreateReg(Register));
+ Inst.addOperand(MCOperand::createReg(Register));
return MCDisassembler::Success;
}
@@ -918,7 +918,7 @@ DecodeGPRwithAPSRRegisterClass(MCInst &I
if (RegNo == 15)
{
- Inst.addOperand(MCOperand::CreateReg(ARM::APSR_NZCV));
+ Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV));
return MCDisassembler::Success;
}
@@ -949,7 +949,7 @@ static DecodeStatus DecodeGPRPairRegiste
S = MCDisassembler::SoftFail;
unsigned RegisterPair = GPRPairDecoderTable[RegNo/2];
- Inst.addOperand(MCOperand::CreateReg(RegisterPair));
+ Inst.addOperand(MCOperand::createReg(RegisterPair));
return S;
}
@@ -979,7 +979,7 @@ static DecodeStatus DecodetcGPRRegisterC
return MCDisassembler::Fail;
}
- Inst.addOperand(MCOperand::CreateReg(Register));
+ Inst.addOperand(MCOperand::createReg(Register));
return MCDisassembler::Success;
}
@@ -1009,7 +1009,7 @@ static DecodeStatus DecodeSPRRegisterCla
return MCDisassembler::Fail;
unsigned Register = SPRDecoderTable[RegNo];
- Inst.addOperand(MCOperand::CreateReg(Register));
+ Inst.addOperand(MCOperand::createReg(Register));
return MCDisassembler::Success;
}
@@ -1034,7 +1034,7 @@ static DecodeStatus DecodeDPRRegisterCla
return MCDisassembler::Fail;
unsigned Register = DPRDecoderTable[RegNo];
- Inst.addOperand(MCOperand::CreateReg(Register));
+ Inst.addOperand(MCOperand::createReg(Register));
return MCDisassembler::Success;
}
@@ -1068,7 +1068,7 @@ static DecodeStatus DecodeQPRRegisterCla
RegNo >>= 1;
unsigned Register = QPRDecoderTable[RegNo];
- Inst.addOperand(MCOperand::CreateReg(Register));
+ Inst.addOperand(MCOperand::createReg(Register));
return MCDisassembler::Success;
}
@@ -1087,7 +1087,7 @@ static DecodeStatus DecodeDPairRegisterC
return MCDisassembler::Fail;
unsigned Register = DPairDecoderTable[RegNo];
- Inst.addOperand(MCOperand::CreateReg(Register));
+ Inst.addOperand(MCOperand::createReg(Register));
return MCDisassembler::Success;
}
@@ -1110,7 +1110,7 @@ static DecodeStatus DecodeDPairSpacedReg
return MCDisassembler::Fail;
unsigned Register = DPairSpacedDecoderTable[RegNo];
- Inst.addOperand(MCOperand::CreateReg(Register));
+ Inst.addOperand(MCOperand::createReg(Register));
return MCDisassembler::Success;
}
@@ -1120,20 +1120,20 @@ static DecodeStatus DecodePredicateOpera
// AL predicate is not allowed on Thumb1 branches.
if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateImm(Val));
+ Inst.addOperand(MCOperand::createImm(Val));
if (Val == ARMCC::AL) {
- Inst.addOperand(MCOperand::CreateReg(0));
+ Inst.addOperand(MCOperand::createReg(0));
} else
- Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
+ Inst.addOperand(MCOperand::createReg(ARM::CPSR));
return MCDisassembler::Success;
}
static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder) {
if (Val)
- Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
+ Inst.addOperand(MCOperand::createReg(ARM::CPSR));
else
- Inst.addOperand(MCOperand::CreateReg(0));
+ Inst.addOperand(MCOperand::createReg(0));
return MCDisassembler::Success;
}
@@ -1169,7 +1169,7 @@ static DecodeStatus DecodeSORegImmOperan
Shift = ARM_AM::rrx;
unsigned Op = Shift | (imm << 3);
- Inst.addOperand(MCOperand::CreateImm(Op));
+ Inst.addOperand(MCOperand::createImm(Op));
return S;
}
@@ -1204,7 +1204,7 @@ static DecodeStatus DecodeSORegRegOperan
break;
}
- Inst.addOperand(MCOperand::CreateImm(Shift));
+ Inst.addOperand(MCOperand::createImm(Shift));
return S;
}
@@ -1318,7 +1318,7 @@ static DecodeStatus DecodeBitfieldMaskOp
if (msb != 31) msb_mask = (1U << (msb+1)) - 1;
uint32_t lsb_mask = (1U << lsb) - 1;
- Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask)));
+ Inst.addOperand(MCOperand::createImm(~(msb_mask ^ lsb_mask)));
return S;
}
@@ -1378,8 +1378,8 @@ static DecodeStatus DecodeCopMemInstruct
if ((featureBits & ARM::HasV8Ops) && (coproc != 14))
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateImm(coproc));
- Inst.addOperand(MCOperand::CreateImm(CRd));
+ Inst.addOperand(MCOperand::createImm(coproc));
+ Inst.addOperand(MCOperand::createImm(CRd));
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail;
@@ -1417,7 +1417,7 @@ static DecodeStatus DecodeCopMemInstruct
case ARM::STC_PRE:
case ARM::STCL_PRE:
imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm);
- Inst.addOperand(MCOperand::CreateImm(imm));
+ Inst.addOperand(MCOperand::createImm(imm));
break;
case ARM::t2LDC2_POST:
case ARM::t2LDC2L_POST:
@@ -1440,7 +1440,7 @@ static DecodeStatus DecodeCopMemInstruct
default:
// The 'option' variant doesn't encode 'U' in the immediate since
// the immediate is unsigned [0,255].
- Inst.addOperand(MCOperand::CreateImm(imm));
+ Inst.addOperand(MCOperand::createImm(imm));
break;
}
@@ -1564,11 +1564,11 @@ DecodeAddrMode2IdxInstruction(MCInst &In
Opc = ARM_AM::rrx;
unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
- Inst.addOperand(MCOperand::CreateImm(imm));
+ Inst.addOperand(MCOperand::createImm(imm));
} else {
- Inst.addOperand(MCOperand::CreateReg(0));
+ Inst.addOperand(MCOperand::createReg(0));
unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode);
- Inst.addOperand(MCOperand::CreateImm(tmp));
+ Inst.addOperand(MCOperand::createImm(tmp));
}
if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
@@ -1615,7 +1615,7 @@ static DecodeStatus DecodeSORegMemOperan
shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
else
shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
- Inst.addOperand(MCOperand::CreateImm(shift));
+ Inst.addOperand(MCOperand::createImm(shift));
return S;
}
@@ -1798,12 +1798,12 @@ DecodeAddrMode3Instruction(MCInst &Inst,
return MCDisassembler::Fail;
if (type) {
- Inst.addOperand(MCOperand::CreateReg(0));
- Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm));
+ Inst.addOperand(MCOperand::createReg(0));
+ Inst.addOperand(MCOperand::createImm(U | (imm << 4) | Rm));
} else {
if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateImm(U));
+ Inst.addOperand(MCOperand::createImm(U));
}
if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
@@ -1834,7 +1834,7 @@ static DecodeStatus DecodeRFEInstruction
break;
}
- Inst.addOperand(MCOperand::CreateImm(mode));
+ Inst.addOperand(MCOperand::createImm(mode));
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail;
@@ -1936,7 +1936,7 @@ static DecodeStatus DecodeMemMultipleWri
return MCDisassembler::Fail;
Inst.addOperand(
- MCOperand::CreateImm(fieldFromInstruction(Insn, 0, 4)));
+ MCOperand::createImm(fieldFromInstruction(Insn, 0, 4)));
return S;
}
@@ -1980,22 +1980,22 @@ static DecodeStatus DecodeCPSInstruction
if (imod && M) {
Inst.setOpcode(ARM::CPS3p);
- Inst.addOperand(MCOperand::CreateImm(imod));
- Inst.addOperand(MCOperand::CreateImm(iflags));
- Inst.addOperand(MCOperand::CreateImm(mode));
+ Inst.addOperand(MCOperand::createImm(imod));
+ Inst.addOperand(MCOperand::createImm(iflags));
+ Inst.addOperand(MCOperand::createImm(mode));
} else if (imod && !M) {
Inst.setOpcode(ARM::CPS2p);
- Inst.addOperand(MCOperand::CreateImm(imod));
- Inst.addOperand(MCOperand::CreateImm(iflags));
+ Inst.addOperand(MCOperand::createImm(imod));
+ Inst.addOperand(MCOperand::createImm(iflags));
if (mode) S = MCDisassembler::SoftFail;
} else if (!imod && M) {
Inst.setOpcode(ARM::CPS1p);
- Inst.addOperand(MCOperand::CreateImm(mode));
+ Inst.addOperand(MCOperand::createImm(mode));
if (iflags) S = MCDisassembler::SoftFail;
} else {
// imod == '00' && M == '0' --> UNPREDICTABLE
Inst.setOpcode(ARM::CPS1p);
- Inst.addOperand(MCOperand::CreateImm(mode));
+ Inst.addOperand(MCOperand::createImm(mode));
S = MCDisassembler::SoftFail;
}
@@ -2020,17 +2020,17 @@ static DecodeStatus DecodeT2CPSInstructi
if (imod && M) {
Inst.setOpcode(ARM::t2CPS3p);
- Inst.addOperand(MCOperand::CreateImm(imod));
- Inst.addOperand(MCOperand::CreateImm(iflags));
- Inst.addOperand(MCOperand::CreateImm(mode));
+ Inst.addOperand(MCOperand::createImm(imod));
+ Inst.addOperand(MCOperand::createImm(iflags));
+ Inst.addOperand(MCOperand::createImm(mode));
} else if (imod && !M) {
Inst.setOpcode(ARM::t2CPS2p);
- Inst.addOperand(MCOperand::CreateImm(imod));
- Inst.addOperand(MCOperand::CreateImm(iflags));
+ Inst.addOperand(MCOperand::createImm(imod));
+ Inst.addOperand(MCOperand::createImm(iflags));
if (mode) S = MCDisassembler::SoftFail;
} else if (!imod && M) {
Inst.setOpcode(ARM::t2CPS1p);
- Inst.addOperand(MCOperand::CreateImm(mode));
+ Inst.addOperand(MCOperand::createImm(mode));
if (iflags) S = MCDisassembler::SoftFail;
} else {
// imod == '00' && M == '0' --> this is a HINT instruction
@@ -2038,7 +2038,7 @@ static DecodeStatus DecodeT2CPSInstructi
// HINT are defined only for immediate in [0..4]
if(imm > 4) return MCDisassembler::Fail;
Inst.setOpcode(ARM::t2HINT);
- Inst.addOperand(MCOperand::CreateImm(imm));
+ Inst.addOperand(MCOperand::createImm(imm));
}
return S;
@@ -2063,7 +2063,7 @@ static DecodeStatus DecodeT2MOVTWInstruc
return MCDisassembler::Fail;
if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
- Inst.addOperand(MCOperand::CreateImm(imm));
+ Inst.addOperand(MCOperand::createImm(imm));
return S;
}
@@ -2087,7 +2087,7 @@ static DecodeStatus DecodeArmMOVTWInstru
return MCDisassembler::Fail;
if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
- Inst.addOperand(MCOperand::CreateImm(imm));
+ Inst.addOperand(MCOperand::createImm(imm));
if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
return MCDisassembler::Fail;
@@ -2166,7 +2166,7 @@ static DecodeStatus DecodeSETPANInstruct
S = MCDisassembler::SoftFail;
Inst.setOpcode(ARM::SETPAN);
- Inst.addOperand(MCOperand::CreateImm(Imm));
+ Inst.addOperand(MCOperand::createImm(Imm));
return S;
}
@@ -2184,7 +2184,7 @@ static DecodeStatus DecodeAddrModeImm12O
if (!add) imm *= -1;
if (imm == 0 && !add) imm = INT32_MIN;
- Inst.addOperand(MCOperand::CreateImm(imm));
+ Inst.addOperand(MCOperand::createImm(imm));
if (Rn == 15)
tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder);
@@ -2203,9 +2203,9 @@ static DecodeStatus DecodeAddrMode5Opera
return MCDisassembler::Fail;
if (U)
- Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm)));
+ Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::add, imm)));
else
- Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm)));
+ Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm)));
return S;
}
@@ -2237,7 +2237,7 @@ DecodeT2BInstruction(MCInst &Inst, unsig
int imm32 = SignExtend32<25>(tmp << 1);
if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
true, 4, Inst, Decoder))
- Inst.addOperand(MCOperand::CreateImm(imm32));
+ Inst.addOperand(MCOperand::createImm(imm32));
return Status;
}
@@ -2255,13 +2255,13 @@ DecodeBranchImmInstruction(MCInst &Inst,
imm |= fieldFromInstruction(Insn, 24, 1) << 1;
if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
true, 4, Inst, Decoder))
- Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
+ Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm)));
return S;
}
if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
true, 4, Inst, Decoder))
- Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
+ Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm)));
if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
return MCDisassembler::Fail;
@@ -2279,9 +2279,9 @@ static DecodeStatus DecodeAddrMode6Opera
if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
return MCDisassembler::Fail;
if (!align)
- Inst.addOperand(MCOperand::CreateImm(0));
+ Inst.addOperand(MCOperand::createImm(0));
else
- Inst.addOperand(MCOperand::CreateImm(4 << align));
+ Inst.addOperand(MCOperand::createImm(4 << align));
return S;
}
@@ -2475,7 +2475,7 @@ static DecodeStatus DecodeVLDInstruction
case ARM::VLD2b8wb_register:
case ARM::VLD2b16wb_register:
case ARM::VLD2b32wb_register:
- Inst.addOperand(MCOperand::CreateImm(0));
+ Inst.addOperand(MCOperand::createImm(0));
break;
case ARM::VLD3d8_UPD:
case ARM::VLD3d16_UPD:
@@ -2510,7 +2510,7 @@ static DecodeStatus DecodeVLDInstruction
//
// The fixed offset encodes as Rm == 0xd, so we check for that.
if (Rm == 0xd) {
- Inst.addOperand(MCOperand::CreateReg(0));
+ Inst.addOperand(MCOperand::createReg(0));
break;
}
// Fall through to handle the register offset variant.
@@ -2676,7 +2676,7 @@ static DecodeStatus DecodeVSTInstruction
case ARM::VST2b32wb_register:
if (Rm == 0xF)
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateImm(0));
+ Inst.addOperand(MCOperand::createImm(0));
break;
case ARM::VST3d8_UPD:
case ARM::VST3d16_UPD:
@@ -2705,7 +2705,7 @@ static DecodeStatus DecodeVSTInstruction
switch (Inst.getOpcode()) {
default:
if (Rm == 0xD)
- Inst.addOperand(MCOperand::CreateReg(0));
+ Inst.addOperand(MCOperand::createReg(0));
else if (Rm != 0xF) {
if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
return MCDisassembler::Fail;
@@ -2917,7 +2917,7 @@ static DecodeStatus DecodeVLD1DupInstruc
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateImm(align));
+ Inst.addOperand(MCOperand::createImm(align));
// The fixed offset post-increment encodes Rm == 0xd. The no-writeback
// variant encodes Rm == 0xf. Anything else is a register offset post-
@@ -2963,11 +2963,11 @@ static DecodeStatus DecodeVLD2DupInstruc
}
if (Rm != 0xF)
- Inst.addOperand(MCOperand::CreateImm(0));
+ Inst.addOperand(MCOperand::createImm(0));
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateImm(align));
+ Inst.addOperand(MCOperand::createImm(align));
if (Rm != 0xD && Rm != 0xF) {
if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
@@ -3000,10 +3000,10 @@ static DecodeStatus DecodeVLD3DupInstruc
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateImm(0));
+ Inst.addOperand(MCOperand::createImm(0));
if (Rm == 0xD)
- Inst.addOperand(MCOperand::CreateReg(0));
+ Inst.addOperand(MCOperand::createReg(0));
else if (Rm != 0xF) {
if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
return MCDisassembler::Fail;
@@ -3052,10 +3052,10 @@ static DecodeStatus DecodeVLD4DupInstruc
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateImm(align));
+ Inst.addOperand(MCOperand::createImm(align));
if (Rm == 0xD)
- Inst.addOperand(MCOperand::CreateReg(0));
+ Inst.addOperand(MCOperand::createReg(0));
else if (Rm != 0xF) {
if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
return MCDisassembler::Fail;
@@ -3086,7 +3086,7 @@ DecodeNEONModImmInstruction(MCInst &Inst
return MCDisassembler::Fail;
}
- Inst.addOperand(MCOperand::CreateImm(imm));
+ Inst.addOperand(MCOperand::createImm(imm));
switch (Inst.getOpcode()) {
case ARM::VORRiv4i16:
@@ -3124,32 +3124,32 @@ static DecodeStatus DecodeVSHLMaxInstruc
return MCDisassembler::Fail;
if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateImm(8 << size));
+ Inst.addOperand(MCOperand::createImm(8 << size));
return S;
}
static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder) {
- Inst.addOperand(MCOperand::CreateImm(8 - Val));
+ Inst.addOperand(MCOperand::createImm(8 - Val));
return MCDisassembler::Success;
}
static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder) {
- Inst.addOperand(MCOperand::CreateImm(16 - Val));
+ Inst.addOperand(MCOperand::createImm(16 - Val));
return MCDisassembler::Success;
}
static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder) {
- Inst.addOperand(MCOperand::CreateImm(32 - Val));
+ Inst.addOperand(MCOperand::createImm(32 - Val));
return MCDisassembler::Success;
}
static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder) {
- Inst.addOperand(MCOperand::CreateImm(64 - Val));
+ Inst.addOperand(MCOperand::createImm(64 - Val));
return MCDisassembler::Success;
}
@@ -3205,11 +3205,11 @@ static DecodeStatus DecodeThumbAddSpecia
case ARM::tADR:
break; // tADR does not explicitly represent the PC as an operand.
case ARM::tADDrSPi:
- Inst.addOperand(MCOperand::CreateReg(ARM::SP));
+ Inst.addOperand(MCOperand::createReg(ARM::SP));
break;
}
- Inst.addOperand(MCOperand::CreateImm(imm));
+ Inst.addOperand(MCOperand::createImm(imm));
return S;
}
@@ -3217,7 +3217,7 @@ static DecodeStatus DecodeThumbBROperand
uint64_t Address, const void *Decoder) {
if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4,
true, 2, Inst, Decoder))
- Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1)));
+ Inst.addOperand(MCOperand::createImm(SignExtend32<12>(Val << 1)));
return MCDisassembler::Success;
}
@@ -3225,7 +3225,7 @@ static DecodeStatus DecodeT2BROperand(MC
uint64_t Address, const void *Decoder) {
if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4,
true, 4, Inst, Decoder))
- Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val)));
+ Inst.addOperand(MCOperand::createImm(SignExtend32<21>(Val)));
return MCDisassembler::Success;
}
@@ -3233,7 +3233,7 @@ static DecodeStatus DecodeThumbCmpBROper
uint64_t Address, const void *Decoder) {
if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4,
true, 2, Inst, Decoder))
- Inst.addOperand(MCOperand::CreateImm(Val << 1));
+ Inst.addOperand(MCOperand::createImm(Val << 1));
return MCDisassembler::Success;
}
@@ -3261,7 +3261,7 @@ static DecodeStatus DecodeThumbAddrModeI
if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateImm(imm));
+ Inst.addOperand(MCOperand::createImm(imm));
return S;
}
@@ -3270,7 +3270,7 @@ static DecodeStatus DecodeThumbAddrModeP
uint64_t Address, const void *Decoder) {
unsigned imm = Val << 2;
- Inst.addOperand(MCOperand::CreateImm(imm));
+ Inst.addOperand(MCOperand::createImm(imm));
tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder);
return MCDisassembler::Success;
@@ -3278,8 +3278,8 @@ static DecodeStatus DecodeThumbAddrModeP
static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder) {
- Inst.addOperand(MCOperand::CreateReg(ARM::SP));
- Inst.addOperand(MCOperand::CreateImm(Val));
+ Inst.addOperand(MCOperand::createReg(ARM::SP));
+ Inst.addOperand(MCOperand::createImm(Val));
return MCDisassembler::Success;
}
@@ -3307,7 +3307,7 @@ static DecodeStatus DecodeT2AddrModeSORe
return MCDisassembler::Fail;
if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateImm(imm));
+ Inst.addOperand(MCOperand::createImm(imm));
return S;
}
@@ -3641,7 +3641,7 @@ static DecodeStatus DecodeT2LoadLabel(MC
else
imm = -imm;
}
- Inst.addOperand(MCOperand::CreateImm(imm));
+ Inst.addOperand(MCOperand::createImm(imm));
return S;
}
@@ -3649,12 +3649,12 @@ static DecodeStatus DecodeT2LoadLabel(MC
static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder) {
if (Val == 0)
- Inst.addOperand(MCOperand::CreateImm(INT32_MIN));
+ Inst.addOperand(MCOperand::createImm(INT32_MIN));
else {
int imm = Val & 0xFF;
if (!(Val & 0x100)) imm *= -1;
- Inst.addOperand(MCOperand::CreateImm(imm * 4));
+ Inst.addOperand(MCOperand::createImm(imm * 4));
}
return MCDisassembler::Success;
@@ -3685,7 +3685,7 @@ static DecodeStatus DecodeT2AddrModeImm0
if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateImm(imm));
+ Inst.addOperand(MCOperand::createImm(imm));
return S;
}
@@ -3697,7 +3697,7 @@ static DecodeStatus DecodeT2Imm8(MCInst
imm = INT32_MIN;
else if (!(Val & 0x100))
imm *= -1;
- Inst.addOperand(MCOperand::CreateImm(imm));
+ Inst.addOperand(MCOperand::createImm(imm));
return MCDisassembler::Success;
}
@@ -3830,7 +3830,7 @@ static DecodeStatus DecodeT2AddrModeImm1
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateImm(imm));
+ Inst.addOperand(MCOperand::createImm(imm));
return S;
}
@@ -3840,9 +3840,9 @@ static DecodeStatus DecodeThumbAddSPImm(
uint64_t Address, const void *Decoder) {
unsigned imm = fieldFromInstruction(Insn, 0, 7);
- Inst.addOperand(MCOperand::CreateReg(ARM::SP));
- Inst.addOperand(MCOperand::CreateReg(ARM::SP));
- Inst.addOperand(MCOperand::CreateImm(imm));
+ Inst.addOperand(MCOperand::createReg(ARM::SP));
+ Inst.addOperand(MCOperand::createReg(ARM::SP));
+ Inst.addOperand(MCOperand::createImm(imm));
return MCDisassembler::Success;
}
@@ -3857,14 +3857,14 @@ static DecodeStatus DecodeThumbAddSPReg(
if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateReg(ARM::SP));
+ Inst.addOperand(MCOperand::createReg(ARM::SP));
if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
return MCDisassembler::Fail;
} else if (Inst.getOpcode() == ARM::tADDspr) {
unsigned Rm = fieldFromInstruction(Insn, 3, 4);
- Inst.addOperand(MCOperand::CreateReg(ARM::SP));
- Inst.addOperand(MCOperand::CreateReg(ARM::SP));
+ Inst.addOperand(MCOperand::createReg(ARM::SP));
+ Inst.addOperand(MCOperand::createReg(ARM::SP));
if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
return MCDisassembler::Fail;
}
@@ -3877,8 +3877,8 @@ static DecodeStatus DecodeThumbCPS(MCIns
unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2;
unsigned flags = fieldFromInstruction(Insn, 0, 3);
- Inst.addOperand(MCOperand::CreateImm(imod));
- Inst.addOperand(MCOperand::CreateImm(flags));
+ Inst.addOperand(MCOperand::createImm(imod));
+ Inst.addOperand(MCOperand::createImm(flags));
return MCDisassembler::Success;
}
@@ -3891,7 +3891,7 @@ static DecodeStatus DecodePostIdxReg(MCI
if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateImm(add));
+ Inst.addOperand(MCOperand::createImm(add));
return S;
}
@@ -3916,7 +3916,7 @@ static DecodeStatus DecodeThumbBLXOffset
if (!tryAddingSymbolicOperand(Address,
(Address & ~2u) + imm32 + 4,
true, 4, Inst, Decoder))
- Inst.addOperand(MCOperand::CreateImm(imm32));
+ Inst.addOperand(MCOperand::createImm(imm32));
return MCDisassembler::Success;
}
@@ -3930,7 +3930,7 @@ static DecodeStatus DecodeCoprocessor(MC
if ((featureBits & ARM::HasV8Ops) && !(Val == 14 || Val == 15))
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateImm(Val));
+ Inst.addOperand(MCOperand::createImm(Val));
return MCDisassembler::Success;
}
@@ -4001,16 +4001,16 @@ static DecodeStatus DecodeT2SOImm(MCInst
unsigned imm = fieldFromInstruction(Val, 0, 8);
switch (byte) {
case 0:
- Inst.addOperand(MCOperand::CreateImm(imm));
+ Inst.addOperand(MCOperand::createImm(imm));
break;
case 1:
- Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm));
+ Inst.addOperand(MCOperand::createImm((imm << 16) | imm));
break;
case 2:
- Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8)));
+ Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 8)));
break;
case 3:
- Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) |
+ Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 16) |
(imm << 8) | imm));
break;
}
@@ -4018,7 +4018,7 @@ static DecodeStatus DecodeT2SOImm(MCInst
unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80;
unsigned rot = fieldFromInstruction(Val, 7, 5);
unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31));
- Inst.addOperand(MCOperand::CreateImm(imm));
+ Inst.addOperand(MCOperand::createImm(imm));
}
return MCDisassembler::Success;
@@ -4029,7 +4029,7 @@ DecodeThumbBCCTargetOperand(MCInst &Inst
uint64_t Address, const void *Decoder){
if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4,
true, 2, Inst, Decoder))
- Inst.addOperand(MCOperand::CreateImm(SignExtend32<9>(Val << 1)));
+ Inst.addOperand(MCOperand::createImm(SignExtend32<9>(Val << 1)));
return MCDisassembler::Success;
}
@@ -4052,7 +4052,7 @@ static DecodeStatus DecodeThumbBLTargetO
if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
true, 4, Inst, Decoder))
- Inst.addOperand(MCOperand::CreateImm(imm32));
+ Inst.addOperand(MCOperand::createImm(imm32));
return MCDisassembler::Success;
}
@@ -4061,7 +4061,7 @@ static DecodeStatus DecodeMemBarrierOpti
if (Val & ~0xf)
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateImm(Val));
+ Inst.addOperand(MCOperand::createImm(Val));
return MCDisassembler::Success;
}
@@ -4070,7 +4070,7 @@ static DecodeStatus DecodeInstSyncBarrie
if (Val & ~0xf)
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateImm(Val));
+ Inst.addOperand(MCOperand::createImm(Val));
return MCDisassembler::Success;
}
@@ -4132,7 +4132,7 @@ static DecodeStatus DecodeMSRMask(MCInst
if (Val == 0)
return MCDisassembler::Fail;
}
- Inst.addOperand(MCOperand::CreateImm(Val));
+ Inst.addOperand(MCOperand::createImm(Val));
return S;
}
@@ -4155,7 +4155,7 @@ static DecodeStatus DecodeBankedReg(MCIn
return MCDisassembler::SoftFail;
}
- Inst.addOperand(MCOperand::CreateImm(Val));
+ Inst.addOperand(MCOperand::createImm(Val));
return MCDisassembler::Success;
}
@@ -4359,18 +4359,18 @@ static DecodeStatus DecodeVLD1LN(MCInst
}
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateImm(align));
+ Inst.addOperand(MCOperand::createImm(align));
if (Rm != 0xF) {
if (Rm != 0xD) {
if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
return MCDisassembler::Fail;
} else
- Inst.addOperand(MCOperand::CreateReg(0));
+ Inst.addOperand(MCOperand::createReg(0));
}
if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateImm(index));
+ Inst.addOperand(MCOperand::createImm(index));
return S;
}
@@ -4424,18 +4424,18 @@ static DecodeStatus DecodeVST1LN(MCInst
}
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateImm(align));
+ Inst.addOperand(MCOperand::createImm(align));
if (Rm != 0xF) {
if (Rm != 0xD) {
if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
return MCDisassembler::Fail;
} else
- Inst.addOperand(MCOperand::CreateReg(0));
+ Inst.addOperand(MCOperand::createReg(0));
}
if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateImm(index));
+ Inst.addOperand(MCOperand::createImm(index));
return S;
}
@@ -4490,20 +4490,20 @@ static DecodeStatus DecodeVLD2LN(MCInst
}
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateImm(align));
+ Inst.addOperand(MCOperand::createImm(align));
if (Rm != 0xF) {
if (Rm != 0xD) {
if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
return MCDisassembler::Fail;
} else
- Inst.addOperand(MCOperand::CreateReg(0));
+ Inst.addOperand(MCOperand::createReg(0));
}
if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
return MCDisassembler::Fail;
if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateImm(index));
+ Inst.addOperand(MCOperand::createImm(index));
return S;
}
@@ -4553,20 +4553,20 @@ static DecodeStatus DecodeVST2LN(MCInst
}
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateImm(align));
+ Inst.addOperand(MCOperand::createImm(align));
if (Rm != 0xF) {
if (Rm != 0xD) {
if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
return MCDisassembler::Fail;
} else
- Inst.addOperand(MCOperand::CreateReg(0));
+ Inst.addOperand(MCOperand::createReg(0));
}
if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
return MCDisassembler::Fail;
if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateImm(index));
+ Inst.addOperand(MCOperand::createImm(index));
return S;
}
@@ -4622,13 +4622,13 @@ static DecodeStatus DecodeVLD3LN(MCInst
}
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateImm(align));
+ Inst.addOperand(MCOperand::createImm(align));
if (Rm != 0xF) {
if (Rm != 0xD) {
if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
return MCDisassembler::Fail;
} else
- Inst.addOperand(MCOperand::CreateReg(0));
+ Inst.addOperand(MCOperand::createReg(0));
}
if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
@@ -4637,7 +4637,7 @@ static DecodeStatus DecodeVLD3LN(MCInst
return MCDisassembler::Fail;
if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateImm(index));
+ Inst.addOperand(MCOperand::createImm(index));
return S;
}
@@ -4685,13 +4685,13 @@ static DecodeStatus DecodeVST3LN(MCInst
}
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateImm(align));
+ Inst.addOperand(MCOperand::createImm(align));
if (Rm != 0xF) {
if (Rm != 0xD) {
if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
return MCDisassembler::Fail;
} else
- Inst.addOperand(MCOperand::CreateReg(0));
+ Inst.addOperand(MCOperand::createReg(0));
}
if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
@@ -4700,7 +4700,7 @@ static DecodeStatus DecodeVST3LN(MCInst
return MCDisassembler::Fail;
if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateImm(index));
+ Inst.addOperand(MCOperand::createImm(index));
return S;
}
@@ -4765,13 +4765,13 @@ static DecodeStatus DecodeVLD4LN(MCInst
}
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateImm(align));
+ Inst.addOperand(MCOperand::createImm(align));
if (Rm != 0xF) {
if (Rm != 0xD) {
if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
return MCDisassembler::Fail;
} else
- Inst.addOperand(MCOperand::CreateReg(0));
+ Inst.addOperand(MCOperand::createReg(0));
}
if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
@@ -4782,7 +4782,7 @@ static DecodeStatus DecodeVLD4LN(MCInst
return MCDisassembler::Fail;
if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateImm(index));
+ Inst.addOperand(MCOperand::createImm(index));
return S;
}
@@ -4837,13 +4837,13 @@ static DecodeStatus DecodeVST4LN(MCInst
}
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateImm(align));
+ Inst.addOperand(MCOperand::createImm(align));
if (Rm != 0xF) {
if (Rm != 0xD) {
if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
return MCDisassembler::Fail;
} else
- Inst.addOperand(MCOperand::CreateReg(0));
+ Inst.addOperand(MCOperand::createReg(0));
}
if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
@@ -4854,7 +4854,7 @@ static DecodeStatus DecodeVST4LN(MCInst
return MCDisassembler::Fail;
if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateImm(index));
+ Inst.addOperand(MCOperand::createImm(index));
return S;
}
@@ -4925,8 +4925,8 @@ static DecodeStatus DecodeIT(MCInst &Ins
if (mask == 0x0)
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateImm(pred));
- Inst.addOperand(MCOperand::CreateImm(mask));
+ Inst.addOperand(MCOperand::createImm(pred));
+ Inst.addOperand(MCOperand::createImm(mask));
return S;
}
@@ -5012,7 +5012,7 @@ static DecodeStatus DecodeT2Adr(MCInst &
Val |= fieldFromInstruction(Insn, 12, 3) << 8;
Val |= fieldFromInstruction(Insn, 26, 1) << 11;
Val |= sign1 << 12;
- Inst.addOperand(MCOperand::CreateImm(SignExtend32<13>(Val)));
+ Inst.addOperand(MCOperand::createImm(SignExtend32<13>(Val)));
return MCDisassembler::Success;
}
@@ -5024,7 +5024,7 @@ static DecodeStatus DecodeT2ShifterImmOp
// Shift of "asr #32" is not allowed in Thumb2 mode.
if (Val == 0x20) S = MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateImm(Val));
+ Inst.addOperand(MCOperand::createImm(Val));
return S;
}
@@ -5080,7 +5080,7 @@ static DecodeStatus DecodeVCVTD(MCInst &
return MCDisassembler::Fail;
if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder)))
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateImm(64 - imm));
+ Inst.addOperand(MCOperand::createImm(64 - imm));
return S;
}
@@ -5110,7 +5110,7 @@ static DecodeStatus DecodeVCVTQ(MCInst &
return MCDisassembler::Fail;
if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder)))
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateImm(64 - imm));
+ Inst.addOperand(MCOperand::createImm(64 - imm));
return S;
}
@@ -5159,13 +5159,13 @@ static DecodeStatus DecodeMRRC2(llvm::MC
if (Rt == Rt2)
S = MCDisassembler::SoftFail;
- Inst.addOperand(MCOperand::CreateImm(cop));
- Inst.addOperand(MCOperand::CreateImm(opc1));
+ Inst.addOperand(MCOperand::createImm(cop));
+ Inst.addOperand(MCOperand::createImm(opc1));
if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
return MCDisassembler::Fail;
if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateImm(CRm));
+ Inst.addOperand(MCOperand::createImm(CRm));
return S;
}
Modified: llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp?rev=237275&r1=237274&r2=237275&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp Wed May 13 13:37:00 2015
@@ -284,7 +284,7 @@ void ARMInstPrinter::printInst(const MCI
if (isStore)
NewMI.addOperand(MI->getOperand(0));
- NewReg = MCOperand::CreateReg(MRI.getMatchingSuperReg(
+ NewReg = MCOperand::createReg(MRI.getMatchingSuperReg(
Reg, ARM::gsub_0, &MRI.getRegClass(ARM::GPRPairRegClassID)));
NewMI.addOperand(NewReg);
Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp?rev=237275&r1=237274&r2=237275&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp (original)
+++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp Wed May 13 13:37:00 2015
@@ -238,9 +238,9 @@ void ARMAsmBackend::relaxInstruction(con
if ((Inst.getOpcode() == ARM::tCBZ || Inst.getOpcode() == ARM::tCBNZ) &&
RelaxedOp == ARM::tHINT) {
Res.setOpcode(RelaxedOp);
- Res.addOperand(MCOperand::CreateImm(0));
- Res.addOperand(MCOperand::CreateImm(14));
- Res.addOperand(MCOperand::CreateReg(0));
+ Res.addOperand(MCOperand::createImm(0));
+ Res.addOperand(MCOperand::createImm(14));
+ Res.addOperand(MCOperand::createReg(0));
return;
}
Modified: llvm/trunk/lib/Target/ARM/Thumb1InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb1InstrInfo.cpp?rev=237275&r1=237274&r2=237275&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Thumb1InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Thumb1InstrInfo.cpp Wed May 13 13:37:00 2015
@@ -27,10 +27,10 @@ Thumb1InstrInfo::Thumb1InstrInfo(const A
/// getNoopForMachoTarget - Return the noop instruction to use for a noop.
void Thumb1InstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
NopInst.setOpcode(ARM::tMOVr);
- NopInst.addOperand(MCOperand::CreateReg(ARM::R8));
- NopInst.addOperand(MCOperand::CreateReg(ARM::R8));
- NopInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
- NopInst.addOperand(MCOperand::CreateReg(0));
+ NopInst.addOperand(MCOperand::createReg(ARM::R8));
+ NopInst.addOperand(MCOperand::createReg(ARM::R8));
+ NopInst.addOperand(MCOperand::createImm(ARMCC::AL));
+ NopInst.addOperand(MCOperand::createReg(0));
}
unsigned Thumb1InstrInfo::getUnindexedOpcode(unsigned Opc) const {
Modified: llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp?rev=237275&r1=237274&r2=237275&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp Wed May 13 13:37:00 2015
@@ -35,9 +35,9 @@ Thumb2InstrInfo::Thumb2InstrInfo(const A
/// getNoopForMachoTarget - Return the noop instruction to use for a noop.
void Thumb2InstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
NopInst.setOpcode(ARM::tHINT);
- NopInst.addOperand(MCOperand::CreateImm(0));
- NopInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
- NopInst.addOperand(MCOperand::CreateReg(0));
+ NopInst.addOperand(MCOperand::createImm(0));
+ NopInst.addOperand(MCOperand::createImm(ARMCC::AL));
+ NopInst.addOperand(MCOperand::createReg(0));
}
unsigned Thumb2InstrInfo::getUnindexedOpcode(unsigned Opc) const {
Modified: llvm/trunk/lib/Target/BPF/BPFMCInstLower.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/BPF/BPFMCInstLower.cpp?rev=237275&r1=237274&r2=237275&view=diff
==============================================================================
--- llvm/trunk/lib/Target/BPF/BPFMCInstLower.cpp (original)
+++ llvm/trunk/lib/Target/BPF/BPFMCInstLower.cpp Wed May 13 13:37:00 2015
@@ -38,7 +38,7 @@ MCOperand BPFMCInstLower::LowerSymbolOpe
if (!MO.isJTI() && MO.getOffset())
llvm_unreachable("unknown symbol op");
- return MCOperand::CreateExpr(Expr);
+ return MCOperand::createExpr(Expr);
}
void BPFMCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
@@ -56,13 +56,13 @@ void BPFMCInstLower::Lower(const Machine
// Ignore all implicit register operands.
if (MO.isImplicit())
continue;
- MCOp = MCOperand::CreateReg(MO.getReg());
+ MCOp = MCOperand::createReg(MO.getReg());
break;
case MachineOperand::MO_Immediate:
- MCOp = MCOperand::CreateImm(MO.getImm());
+ MCOp = MCOperand::createImm(MO.getImm());
break;
case MachineOperand::MO_MachineBasicBlock:
- MCOp = MCOperand::CreateExpr(
+ MCOp = MCOperand::createExpr(
MCSymbolRefExpr::Create(MO.getMBB()->getSymbol(), Ctx));
break;
case MachineOperand::MO_RegisterMask:
Modified: llvm/trunk/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp?rev=237275&r1=237274&r2=237275&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp Wed May 13 13:37:00 2015
@@ -69,7 +69,7 @@ Hexagon::P2, Hexagon::P3 };
static DecodeStatus DecodeRegisterClass(MCInst &Inst, unsigned RegNo,
const uint16_t Table[], size_t Size) {
if (RegNo < Size) {
- Inst.addOperand(MCOperand::CreateReg(Table[RegNo]));
+ Inst.addOperand(MCOperand::createReg(Table[RegNo]));
return MCDisassembler::Success;
}
else
@@ -83,7 +83,7 @@ static DecodeStatus DecodeIntRegsRegiste
return MCDisassembler::Fail;
unsigned Register = IntRegDecoderTable[RegNo];
- Inst.addOperand(MCOperand::CreateReg(Register));
+ Inst.addOperand(MCOperand::createReg(Register));
return MCDisassembler::Success;
}
@@ -103,7 +103,7 @@ static DecodeStatus DecodeCtrRegsRegiste
return MCDisassembler::Fail;
unsigned Register = CtrlRegDecoderTable[RegNo];
- Inst.addOperand(MCOperand::CreateReg(Register));
+ Inst.addOperand(MCOperand::createReg(Register));
return MCDisassembler::Success;
}
@@ -127,7 +127,7 @@ static DecodeStatus DecodeCtrRegs64Regis
return MCDisassembler::Fail;
unsigned Register = CtrlReg64DecoderTable[RegNo];
- Inst.addOperand(MCOperand::CreateReg(Register));
+ Inst.addOperand(MCOperand::createReg(Register));
return MCDisassembler::Success;
}
@@ -144,7 +144,7 @@ static DecodeStatus DecodeModRegsRegiste
default:
return MCDisassembler::Fail;
}
- Inst.addOperand(MCOperand::CreateReg(Register));
+ Inst.addOperand(MCOperand::createReg(Register));
return MCDisassembler::Success;
}
@@ -169,7 +169,7 @@ static DecodeStatus DecodePredRegsRegist
return MCDisassembler::Fail;
unsigned Register = PredRegDecoderTable[RegNo];
- Inst.addOperand(MCOperand::CreateReg(Register));
+ Inst.addOperand(MCOperand::createReg(Register));
return MCDisassembler::Success;
}
Modified: llvm/trunk/lib/Target/Hexagon/HexagonMCInstLower.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonMCInstLower.cpp?rev=237275&r1=237274&r2=237275&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonMCInstLower.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonMCInstLower.cpp Wed May 13 13:37:00 2015
@@ -34,7 +34,7 @@ static MCOperand GetSymbolRef(const Mach
ME = MCBinaryExpr::CreateAdd(ME, MCConstantExpr::Create(MO.getOffset(), MC),
MC);
- return (MCOperand::CreateExpr(ME));
+ return (MCOperand::createExpr(ME));
}
// Create an MCInst from a MachineInstr
@@ -53,20 +53,20 @@ void llvm::HexagonLowerToMC(MachineInstr
case MachineOperand::MO_Register:
// Ignore all implicit register operands.
if (MO.isImplicit()) continue;
- MCO = MCOperand::CreateReg(MO.getReg());
+ MCO = MCOperand::createReg(MO.getReg());
break;
case MachineOperand::MO_FPImmediate: {
APFloat Val = MO.getFPImm()->getValueAPF();
// FP immediates are used only when setting GPRs, so they may be dealt
// with like regular immediates from this point on.
- MCO = MCOperand::CreateImm(*Val.bitcastToAPInt().getRawData());
+ MCO = MCOperand::createImm(*Val.bitcastToAPInt().getRawData());
break;
}
case MachineOperand::MO_Immediate:
- MCO = MCOperand::CreateImm(MO.getImm());
+ MCO = MCOperand::createImm(MO.getImm());
break;
case MachineOperand::MO_MachineBasicBlock:
- MCO = MCOperand::CreateExpr
+ MCO = MCOperand::createExpr
(MCSymbolRefExpr::Create(MO.getMBB()->getSymbol(),
AP.OutContext));
break;
Modified: llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp?rev=237275&r1=237274&r2=237275&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp Wed May 13 13:37:00 2015
@@ -16,8 +16,8 @@
namespace llvm {
void HexagonMCInstrInfo::AppendImplicitOperands(MCInst &MCI) {
- MCI.addOperand(MCOperand::CreateImm(0));
- MCI.addOperand(MCOperand::CreateInst(nullptr));
+ MCI.addOperand(MCOperand::createImm(0));
+ MCI.addOperand(MCOperand::createInst(nullptr));
}
HexagonII::MemAccessSize
Modified: llvm/trunk/lib/Target/MSP430/MSP430MCInstLower.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430MCInstLower.cpp?rev=237275&r1=237274&r2=237275&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MSP430/MSP430MCInstLower.cpp (original)
+++ llvm/trunk/lib/Target/MSP430/MSP430MCInstLower.cpp Wed May 13 13:37:00 2015
@@ -107,7 +107,7 @@ LowerSymbolOperand(const MachineOperand
Expr = MCBinaryExpr::CreateAdd(Expr,
MCConstantExpr::Create(MO.getOffset(), Ctx),
Ctx);
- return MCOperand::CreateExpr(Expr);
+ return MCOperand::createExpr(Expr);
}
void MSP430MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
@@ -124,13 +124,13 @@ void MSP430MCInstLower::Lower(const Mach
case MachineOperand::MO_Register:
// Ignore all implicit register operands.
if (MO.isImplicit()) continue;
- MCOp = MCOperand::CreateReg(MO.getReg());
+ MCOp = MCOperand::createReg(MO.getReg());
break;
case MachineOperand::MO_Immediate:
- MCOp = MCOperand::CreateImm(MO.getImm());
+ MCOp = MCOperand::createImm(MO.getImm());
break;
case MachineOperand::MO_MachineBasicBlock:
- MCOp = MCOperand::CreateExpr(MCSymbolRefExpr::Create(
+ MCOp = MCOperand::createExpr(MCSymbolRefExpr::Create(
MO.getMBB()->getSymbol(), Ctx));
break;
case MachineOperand::MO_GlobalAddress:
Modified: llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp?rev=237275&r1=237274&r2=237275&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp Wed May 13 13:37:00 2015
@@ -697,11 +697,11 @@ public:
void addExpr(MCInst &Inst, const MCExpr *Expr) const {
// Add as immediate when possible. Null MCExpr = 0.
if (!Expr)
- Inst.addOperand(MCOperand::CreateImm(0));
+ Inst.addOperand(MCOperand::createImm(0));
else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
- Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
+ Inst.addOperand(MCOperand::createImm(CE->getValue()));
else
- Inst.addOperand(MCOperand::CreateExpr(Expr));
+ Inst.addOperand(MCOperand::createExpr(Expr));
}
void addRegOperands(MCInst &Inst, unsigned N) const {
@@ -713,22 +713,22 @@ public:
/// is not a k_RegisterIndex compatible with RegKind_GPR
void addGPR32AsmRegOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateReg(getGPR32Reg()));
+ Inst.addOperand(MCOperand::createReg(getGPR32Reg()));
}
void addGPRMM16AsmRegOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateReg(getGPRMM16Reg()));
+ Inst.addOperand(MCOperand::createReg(getGPRMM16Reg()));
}
void addGPRMM16AsmRegZeroOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateReg(getGPRMM16Reg()));
+ Inst.addOperand(MCOperand::createReg(getGPRMM16Reg()));
}
void addGPRMM16AsmRegMovePOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateReg(getGPRMM16Reg()));
+ Inst.addOperand(MCOperand::createReg(getGPRMM16Reg()));
}
/// Render the operand to an MCInst as a GPR64
@@ -736,22 +736,22 @@ public:
/// is not a k_RegisterIndex compatible with RegKind_GPR
void addGPR64AsmRegOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateReg(getGPR64Reg()));
+ Inst.addOperand(MCOperand::createReg(getGPR64Reg()));
}
void addAFGR64AsmRegOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateReg(getAFGR64Reg()));
+ Inst.addOperand(MCOperand::createReg(getAFGR64Reg()));
}
void addFGR64AsmRegOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateReg(getFGR64Reg()));
+ Inst.addOperand(MCOperand::createReg(getFGR64Reg()));
}
void addFGR32AsmRegOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateReg(getFGR32Reg()));
+ Inst.addOperand(MCOperand::createReg(getFGR32Reg()));
// FIXME: We ought to do this for -integrated-as without -via-file-asm too.
if (!AsmParser.useOddSPReg() && RegIdx.Index & 1)
AsmParser.Error(StartLoc, "-mno-odd-spreg prohibits the use of odd FPU "
@@ -760,57 +760,57 @@ public:
void addFGRH32AsmRegOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateReg(getFGRH32Reg()));
+ Inst.addOperand(MCOperand::createReg(getFGRH32Reg()));
}
void addFCCAsmRegOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateReg(getFCCReg()));
+ Inst.addOperand(MCOperand::createReg(getFCCReg()));
}
void addMSA128AsmRegOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateReg(getMSA128Reg()));
+ Inst.addOperand(MCOperand::createReg(getMSA128Reg()));
}
void addMSACtrlAsmRegOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateReg(getMSACtrlReg()));
+ Inst.addOperand(MCOperand::createReg(getMSACtrlReg()));
}
void addCOP2AsmRegOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateReg(getCOP2Reg()));
+ Inst.addOperand(MCOperand::createReg(getCOP2Reg()));
}
void addCOP3AsmRegOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateReg(getCOP3Reg()));
+ Inst.addOperand(MCOperand::createReg(getCOP3Reg()));
}
void addACC64DSPAsmRegOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateReg(getACC64DSPReg()));
+ Inst.addOperand(MCOperand::createReg(getACC64DSPReg()));
}
void addHI32DSPAsmRegOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateReg(getHI32DSPReg()));
+ Inst.addOperand(MCOperand::createReg(getHI32DSPReg()));
}
void addLO32DSPAsmRegOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateReg(getLO32DSPReg()));
+ Inst.addOperand(MCOperand::createReg(getLO32DSPReg()));
}
void addCCRAsmRegOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateReg(getCCRReg()));
+ Inst.addOperand(MCOperand::createReg(getCCRReg()));
}
void addHWRegsAsmRegOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateReg(getHWRegsReg()));
+ Inst.addOperand(MCOperand::createReg(getHWRegsReg()));
}
void addImmOperands(MCInst &Inst, unsigned N) const {
@@ -822,7 +822,7 @@ public:
void addMemOperands(MCInst &Inst, unsigned N) const {
assert(N == 2 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateReg(getMemBase()->getGPR32Reg()));
+ Inst.addOperand(MCOperand::createReg(getMemBase()->getGPR32Reg()));
const MCExpr *Expr = getMemOff();
addExpr(Inst, Expr);
@@ -831,7 +831,7 @@ public:
void addMicroMipsMemOperands(MCInst &Inst, unsigned N) const {
assert(N == 2 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateReg(getMemBase()->getGPRMM16Reg()));
+ Inst.addOperand(MCOperand::createReg(getMemBase()->getGPRMM16Reg()));
const MCExpr *Expr = getMemOff();
addExpr(Inst, Expr);
@@ -841,20 +841,20 @@ public:
assert(N == 1 && "Invalid number of operands!");
for (auto RegNo : getRegList())
- Inst.addOperand(MCOperand::CreateReg(RegNo));
+ Inst.addOperand(MCOperand::createReg(RegNo));
}
void addRegPairOperands(MCInst &Inst, unsigned N) const {
assert(N == 2 && "Invalid number of operands!");
unsigned RegNo = getRegPair();
- Inst.addOperand(MCOperand::CreateReg(RegNo++));
- Inst.addOperand(MCOperand::CreateReg(RegNo));
+ Inst.addOperand(MCOperand::createReg(RegNo++));
+ Inst.addOperand(MCOperand::createReg(RegNo));
}
void addMovePRegPairOperands(MCInst &Inst, unsigned N) const {
assert(N == 2 && "Invalid number of operands!");
for (auto RegNo : getRegList())
- Inst.addOperand(MCOperand::CreateReg(RegNo));
+ Inst.addOperand(MCOperand::createReg(RegNo));
}
bool isReg() const override {
@@ -1445,9 +1445,9 @@ bool MipsAsmParser::processInstruction(M
MCInst TmpInst;
TmpInst.setLoc(IDLoc);
TmpInst.setOpcode(Mips::LWGP_MM);
- TmpInst.addOperand(MCOperand::CreateReg(DstReg.getReg()));
- TmpInst.addOperand(MCOperand::CreateReg(Mips::GP));
- TmpInst.addOperand(MCOperand::CreateImm(MemOffset));
+ TmpInst.addOperand(MCOperand::createReg(DstReg.getReg()));
+ TmpInst.addOperand(MCOperand::createReg(Mips::GP));
+ TmpInst.addOperand(MCOperand::createImm(MemOffset));
Instructions.push_back(TmpInst);
return false;
}
@@ -1643,17 +1643,17 @@ void createLShiftOri(MCOperand Operand,
MCInst tmpInst;
if (ShiftAmount >= 32) {
tmpInst.setOpcode(Mips::DSLL32);
- tmpInst.addOperand(MCOperand::CreateReg(RegNo));
- tmpInst.addOperand(MCOperand::CreateReg(RegNo));
- tmpInst.addOperand(MCOperand::CreateImm(ShiftAmount - 32));
+ tmpInst.addOperand(MCOperand::createReg(RegNo));
+ tmpInst.addOperand(MCOperand::createReg(RegNo));
+ tmpInst.addOperand(MCOperand::createImm(ShiftAmount - 32));
tmpInst.setLoc(IDLoc);
Instructions.push_back(tmpInst);
tmpInst.clear();
} else if (ShiftAmount > 0) {
tmpInst.setOpcode(Mips::DSLL);
- tmpInst.addOperand(MCOperand::CreateReg(RegNo));
- tmpInst.addOperand(MCOperand::CreateReg(RegNo));
- tmpInst.addOperand(MCOperand::CreateImm(ShiftAmount));
+ tmpInst.addOperand(MCOperand::createReg(RegNo));
+ tmpInst.addOperand(MCOperand::createReg(RegNo));
+ tmpInst.addOperand(MCOperand::createImm(ShiftAmount));
tmpInst.setLoc(IDLoc);
Instructions.push_back(tmpInst);
tmpInst.clear();
@@ -1663,8 +1663,8 @@ void createLShiftOri(MCOperand Operand,
return;
tmpInst.setOpcode(Mips::ORi);
- tmpInst.addOperand(MCOperand::CreateReg(RegNo));
- tmpInst.addOperand(MCOperand::CreateReg(RegNo));
+ tmpInst.addOperand(MCOperand::createReg(RegNo));
+ tmpInst.addOperand(MCOperand::createReg(RegNo));
tmpInst.addOperand(Operand);
tmpInst.setLoc(IDLoc);
Instructions.push_back(tmpInst);
@@ -1673,7 +1673,7 @@ void createLShiftOri(MCOperand Operand,
template <unsigned ShiftAmount>
void createLShiftOri(int64_t Value, unsigned RegNo, SMLoc IDLoc,
SmallVectorImpl<MCInst> &Instructions) {
- createLShiftOri<ShiftAmount>(MCOperand::CreateImm(Value), RegNo, IDLoc,
+ createLShiftOri<ShiftAmount>(MCOperand::createImm(Value), RegNo, IDLoc,
Instructions);
}
}
@@ -1693,7 +1693,7 @@ bool MipsAsmParser::expandJalWithRegs(MC
JalrInst.addOperand(FirstRegOp);
} else {
JalrInst.setOpcode(Mips::JALR);
- JalrInst.addOperand(MCOperand::CreateReg(Mips::RA));
+ JalrInst.addOperand(MCOperand::createReg(Mips::RA));
JalrInst.addOperand(FirstRegOp);
}
} else if (Opcode == Mips::JalTwoReg) {
@@ -1711,9 +1711,9 @@ bool MipsAsmParser::expandJalWithRegs(MC
// do not have a short delay slot.
MCInst NopInst;
NopInst.setOpcode(Mips::SLL);
- NopInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
- NopInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
- NopInst.addOperand(MCOperand::CreateImm(0));
+ NopInst.addOperand(MCOperand::createReg(Mips::ZERO));
+ NopInst.addOperand(MCOperand::createReg(Mips::ZERO));
+ NopInst.addOperand(MCOperand::createImm(0));
Instructions.push_back(NopInst);
}
@@ -1743,9 +1743,9 @@ bool MipsAsmParser::loadImmediate(int64_
if (!UseSrcReg)
SrcReg = isGP64bit() ? Mips::ZERO_64 : Mips::ZERO;
tmpInst.setOpcode(Mips::ORi);
- tmpInst.addOperand(MCOperand::CreateReg(DstReg));
- tmpInst.addOperand(MCOperand::CreateReg(SrcReg));
- tmpInst.addOperand(MCOperand::CreateImm(ImmValue));
+ tmpInst.addOperand(MCOperand::createReg(DstReg));
+ tmpInst.addOperand(MCOperand::createReg(SrcReg));
+ tmpInst.addOperand(MCOperand::createImm(ImmValue));
Instructions.push_back(tmpInst);
} else if (ImmValue < 0 && ImmValue >= -32768) {
// For negative signed 16-bit values (-32768 <= j < 0):
@@ -1753,9 +1753,9 @@ bool MipsAsmParser::loadImmediate(int64_
if (!UseSrcReg)
SrcReg = Mips::ZERO;
tmpInst.setOpcode(Mips::ADDiu);
- tmpInst.addOperand(MCOperand::CreateReg(DstReg));
- tmpInst.addOperand(MCOperand::CreateReg(SrcReg));
- tmpInst.addOperand(MCOperand::CreateImm(ImmValue));
+ tmpInst.addOperand(MCOperand::createReg(DstReg));
+ tmpInst.addOperand(MCOperand::createReg(SrcReg));
+ tmpInst.addOperand(MCOperand::createImm(ImmValue));
Instructions.push_back(tmpInst);
} else if ((ImmValue & 0xffffffff) == ImmValue) {
// For all other values which are representable as a 32-bit integer:
@@ -1765,8 +1765,8 @@ bool MipsAsmParser::loadImmediate(int64_
uint16_t Bits15To0 = ImmValue & 0xffff;
tmpInst.setOpcode(Mips::LUi);
- tmpInst.addOperand(MCOperand::CreateReg(DstReg));
- tmpInst.addOperand(MCOperand::CreateImm(Bits31To16));
+ tmpInst.addOperand(MCOperand::createReg(DstReg));
+ tmpInst.addOperand(MCOperand::createImm(Bits31To16));
Instructions.push_back(tmpInst);
createLShiftOri<0>(Bits15To0, DstReg, IDLoc, Instructions);
@@ -1797,8 +1797,8 @@ bool MipsAsmParser::loadImmediate(int64_
uint16_t Bits15To0 = ImmValue & 0xffff;
tmpInst.setOpcode(Mips::LUi);
- tmpInst.addOperand(MCOperand::CreateReg(DstReg));
- tmpInst.addOperand(MCOperand::CreateImm(Bits47To32));
+ tmpInst.addOperand(MCOperand::createReg(DstReg));
+ tmpInst.addOperand(MCOperand::createImm(Bits47To32));
Instructions.push_back(tmpInst);
createLShiftOri<0>(Bits31To16, DstReg, IDLoc, Instructions);
createLShiftOri<16>(Bits15To0, DstReg, IDLoc, Instructions);
@@ -1832,8 +1832,8 @@ bool MipsAsmParser::loadImmediate(int64_
uint16_t Bits15To0 = ImmValue & 0xffff;
tmpInst.setOpcode(Mips::LUi);
- tmpInst.addOperand(MCOperand::CreateReg(DstReg));
- tmpInst.addOperand(MCOperand::CreateImm(Bits63To48));
+ tmpInst.addOperand(MCOperand::createReg(DstReg));
+ tmpInst.addOperand(MCOperand::createImm(Bits63To48));
Instructions.push_back(tmpInst);
createLShiftOri<0>(Bits47To32, DstReg, IDLoc, Instructions);
@@ -1949,26 +1949,26 @@ MipsAsmParser::expandLoadAddressSym(MCIn
MCSymbolRefExpr::VK_Mips_HIGHER, getContext());
tmpInst.setOpcode(Mips::LUi);
- tmpInst.addOperand(MCOperand::CreateReg(RegNo));
- tmpInst.addOperand(MCOperand::CreateExpr(HighestExpr));
+ tmpInst.addOperand(MCOperand::createReg(RegNo));
+ tmpInst.addOperand(MCOperand::createExpr(HighestExpr));
Instructions.push_back(tmpInst);
- createLShiftOri<0>(MCOperand::CreateExpr(HigherExpr), RegNo, SMLoc(),
+ createLShiftOri<0>(MCOperand::createExpr(HigherExpr), RegNo, SMLoc(),
Instructions);
- createLShiftOri<16>(MCOperand::CreateExpr(HiExpr), RegNo, SMLoc(),
+ createLShiftOri<16>(MCOperand::createExpr(HiExpr), RegNo, SMLoc(),
Instructions);
- createLShiftOri<16>(MCOperand::CreateExpr(LoExpr), RegNo, SMLoc(),
+ createLShiftOri<16>(MCOperand::createExpr(LoExpr), RegNo, SMLoc(),
Instructions);
} else {
// Otherwise, expand to:
// la d,sym => lui d,hi16(sym)
// ori d,d,lo16(sym)
tmpInst.setOpcode(Mips::LUi);
- tmpInst.addOperand(MCOperand::CreateReg(RegNo));
- tmpInst.addOperand(MCOperand::CreateExpr(HiExpr));
+ tmpInst.addOperand(MCOperand::createReg(RegNo));
+ tmpInst.addOperand(MCOperand::createExpr(HiExpr));
Instructions.push_back(tmpInst);
- createLShiftOri<0>(MCOperand::CreateExpr(LoExpr), RegNo, SMLoc(),
+ createLShiftOri<0>(MCOperand::createExpr(LoExpr), RegNo, SMLoc(),
Instructions);
}
}
@@ -1982,9 +1982,9 @@ bool MipsAsmParser::expandUncondBranchMM
if (Offset.isExpr()) {
Inst.clear();
Inst.setOpcode(Mips::BEQ_MM);
- Inst.addOperand(MCOperand::CreateReg(Mips::ZERO));
- Inst.addOperand(MCOperand::CreateReg(Mips::ZERO));
- Inst.addOperand(MCOperand::CreateExpr(Offset.getExpr()));
+ Inst.addOperand(MCOperand::createReg(Mips::ZERO));
+ Inst.addOperand(MCOperand::createReg(Mips::ZERO));
+ Inst.addOperand(MCOperand::createExpr(Offset.getExpr()));
} else {
assert(Offset.isImm() && "expected immediate operand kind");
if (isIntN(11, Offset.getImm())) {
@@ -1998,9 +1998,9 @@ bool MipsAsmParser::expandUncondBranchMM
Error(IDLoc, "branch to misaligned address");
Inst.clear();
Inst.setOpcode(Mips::BEQ_MM);
- Inst.addOperand(MCOperand::CreateReg(Mips::ZERO));
- Inst.addOperand(MCOperand::CreateReg(Mips::ZERO));
- Inst.addOperand(MCOperand::CreateImm(Offset.getImm()));
+ Inst.addOperand(MCOperand::createReg(Mips::ZERO));
+ Inst.addOperand(MCOperand::createReg(Mips::ZERO));
+ Inst.addOperand(MCOperand::createImm(Offset.getImm()));
}
}
Instructions.push_back(Inst);
@@ -2078,19 +2078,19 @@ void MipsAsmParser::expandMemInst(MCInst
}
TempInst.setOpcode(Mips::LUi);
- TempInst.addOperand(MCOperand::CreateReg(TmpRegNum));
+ TempInst.addOperand(MCOperand::createReg(TmpRegNum));
if (isImmOpnd)
- TempInst.addOperand(MCOperand::CreateImm(HiOffset));
+ TempInst.addOperand(MCOperand::createImm(HiOffset));
else {
if (ExprOffset->getKind() == MCExpr::SymbolRef) {
SR = static_cast<const MCSymbolRefExpr *>(ExprOffset);
const MCSymbolRefExpr *HiExpr = MCSymbolRefExpr::Create(
SR->getSymbol().getName(), MCSymbolRefExpr::VK_Mips_ABS_HI,
getContext());
- TempInst.addOperand(MCOperand::CreateExpr(HiExpr));
+ TempInst.addOperand(MCOperand::createExpr(HiExpr));
} else {
const MCExpr *HiExpr = evaluateRelocExpr(ExprOffset, "hi");
- TempInst.addOperand(MCOperand::CreateExpr(HiExpr));
+ TempInst.addOperand(MCOperand::createExpr(HiExpr));
}
}
// Add the instruction to the list.
@@ -2100,28 +2100,28 @@ void MipsAsmParser::expandMemInst(MCInst
// Add temp register to base.
if (BaseRegNum != Mips::ZERO) {
TempInst.setOpcode(Mips::ADDu);
- TempInst.addOperand(MCOperand::CreateReg(TmpRegNum));
- TempInst.addOperand(MCOperand::CreateReg(TmpRegNum));
- TempInst.addOperand(MCOperand::CreateReg(BaseRegNum));
+ TempInst.addOperand(MCOperand::createReg(TmpRegNum));
+ TempInst.addOperand(MCOperand::createReg(TmpRegNum));
+ TempInst.addOperand(MCOperand::createReg(BaseRegNum));
Instructions.push_back(TempInst);
TempInst.clear();
}
// And finally, create original instruction with low part
// of offset and new base.
TempInst.setOpcode(Inst.getOpcode());
- TempInst.addOperand(MCOperand::CreateReg(RegOpNum));
- TempInst.addOperand(MCOperand::CreateReg(TmpRegNum));
+ TempInst.addOperand(MCOperand::createReg(RegOpNum));
+ TempInst.addOperand(MCOperand::createReg(TmpRegNum));
if (isImmOpnd)
- TempInst.addOperand(MCOperand::CreateImm(LoOffset));
+ TempInst.addOperand(MCOperand::createImm(LoOffset));
else {
if (ExprOffset->getKind() == MCExpr::SymbolRef) {
const MCSymbolRefExpr *LoExpr = MCSymbolRefExpr::Create(
SR->getSymbol().getName(), MCSymbolRefExpr::VK_Mips_ABS_LO,
getContext());
- TempInst.addOperand(MCOperand::CreateExpr(LoExpr));
+ TempInst.addOperand(MCOperand::createExpr(LoExpr));
} else {
const MCExpr *LoExpr = evaluateRelocExpr(ExprOffset, "lo");
- TempInst.addOperand(MCOperand::CreateExpr(LoExpr));
+ TempInst.addOperand(MCOperand::createExpr(LoExpr));
}
}
Instructions.push_back(TempInst);
@@ -2156,13 +2156,13 @@ void MipsAsmParser::createNop(bool hasSh
MCInst NopInst;
if (hasShortDelaySlot) {
NopInst.setOpcode(Mips::MOVE16_MM);
- NopInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
- NopInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
+ NopInst.addOperand(MCOperand::createReg(Mips::ZERO));
+ NopInst.addOperand(MCOperand::createReg(Mips::ZERO));
} else {
NopInst.setOpcode(Mips::SLL);
- NopInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
- NopInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
- NopInst.addOperand(MCOperand::CreateImm(0));
+ NopInst.addOperand(MCOperand::createReg(Mips::ZERO));
+ NopInst.addOperand(MCOperand::createReg(Mips::ZERO));
+ NopInst.addOperand(MCOperand::createImm(0));
}
Instructions.push_back(NopInst);
}
@@ -2172,9 +2172,9 @@ void MipsAsmParser::createAddu(unsigned
SmallVectorImpl<MCInst> &Instructions) {
MCInst AdduInst;
AdduInst.setOpcode(Mips::ADDu);
- AdduInst.addOperand(MCOperand::CreateReg(DstReg));
- AdduInst.addOperand(MCOperand::CreateReg(SrcReg));
- AdduInst.addOperand(MCOperand::CreateReg(TrgReg));
+ AdduInst.addOperand(MCOperand::createReg(DstReg));
+ AdduInst.addOperand(MCOperand::createReg(SrcReg));
+ AdduInst.addOperand(MCOperand::createReg(TrgReg));
Instructions.push_back(AdduInst);
}
Modified: llvm/trunk/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Disassembler/MipsDisassembler.cpp?rev=237275&r1=237274&r2=237275&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Disassembler/MipsDisassembler.cpp (original)
+++ llvm/trunk/lib/Target/Mips/Disassembler/MipsDisassembler.cpp Wed May 13 13:37:00 2015
@@ -490,13 +490,13 @@ static DecodeStatus DecodeINSVE_DF(MCIns
return MCDisassembler::Fail;
// $n
tmp = fieldFromInstruction(insn, 16, NSize);
- MI.addOperand(MCOperand::CreateImm(tmp));
+ MI.addOperand(MCOperand::createImm(tmp));
// $ws
tmp = fieldFromInstruction(insn, 11, 5);
if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
return MCDisassembler::Fail;
// $n2
- MI.addOperand(MCOperand::CreateImm(0));
+ MI.addOperand(MCOperand::createImm(0));
return MCDisassembler::Success;
}
@@ -530,12 +530,12 @@ static DecodeStatus DecodeAddiGroupBranc
MI.setOpcode(Mips::BEQZALC);
if (HasRs)
- MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
+ MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
Rs)));
- MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
+ MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
Rt)));
- MI.addOperand(MCOperand::CreateImm(Imm));
+ MI.addOperand(MCOperand::createImm(Imm));
return MCDisassembler::Success;
}
@@ -569,12 +569,12 @@ static DecodeStatus DecodeDaddiGroupBran
MI.setOpcode(Mips::BNEZALC);
if (HasRs)
- MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
+ MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
Rs)));
- MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
+ MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
Rt)));
- MI.addOperand(MCOperand::CreateImm(Imm));
+ MI.addOperand(MCOperand::createImm(Imm));
return MCDisassembler::Success;
}
@@ -611,13 +611,13 @@ static DecodeStatus DecodeBlezlGroupBran
}
if (HasRs)
- MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
+ MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
Rs)));
- MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
+ MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
Rt)));
- MI.addOperand(MCOperand::CreateImm(Imm));
+ MI.addOperand(MCOperand::createImm(Imm));
return MCDisassembler::Success;
}
@@ -655,13 +655,13 @@ static DecodeStatus DecodeBgtzlGroupBran
}
if (HasRs)
- MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
+ MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
Rs)));
- MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
+ MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
Rt)));
- MI.addOperand(MCOperand::CreateImm(Imm));
+ MI.addOperand(MCOperand::createImm(Imm));
return MCDisassembler::Success;
}
@@ -703,14 +703,14 @@ static DecodeStatus DecodeBgtzGroupBranc
}
if (HasRs)
- MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
+ MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
Rs)));
if (HasRt)
- MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
+ MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
Rt)));
- MI.addOperand(MCOperand::CreateImm(Imm));
+ MI.addOperand(MCOperand::createImm(Imm));
return MCDisassembler::Success;
}
@@ -747,12 +747,12 @@ static DecodeStatus DecodeBlezGroupBranc
}
if (HasRs)
- MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
+ MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
Rs)));
- MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
+ MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
Rt)));
- MI.addOperand(MCOperand::CreateImm(Imm));
+ MI.addOperand(MCOperand::createImm(Imm));
return MCDisassembler::Success;
}
@@ -929,7 +929,7 @@ static DecodeStatus DecodeGPR64RegisterC
return MCDisassembler::Fail;
unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo);
- Inst.addOperand(MCOperand::CreateReg(Reg));
+ Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success;
}
@@ -940,7 +940,7 @@ static DecodeStatus DecodeGPRMM16Registe
if (RegNo > 7)
return MCDisassembler::Fail;
unsigned Reg = getReg(Decoder, Mips::GPRMM16RegClassID, RegNo);
- Inst.addOperand(MCOperand::CreateReg(Reg));
+ Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success;
}
@@ -951,7 +951,7 @@ static DecodeStatus DecodeGPRMM16ZeroReg
if (RegNo > 7)
return MCDisassembler::Fail;
unsigned Reg = getReg(Decoder, Mips::GPRMM16ZeroRegClassID, RegNo);
- Inst.addOperand(MCOperand::CreateReg(Reg));
+ Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success;
}
@@ -962,7 +962,7 @@ static DecodeStatus DecodeGPRMM16MovePRe
if (RegNo > 7)
return MCDisassembler::Fail;
unsigned Reg = getReg(Decoder, Mips::GPRMM16MovePRegClassID, RegNo);
- Inst.addOperand(MCOperand::CreateReg(Reg));
+ Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success;
}
@@ -973,7 +973,7 @@ static DecodeStatus DecodeGPR32RegisterC
if (RegNo > 31)
return MCDisassembler::Fail;
unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo);
- Inst.addOperand(MCOperand::CreateReg(Reg));
+ Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success;
}
@@ -1002,7 +1002,7 @@ static DecodeStatus DecodeFGR64RegisterC
return MCDisassembler::Fail;
unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo);
- Inst.addOperand(MCOperand::CreateReg(Reg));
+ Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success;
}
@@ -1014,7 +1014,7 @@ static DecodeStatus DecodeFGR32RegisterC
return MCDisassembler::Fail;
unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo);
- Inst.addOperand(MCOperand::CreateReg(Reg));
+ Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success;
}
@@ -1025,7 +1025,7 @@ static DecodeStatus DecodeCCRRegisterCla
if (RegNo > 31)
return MCDisassembler::Fail;
unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo);
- Inst.addOperand(MCOperand::CreateReg(Reg));
+ Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success;
}
@@ -1036,7 +1036,7 @@ static DecodeStatus DecodeFCCRegisterCla
if (RegNo > 7)
return MCDisassembler::Fail;
unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo);
- Inst.addOperand(MCOperand::CreateReg(Reg));
+ Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success;
}
@@ -1047,7 +1047,7 @@ static DecodeStatus DecodeFGRCCRegisterC
return MCDisassembler::Fail;
unsigned Reg = getReg(Decoder, Mips::FGRCCRegClassID, RegNo);
- Inst.addOperand(MCOperand::CreateReg(Reg));
+ Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success;
}
@@ -1064,12 +1064,12 @@ static DecodeStatus DecodeMem(MCInst &In
if(Inst.getOpcode() == Mips::SC ||
Inst.getOpcode() == Mips::SCD){
- Inst.addOperand(MCOperand::CreateReg(Reg));
+ Inst.addOperand(MCOperand::createReg(Reg));
}
- Inst.addOperand(MCOperand::CreateReg(Reg));
- Inst.addOperand(MCOperand::CreateReg(Base));
- Inst.addOperand(MCOperand::CreateImm(Offset));
+ Inst.addOperand(MCOperand::createReg(Reg));
+ Inst.addOperand(MCOperand::createReg(Base));
+ Inst.addOperand(MCOperand::createImm(Offset));
return MCDisassembler::Success;
}
@@ -1084,9 +1084,9 @@ static DecodeStatus DecodeCacheOp(MCInst
Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
- Inst.addOperand(MCOperand::CreateReg(Base));
- Inst.addOperand(MCOperand::CreateImm(Offset));
- Inst.addOperand(MCOperand::CreateImm(Hint));
+ Inst.addOperand(MCOperand::createReg(Base));
+ Inst.addOperand(MCOperand::createImm(Offset));
+ Inst.addOperand(MCOperand::createImm(Hint));
return MCDisassembler::Success;
}
@@ -1101,9 +1101,9 @@ static DecodeStatus DecodeCacheOpMM(MCIn
Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
- Inst.addOperand(MCOperand::CreateReg(Base));
- Inst.addOperand(MCOperand::CreateImm(Offset));
- Inst.addOperand(MCOperand::CreateImm(Hint));
+ Inst.addOperand(MCOperand::createReg(Base));
+ Inst.addOperand(MCOperand::createImm(Offset));
+ Inst.addOperand(MCOperand::createImm(Hint));
return MCDisassembler::Success;
}
@@ -1118,9 +1118,9 @@ static DecodeStatus DecodeCacheOpR6(MCIn
Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
- Inst.addOperand(MCOperand::CreateReg(Base));
- Inst.addOperand(MCOperand::CreateImm(Offset));
- Inst.addOperand(MCOperand::CreateImm(Hint));
+ Inst.addOperand(MCOperand::createReg(Base));
+ Inst.addOperand(MCOperand::createImm(Offset));
+ Inst.addOperand(MCOperand::createImm(Hint));
return MCDisassembler::Success;
}
@@ -1134,8 +1134,8 @@ static DecodeStatus DecodeSyncI(MCInst &
Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
- Inst.addOperand(MCOperand::CreateReg(Base));
- Inst.addOperand(MCOperand::CreateImm(Offset));
+ Inst.addOperand(MCOperand::createReg(Base));
+ Inst.addOperand(MCOperand::createImm(Offset));
return MCDisassembler::Success;
}
@@ -1149,8 +1149,8 @@ static DecodeStatus DecodeMSA128Mem(MCIn
Reg = getReg(Decoder, Mips::MSA128BRegClassID, Reg);
Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
- Inst.addOperand(MCOperand::CreateReg(Reg));
- Inst.addOperand(MCOperand::CreateReg(Base));
+ Inst.addOperand(MCOperand::createReg(Reg));
+ Inst.addOperand(MCOperand::createReg(Base));
// The immediate field of an LD/ST instruction is scaled which means it must
// be multiplied (when decoding) by the size (in bytes) of the instructions'
@@ -1167,19 +1167,19 @@ static DecodeStatus DecodeMSA128Mem(MCIn
break;
case Mips::LD_B:
case Mips::ST_B:
- Inst.addOperand(MCOperand::CreateImm(Offset));
+ Inst.addOperand(MCOperand::createImm(Offset));
break;
case Mips::LD_H:
case Mips::ST_H:
- Inst.addOperand(MCOperand::CreateImm(Offset * 2));
+ Inst.addOperand(MCOperand::createImm(Offset * 2));
break;
case Mips::LD_W:
case Mips::ST_W:
- Inst.addOperand(MCOperand::CreateImm(Offset * 4));
+ Inst.addOperand(MCOperand::createImm(Offset * 4));
break;
case Mips::LD_D:
case Mips::ST_D:
- Inst.addOperand(MCOperand::CreateImm(Offset * 8));
+ Inst.addOperand(MCOperand::createImm(Offset * 8));
break;
}
@@ -1218,20 +1218,20 @@ static DecodeStatus DecodeMemMMImm4(MCIn
switch (Inst.getOpcode()) {
case Mips::LBU16_MM:
if (Offset == 0xf)
- Inst.addOperand(MCOperand::CreateImm(-1));
+ Inst.addOperand(MCOperand::createImm(-1));
else
- Inst.addOperand(MCOperand::CreateImm(Offset));
+ Inst.addOperand(MCOperand::createImm(Offset));
break;
case Mips::SB16_MM:
- Inst.addOperand(MCOperand::CreateImm(Offset));
+ Inst.addOperand(MCOperand::createImm(Offset));
break;
case Mips::LHU16_MM:
case Mips::SH16_MM:
- Inst.addOperand(MCOperand::CreateImm(Offset << 1));
+ Inst.addOperand(MCOperand::createImm(Offset << 1));
break;
case Mips::LW16_MM:
case Mips::SW16_MM:
- Inst.addOperand(MCOperand::CreateImm(Offset << 2));
+ Inst.addOperand(MCOperand::createImm(Offset << 2));
break;
}
@@ -1247,9 +1247,9 @@ static DecodeStatus DecodeMemMMSPImm5Lsl
Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
- Inst.addOperand(MCOperand::CreateReg(Reg));
- Inst.addOperand(MCOperand::CreateReg(Mips::SP));
- Inst.addOperand(MCOperand::CreateImm(Offset << 2));
+ Inst.addOperand(MCOperand::createReg(Reg));
+ Inst.addOperand(MCOperand::createReg(Mips::SP));
+ Inst.addOperand(MCOperand::createImm(Offset << 2));
return MCDisassembler::Success;
}
@@ -1263,9 +1263,9 @@ static DecodeStatus DecodeMemMMGPImm7Lsl
Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
- Inst.addOperand(MCOperand::CreateReg(Reg));
- Inst.addOperand(MCOperand::CreateReg(Mips::GP));
- Inst.addOperand(MCOperand::CreateImm(Offset << 2));
+ Inst.addOperand(MCOperand::createReg(Reg));
+ Inst.addOperand(MCOperand::createReg(Mips::GP));
+ Inst.addOperand(MCOperand::createImm(Offset << 2));
return MCDisassembler::Success;
}
@@ -1280,8 +1280,8 @@ static DecodeStatus DecodeMemMMReglistIm
== MCDisassembler::Fail)
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateReg(Mips::SP));
- Inst.addOperand(MCOperand::CreateImm(Offset << 2));
+ Inst.addOperand(MCOperand::createReg(Mips::SP));
+ Inst.addOperand(MCOperand::createImm(Offset << 2));
return MCDisassembler::Success;
}
@@ -1303,19 +1303,19 @@ static DecodeStatus DecodeMemMMImm12(MCI
if (DecodeRegListOperand(Inst, Insn, Address, Decoder)
== MCDisassembler::Fail)
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateReg(Base));
- Inst.addOperand(MCOperand::CreateImm(Offset));
+ Inst.addOperand(MCOperand::createReg(Base));
+ Inst.addOperand(MCOperand::createImm(Offset));
break;
case Mips::SC_MM:
- Inst.addOperand(MCOperand::CreateReg(Reg));
+ Inst.addOperand(MCOperand::createReg(Reg));
// fallthrough
default:
- Inst.addOperand(MCOperand::CreateReg(Reg));
+ Inst.addOperand(MCOperand::createReg(Reg));
if (Inst.getOpcode() == Mips::LWP_MM || Inst.getOpcode() == Mips::SWP_MM)
- Inst.addOperand(MCOperand::CreateReg(Reg+1));
+ Inst.addOperand(MCOperand::createReg(Reg+1));
- Inst.addOperand(MCOperand::CreateReg(Base));
- Inst.addOperand(MCOperand::CreateImm(Offset));
+ Inst.addOperand(MCOperand::createReg(Base));
+ Inst.addOperand(MCOperand::createImm(Offset));
}
return MCDisassembler::Success;
@@ -1332,9 +1332,9 @@ static DecodeStatus DecodeMemMMImm16(MCI
Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
- Inst.addOperand(MCOperand::CreateReg(Reg));
- Inst.addOperand(MCOperand::CreateReg(Base));
- Inst.addOperand(MCOperand::CreateImm(Offset));
+ Inst.addOperand(MCOperand::createReg(Reg));
+ Inst.addOperand(MCOperand::createReg(Base));
+ Inst.addOperand(MCOperand::createImm(Offset));
return MCDisassembler::Success;
}
@@ -1350,9 +1350,9 @@ static DecodeStatus DecodeFMem(MCInst &I
Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg);
Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
- Inst.addOperand(MCOperand::CreateReg(Reg));
- Inst.addOperand(MCOperand::CreateReg(Base));
- Inst.addOperand(MCOperand::CreateImm(Offset));
+ Inst.addOperand(MCOperand::createReg(Reg));
+ Inst.addOperand(MCOperand::createReg(Base));
+ Inst.addOperand(MCOperand::createImm(Offset));
return MCDisassembler::Success;
}
@@ -1368,9 +1368,9 @@ static DecodeStatus DecodeFMem2(MCInst &
Reg = getReg(Decoder, Mips::COP2RegClassID, Reg);
Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
- Inst.addOperand(MCOperand::CreateReg(Reg));
- Inst.addOperand(MCOperand::CreateReg(Base));
- Inst.addOperand(MCOperand::CreateImm(Offset));
+ Inst.addOperand(MCOperand::createReg(Reg));
+ Inst.addOperand(MCOperand::createReg(Base));
+ Inst.addOperand(MCOperand::createImm(Offset));
return MCDisassembler::Success;
}
@@ -1386,9 +1386,9 @@ static DecodeStatus DecodeFMem3(MCInst &
Reg = getReg(Decoder, Mips::COP3RegClassID, Reg);
Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
- Inst.addOperand(MCOperand::CreateReg(Reg));
- Inst.addOperand(MCOperand::CreateReg(Base));
- Inst.addOperand(MCOperand::CreateImm(Offset));
+ Inst.addOperand(MCOperand::createReg(Reg));
+ Inst.addOperand(MCOperand::createReg(Base));
+ Inst.addOperand(MCOperand::createImm(Offset));
return MCDisassembler::Success;
}
@@ -1404,9 +1404,9 @@ static DecodeStatus DecodeFMemCop2R6(MCI
Reg = getReg(Decoder, Mips::COP2RegClassID, Reg);
Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
- Inst.addOperand(MCOperand::CreateReg(Reg));
- Inst.addOperand(MCOperand::CreateReg(Base));
- Inst.addOperand(MCOperand::CreateImm(Offset));
+ Inst.addOperand(MCOperand::createReg(Reg));
+ Inst.addOperand(MCOperand::createReg(Base));
+ Inst.addOperand(MCOperand::createImm(Offset));
return MCDisassembler::Success;
}
@@ -1422,12 +1422,12 @@ static DecodeStatus DecodeSpecial3LlSc(M
Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
if(Inst.getOpcode() == Mips::SC_R6 || Inst.getOpcode() == Mips::SCD_R6){
- Inst.addOperand(MCOperand::CreateReg(Rt));
+ Inst.addOperand(MCOperand::createReg(Rt));
}
- Inst.addOperand(MCOperand::CreateReg(Rt));
- Inst.addOperand(MCOperand::CreateReg(Base));
- Inst.addOperand(MCOperand::CreateImm(Offset));
+ Inst.addOperand(MCOperand::createReg(Rt));
+ Inst.addOperand(MCOperand::createReg(Base));
+ Inst.addOperand(MCOperand::createImm(Offset));
return MCDisassembler::Success;
}
@@ -1439,7 +1439,7 @@ static DecodeStatus DecodeHWRegsRegister
// Currently only hardware register 29 is supported.
if (RegNo != 29)
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateReg(Mips::HWR29));
+ Inst.addOperand(MCOperand::createReg(Mips::HWR29));
return MCDisassembler::Success;
}
@@ -1452,7 +1452,7 @@ static DecodeStatus DecodeAFGR64Register
;
unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2);
- Inst.addOperand(MCOperand::CreateReg(Reg));
+ Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success;
}
@@ -1464,7 +1464,7 @@ static DecodeStatus DecodeACC64DSPRegist
return MCDisassembler::Fail;
unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo);
- Inst.addOperand(MCOperand::CreateReg(Reg));
+ Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success;
}
@@ -1476,7 +1476,7 @@ static DecodeStatus DecodeHI32DSPRegiste
return MCDisassembler::Fail;
unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo);
- Inst.addOperand(MCOperand::CreateReg(Reg));
+ Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success;
}
@@ -1488,7 +1488,7 @@ static DecodeStatus DecodeLO32DSPRegiste
return MCDisassembler::Fail;
unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo);
- Inst.addOperand(MCOperand::CreateReg(Reg));
+ Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success;
}
@@ -1500,7 +1500,7 @@ static DecodeStatus DecodeMSA128BRegiste
return MCDisassembler::Fail;
unsigned Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo);
- Inst.addOperand(MCOperand::CreateReg(Reg));
+ Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success;
}
@@ -1512,7 +1512,7 @@ static DecodeStatus DecodeMSA128HRegiste
return MCDisassembler::Fail;
unsigned Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo);
- Inst.addOperand(MCOperand::CreateReg(Reg));
+ Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success;
}
@@ -1524,7 +1524,7 @@ static DecodeStatus DecodeMSA128WRegiste
return MCDisassembler::Fail;
unsigned Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo);
- Inst.addOperand(MCOperand::CreateReg(Reg));
+ Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success;
}
@@ -1536,7 +1536,7 @@ static DecodeStatus DecodeMSA128DRegiste
return MCDisassembler::Fail;
unsigned Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo);
- Inst.addOperand(MCOperand::CreateReg(Reg));
+ Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success;
}
@@ -1548,7 +1548,7 @@ static DecodeStatus DecodeMSACtrlRegiste
return MCDisassembler::Fail;
unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo);
- Inst.addOperand(MCOperand::CreateReg(Reg));
+ Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success;
}
@@ -1560,7 +1560,7 @@ static DecodeStatus DecodeCOP2RegisterCl
return MCDisassembler::Fail;
unsigned Reg = getReg(Decoder, Mips::COP2RegClassID, RegNo);
- Inst.addOperand(MCOperand::CreateReg(Reg));
+ Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success;
}
@@ -1569,7 +1569,7 @@ static DecodeStatus DecodeBranchTarget(M
uint64_t Address,
const void *Decoder) {
int32_t BranchOffset = (SignExtend32<16>(Offset) * 4) + 4;
- Inst.addOperand(MCOperand::CreateImm(BranchOffset));
+ Inst.addOperand(MCOperand::createImm(BranchOffset));
return MCDisassembler::Success;
}
@@ -1579,7 +1579,7 @@ static DecodeStatus DecodeJumpTarget(MCI
const void *Decoder) {
unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2;
- Inst.addOperand(MCOperand::CreateImm(JumpOffset));
+ Inst.addOperand(MCOperand::createImm(JumpOffset));
return MCDisassembler::Success;
}
@@ -1589,7 +1589,7 @@ static DecodeStatus DecodeBranchTarget21
const void *Decoder) {
int32_t BranchOffset = SignExtend32<21>(Offset) * 4;
- Inst.addOperand(MCOperand::CreateImm(BranchOffset));
+ Inst.addOperand(MCOperand::createImm(BranchOffset));
return MCDisassembler::Success;
}
@@ -1599,7 +1599,7 @@ static DecodeStatus DecodeBranchTarget26
const void *Decoder) {
int32_t BranchOffset = SignExtend32<26>(Offset) * 4;
- Inst.addOperand(MCOperand::CreateImm(BranchOffset));
+ Inst.addOperand(MCOperand::createImm(BranchOffset));
return MCDisassembler::Success;
}
@@ -1608,7 +1608,7 @@ static DecodeStatus DecodeBranchTarget7M
uint64_t Address,
const void *Decoder) {
int32_t BranchOffset = SignExtend32<7>(Offset) << 1;
- Inst.addOperand(MCOperand::CreateImm(BranchOffset));
+ Inst.addOperand(MCOperand::createImm(BranchOffset));
return MCDisassembler::Success;
}
@@ -1617,7 +1617,7 @@ static DecodeStatus DecodeBranchTarget10
uint64_t Address,
const void *Decoder) {
int32_t BranchOffset = SignExtend32<10>(Offset) << 1;
- Inst.addOperand(MCOperand::CreateImm(BranchOffset));
+ Inst.addOperand(MCOperand::createImm(BranchOffset));
return MCDisassembler::Success;
}
@@ -1626,7 +1626,7 @@ static DecodeStatus DecodeBranchTargetMM
uint64_t Address,
const void *Decoder) {
int32_t BranchOffset = SignExtend32<16>(Offset) * 2;
- Inst.addOperand(MCOperand::CreateImm(BranchOffset));
+ Inst.addOperand(MCOperand::createImm(BranchOffset));
return MCDisassembler::Success;
}
@@ -1635,7 +1635,7 @@ static DecodeStatus DecodeJumpTargetMM(M
uint64_t Address,
const void *Decoder) {
unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1;
- Inst.addOperand(MCOperand::CreateImm(JumpOffset));
+ Inst.addOperand(MCOperand::createImm(JumpOffset));
return MCDisassembler::Success;
}
@@ -1644,11 +1644,11 @@ static DecodeStatus DecodeAddiur2Simm7(M
uint64_t Address,
const void *Decoder) {
if (Value == 0)
- Inst.addOperand(MCOperand::CreateImm(1));
+ Inst.addOperand(MCOperand::createImm(1));
else if (Value == 0x7)
- Inst.addOperand(MCOperand::CreateImm(-1));
+ Inst.addOperand(MCOperand::createImm(-1));
else
- Inst.addOperand(MCOperand::CreateImm(Value << 2));
+ Inst.addOperand(MCOperand::createImm(Value << 2));
return MCDisassembler::Success;
}
@@ -1656,7 +1656,7 @@ static DecodeStatus DecodeUImm6Lsl2(MCIn
unsigned Value,
uint64_t Address,
const void *Decoder) {
- Inst.addOperand(MCOperand::CreateImm(Value << 2));
+ Inst.addOperand(MCOperand::createImm(Value << 2));
return MCDisassembler::Success;
}
@@ -1665,9 +1665,9 @@ static DecodeStatus DecodeLiSimm7(MCInst
uint64_t Address,
const void *Decoder) {
if (Value == 0x7F)
- Inst.addOperand(MCOperand::CreateImm(-1));
+ Inst.addOperand(MCOperand::createImm(-1));
else
- Inst.addOperand(MCOperand::CreateImm(Value));
+ Inst.addOperand(MCOperand::createImm(Value));
return MCDisassembler::Success;
}
@@ -1675,7 +1675,7 @@ static DecodeStatus DecodeSimm4(MCInst &
unsigned Value,
uint64_t Address,
const void *Decoder) {
- Inst.addOperand(MCOperand::CreateImm(SignExtend32<4>(Value)));
+ Inst.addOperand(MCOperand::createImm(SignExtend32<4>(Value)));
return MCDisassembler::Success;
}
@@ -1683,7 +1683,7 @@ static DecodeStatus DecodeSimm16(MCInst
unsigned Insn,
uint64_t Address,
const void *Decoder) {
- Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Insn)));
+ Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Insn)));
return MCDisassembler::Success;
}
@@ -1692,7 +1692,7 @@ static DecodeStatus DecodeLSAImm(MCInst
uint64_t Address,
const void *Decoder) {
// We add one to the immediate field as it was encoded as 'imm - 1'.
- Inst.addOperand(MCOperand::CreateImm(Insn + 1));
+ Inst.addOperand(MCOperand::createImm(Insn + 1));
return MCDisassembler::Success;
}
@@ -1703,7 +1703,7 @@ static DecodeStatus DecodeInsSize(MCInst
// First we need to grab the pos(lsb) from MCInst.
int Pos = Inst.getOperand(2).getImm();
int Size = (int) Insn - Pos + 1;
- Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size)));
+ Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Size)));
return MCDisassembler::Success;
}
@@ -1712,19 +1712,19 @@ static DecodeStatus DecodeExtSize(MCInst
uint64_t Address,
const void *Decoder) {
int Size = (int) Insn + 1;
- Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size)));
+ Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Size)));
return MCDisassembler::Success;
}
static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) {
- Inst.addOperand(MCOperand::CreateImm(SignExtend32<19>(Insn) * 4));
+ Inst.addOperand(MCOperand::createImm(SignExtend32<19>(Insn) * 4));
return MCDisassembler::Success;
}
static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) {
- Inst.addOperand(MCOperand::CreateImm(SignExtend32<18>(Insn) * 8));
+ Inst.addOperand(MCOperand::createImm(SignExtend32<18>(Insn) * 8));
return MCDisassembler::Success;
}
@@ -1738,7 +1738,7 @@ static DecodeStatus DecodeSimm9SP(MCInst
case 511: DecodedValue = -257; break;
default: DecodedValue = SignExtend32<9>(Insn); break;
}
- Inst.addOperand(MCOperand::CreateImm(DecodedValue * 4));
+ Inst.addOperand(MCOperand::createImm(DecodedValue * 4));
return MCDisassembler::Success;
}
@@ -1748,13 +1748,13 @@ static DecodeStatus DecodeANDI16Imm(MCIn
assert(Insn < 16);
int32_t DecodedValues[] = {128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64,
255, 32768, 65535};
- Inst.addOperand(MCOperand::CreateImm(DecodedValues[Insn]));
+ Inst.addOperand(MCOperand::createImm(DecodedValues[Insn]));
return MCDisassembler::Success;
}
static DecodeStatus DecodeUImm5lsl2(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) {
- Inst.addOperand(MCOperand::CreateImm(Insn << 2));
+ Inst.addOperand(MCOperand::createImm(Insn << 2));
return MCDisassembler::Success;
}
@@ -1773,10 +1773,10 @@ static DecodeStatus DecodeRegListOperand
RegNum = RegLst & 0xf;
for (unsigned i = 0; i < RegNum; i++)
- Inst.addOperand(MCOperand::CreateReg(Regs[i]));
+ Inst.addOperand(MCOperand::createReg(Regs[i]));
if (RegLst & 0x10)
- Inst.addOperand(MCOperand::CreateReg(Mips::RA));
+ Inst.addOperand(MCOperand::createReg(Mips::RA));
return MCDisassembler::Success;
}
@@ -1789,9 +1789,9 @@ static DecodeStatus DecodeRegListOperand
unsigned RegNum = RegLst & 0x3;
for (unsigned i = 0; i <= RegNum; i++)
- Inst.addOperand(MCOperand::CreateReg(Regs[i]));
+ Inst.addOperand(MCOperand::createReg(Regs[i]));
- Inst.addOperand(MCOperand::CreateReg(Mips::RA));
+ Inst.addOperand(MCOperand::createReg(Mips::RA));
return MCDisassembler::Success;
}
@@ -1805,36 +1805,36 @@ static DecodeStatus DecodeMovePRegPair(M
default:
return MCDisassembler::Fail;
case 0:
- Inst.addOperand(MCOperand::CreateReg(Mips::A1));
- Inst.addOperand(MCOperand::CreateReg(Mips::A2));
+ Inst.addOperand(MCOperand::createReg(Mips::A1));
+ Inst.addOperand(MCOperand::createReg(Mips::A2));
break;
case 1:
- Inst.addOperand(MCOperand::CreateReg(Mips::A1));
- Inst.addOperand(MCOperand::CreateReg(Mips::A3));
+ Inst.addOperand(MCOperand::createReg(Mips::A1));
+ Inst.addOperand(MCOperand::createReg(Mips::A3));
break;
case 2:
- Inst.addOperand(MCOperand::CreateReg(Mips::A2));
- Inst.addOperand(MCOperand::CreateReg(Mips::A3));
+ Inst.addOperand(MCOperand::createReg(Mips::A2));
+ Inst.addOperand(MCOperand::createReg(Mips::A3));
break;
case 3:
- Inst.addOperand(MCOperand::CreateReg(Mips::A0));
- Inst.addOperand(MCOperand::CreateReg(Mips::S5));
+ Inst.addOperand(MCOperand::createReg(Mips::A0));
+ Inst.addOperand(MCOperand::createReg(Mips::S5));
break;
case 4:
- Inst.addOperand(MCOperand::CreateReg(Mips::A0));
- Inst.addOperand(MCOperand::CreateReg(Mips::S6));
+ Inst.addOperand(MCOperand::createReg(Mips::A0));
+ Inst.addOperand(MCOperand::createReg(Mips::S6));
break;
case 5:
- Inst.addOperand(MCOperand::CreateReg(Mips::A0));
- Inst.addOperand(MCOperand::CreateReg(Mips::A1));
+ Inst.addOperand(MCOperand::createReg(Mips::A0));
+ Inst.addOperand(MCOperand::createReg(Mips::A1));
break;
case 6:
- Inst.addOperand(MCOperand::CreateReg(Mips::A0));
- Inst.addOperand(MCOperand::CreateReg(Mips::A2));
+ Inst.addOperand(MCOperand::createReg(Mips::A0));
+ Inst.addOperand(MCOperand::createReg(Mips::A2));
break;
case 7:
- Inst.addOperand(MCOperand::CreateReg(Mips::A0));
- Inst.addOperand(MCOperand::CreateReg(Mips::A3));
+ Inst.addOperand(MCOperand::createReg(Mips::A0));
+ Inst.addOperand(MCOperand::createReg(Mips::A3));
break;
}
@@ -1843,6 +1843,6 @@ static DecodeStatus DecodeMovePRegPair(M
static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) {
- Inst.addOperand(MCOperand::CreateImm(SignExtend32<23>(Insn) << 2));
+ Inst.addOperand(MCOperand::createImm(SignExtend32<23>(Insn) << 2));
return MCDisassembler::Success;
}
Modified: llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsNaClELFStreamer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsNaClELFStreamer.cpp?rev=237275&r1=237274&r2=237275&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsNaClELFStreamer.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsNaClELFStreamer.cpp Wed May 13 13:37:00 2015
@@ -94,9 +94,9 @@ private:
const MCSubtargetInfo &STI) {
MCInst MaskInst;
MaskInst.setOpcode(Mips::AND);
- MaskInst.addOperand(MCOperand::CreateReg(AddrReg));
- MaskInst.addOperand(MCOperand::CreateReg(AddrReg));
- MaskInst.addOperand(MCOperand::CreateReg(MaskReg));
+ MaskInst.addOperand(MCOperand::createReg(AddrReg));
+ MaskInst.addOperand(MCOperand::createReg(AddrReg));
+ MaskInst.addOperand(MCOperand::createReg(MaskReg));
MipsELFStreamer::EmitInstruction(MaskInst, STI);
}
Modified: llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp?rev=237275&r1=237274&r2=237275&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp Wed May 13 13:37:00 2015
@@ -697,28 +697,28 @@ void MipsTargetELFStreamer::emitDirectiv
MCInst TmpInst;
TmpInst.setOpcode(Mips::LUi);
- TmpInst.addOperand(MCOperand::CreateReg(Mips::GP));
+ TmpInst.addOperand(MCOperand::createReg(Mips::GP));
const MCSymbolRefExpr *HiSym = MCSymbolRefExpr::Create(
"_gp_disp", MCSymbolRefExpr::VK_Mips_ABS_HI, MCA.getContext());
- TmpInst.addOperand(MCOperand::CreateExpr(HiSym));
+ TmpInst.addOperand(MCOperand::createExpr(HiSym));
getStreamer().EmitInstruction(TmpInst, STI);
TmpInst.clear();
TmpInst.setOpcode(Mips::ADDiu);
- TmpInst.addOperand(MCOperand::CreateReg(Mips::GP));
- TmpInst.addOperand(MCOperand::CreateReg(Mips::GP));
+ TmpInst.addOperand(MCOperand::createReg(Mips::GP));
+ TmpInst.addOperand(MCOperand::createReg(Mips::GP));
const MCSymbolRefExpr *LoSym = MCSymbolRefExpr::Create(
"_gp_disp", MCSymbolRefExpr::VK_Mips_ABS_LO, MCA.getContext());
- TmpInst.addOperand(MCOperand::CreateExpr(LoSym));
+ TmpInst.addOperand(MCOperand::createExpr(LoSym));
getStreamer().EmitInstruction(TmpInst, STI);
TmpInst.clear();
TmpInst.setOpcode(Mips::ADDu);
- TmpInst.addOperand(MCOperand::CreateReg(Mips::GP));
- TmpInst.addOperand(MCOperand::CreateReg(Mips::GP));
- TmpInst.addOperand(MCOperand::CreateReg(RegNo));
+ TmpInst.addOperand(MCOperand::createReg(Mips::GP));
+ TmpInst.addOperand(MCOperand::createReg(Mips::GP));
+ TmpInst.addOperand(MCOperand::createReg(RegNo));
getStreamer().EmitInstruction(TmpInst, STI);
forbidModuleDirective();
@@ -739,15 +739,15 @@ void MipsTargetELFStreamer::emitDirectiv
if (IsReg) {
// move $save, $gpreg
Inst.setOpcode(Mips::DADDu);
- Inst.addOperand(MCOperand::CreateReg(RegOrOffset));
- Inst.addOperand(MCOperand::CreateReg(Mips::GP));
- Inst.addOperand(MCOperand::CreateReg(Mips::ZERO));
+ Inst.addOperand(MCOperand::createReg(RegOrOffset));
+ Inst.addOperand(MCOperand::createReg(Mips::GP));
+ Inst.addOperand(MCOperand::createReg(Mips::ZERO));
} else {
// sd $gpreg, offset($sp)
Inst.setOpcode(Mips::SD);
- Inst.addOperand(MCOperand::CreateReg(Mips::GP));
- Inst.addOperand(MCOperand::CreateReg(Mips::SP));
- Inst.addOperand(MCOperand::CreateImm(RegOrOffset));
+ Inst.addOperand(MCOperand::createReg(Mips::GP));
+ Inst.addOperand(MCOperand::createReg(Mips::SP));
+ Inst.addOperand(MCOperand::createImm(RegOrOffset));
}
getStreamer().EmitInstruction(Inst, STI);
Inst.clear();
@@ -759,24 +759,24 @@ void MipsTargetELFStreamer::emitDirectiv
// lui $gp, %hi(%neg(%gp_rel(funcSym)))
Inst.setOpcode(Mips::LUi);
- Inst.addOperand(MCOperand::CreateReg(Mips::GP));
- Inst.addOperand(MCOperand::CreateExpr(HiExpr));
+ Inst.addOperand(MCOperand::createReg(Mips::GP));
+ Inst.addOperand(MCOperand::createExpr(HiExpr));
getStreamer().EmitInstruction(Inst, STI);
Inst.clear();
// addiu $gp, $gp, %lo(%neg(%gp_rel(funcSym)))
Inst.setOpcode(Mips::ADDiu);
- Inst.addOperand(MCOperand::CreateReg(Mips::GP));
- Inst.addOperand(MCOperand::CreateReg(Mips::GP));
- Inst.addOperand(MCOperand::CreateExpr(LoExpr));
+ Inst.addOperand(MCOperand::createReg(Mips::GP));
+ Inst.addOperand(MCOperand::createReg(Mips::GP));
+ Inst.addOperand(MCOperand::createExpr(LoExpr));
getStreamer().EmitInstruction(Inst, STI);
Inst.clear();
// daddu $gp, $gp, $funcreg
Inst.setOpcode(Mips::DADDu);
- Inst.addOperand(MCOperand::CreateReg(Mips::GP));
- Inst.addOperand(MCOperand::CreateReg(Mips::GP));
- Inst.addOperand(MCOperand::CreateReg(RegNo));
+ Inst.addOperand(MCOperand::createReg(Mips::GP));
+ Inst.addOperand(MCOperand::createReg(Mips::GP));
+ Inst.addOperand(MCOperand::createReg(RegNo));
getStreamer().EmitInstruction(Inst, STI);
forbidModuleDirective();
Modified: llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp?rev=237275&r1=237274&r2=237275&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp Wed May 13 13:37:00 2015
@@ -121,7 +121,7 @@ void MipsAsmPrinter::emitPseudoIndirectB
if (HasLinkReg) {
unsigned ZeroReg = Subtarget->isGP64bit() ? Mips::ZERO_64 : Mips::ZERO;
- TmpInst0.addOperand(MCOperand::CreateReg(ZeroReg));
+ TmpInst0.addOperand(MCOperand::createReg(ZeroReg));
}
lowerOperand(MI->getOperand(0), MCOp);
@@ -779,7 +779,7 @@ void MipsAsmPrinter::EmitJal(const MCSub
MCInst I;
I.setOpcode(Mips::JAL);
I.addOperand(
- MCOperand::CreateExpr(MCSymbolRefExpr::Create(Symbol, OutContext)));
+ MCOperand::createExpr(MCSymbolRefExpr::Create(Symbol, OutContext)));
OutStreamer->EmitInstruction(I, STI);
}
@@ -787,7 +787,7 @@ void MipsAsmPrinter::EmitInstrReg(const
unsigned Reg) {
MCInst I;
I.setOpcode(Opcode);
- I.addOperand(MCOperand::CreateReg(Reg));
+ I.addOperand(MCOperand::createReg(Reg));
OutStreamer->EmitInstruction(I, STI);
}
@@ -806,8 +806,8 @@ void MipsAsmPrinter::EmitInstrRegReg(con
Reg2 = Temp;
}
I.setOpcode(Opcode);
- I.addOperand(MCOperand::CreateReg(Reg1));
- I.addOperand(MCOperand::CreateReg(Reg2));
+ I.addOperand(MCOperand::createReg(Reg1));
+ I.addOperand(MCOperand::createReg(Reg2));
OutStreamer->EmitInstruction(I, STI);
}
@@ -816,9 +816,9 @@ void MipsAsmPrinter::EmitInstrRegRegReg(
unsigned Reg2, unsigned Reg3) {
MCInst I;
I.setOpcode(Opcode);
- I.addOperand(MCOperand::CreateReg(Reg1));
- I.addOperand(MCOperand::CreateReg(Reg2));
- I.addOperand(MCOperand::CreateReg(Reg3));
+ I.addOperand(MCOperand::createReg(Reg1));
+ I.addOperand(MCOperand::createReg(Reg2));
+ I.addOperand(MCOperand::createReg(Reg3));
OutStreamer->EmitInstruction(I, STI);
}
Modified: llvm/trunk/lib/Target/Mips/MipsMCInstLower.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsMCInstLower.cpp?rev=237275&r1=237274&r2=237275&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsMCInstLower.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsMCInstLower.cpp Wed May 13 13:37:00 2015
@@ -104,14 +104,14 @@ MCOperand MipsMCInstLower::LowerSymbolOp
const MCSymbolRefExpr *MCSym = MCSymbolRefExpr::Create(Symbol, Kind, *Ctx);
if (!Offset)
- return MCOperand::CreateExpr(MCSym);
+ return MCOperand::createExpr(MCSym);
// Assume offset is never negative.
assert(Offset > 0);
const MCConstantExpr *OffsetExpr = MCConstantExpr::Create(Offset, *Ctx);
const MCBinaryExpr *Add = MCBinaryExpr::CreateAdd(MCSym, OffsetExpr, *Ctx);
- return MCOperand::CreateExpr(Add);
+ return MCOperand::createExpr(Add);
}
/*
@@ -135,9 +135,9 @@ MCOperand MipsMCInstLower::LowerOperand(
case MachineOperand::MO_Register:
// Ignore all implicit register operands.
if (MO.isImplicit()) break;
- return MCOperand::CreateReg(MO.getReg());
+ return MCOperand::createReg(MO.getReg());
case MachineOperand::MO_Immediate:
- return MCOperand::CreateImm(MO.getImm() + offset);
+ return MCOperand::createImm(MO.getImm() + offset);
case MachineOperand::MO_MachineBasicBlock:
case MachineOperand::MO_GlobalAddress:
case MachineOperand::MO_ExternalSymbol:
@@ -159,7 +159,7 @@ MCOperand MipsMCInstLower::createSub(Mac
const MCSymbolRefExpr *Sym2 = MCSymbolRefExpr::Create(BB2->getSymbol(), *Ctx);
const MCBinaryExpr *Sub = MCBinaryExpr::CreateSub(Sym1, Sym2, *Ctx);
- return MCOperand::CreateExpr(MipsMCExpr::Create(Kind, Sub, *Ctx));
+ return MCOperand::createExpr(MipsMCExpr::Create(Kind, Sub, *Ctx));
}
void MipsMCInstLower::
Modified: llvm/trunk/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/NVPTXAsmPrinter.cpp?rev=237275&r1=237274&r2=237275&view=diff
==============================================================================
--- llvm/trunk/lib/Target/NVPTX/NVPTXAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/NVPTX/NVPTXAsmPrinter.cpp Wed May 13 13:37:00 2015
@@ -259,13 +259,13 @@ bool NVPTXAsmPrinter::lowerOperand(const
switch (MO.getType()) {
default: llvm_unreachable("unknown operand type");
case MachineOperand::MO_Register:
- MCOp = MCOperand::CreateReg(encodeVirtualRegister(MO.getReg()));
+ MCOp = MCOperand::createReg(encodeVirtualRegister(MO.getReg()));
break;
case MachineOperand::MO_Immediate:
- MCOp = MCOperand::CreateImm(MO.getImm());
+ MCOp = MCOperand::createImm(MO.getImm());
break;
case MachineOperand::MO_MachineBasicBlock:
- MCOp = MCOperand::CreateExpr(MCSymbolRefExpr::Create(
+ MCOp = MCOperand::createExpr(MCSymbolRefExpr::Create(
MO.getMBB()->getSymbol(), OutContext));
break;
case MachineOperand::MO_ExternalSymbol:
@@ -281,11 +281,11 @@ bool NVPTXAsmPrinter::lowerOperand(const
switch (Cnt->getType()->getTypeID()) {
default: report_fatal_error("Unsupported FP type"); break;
case Type::FloatTyID:
- MCOp = MCOperand::CreateExpr(
+ MCOp = MCOperand::createExpr(
NVPTXFloatMCExpr::CreateConstantFPSingle(Val, OutContext));
break;
case Type::DoubleTyID:
- MCOp = MCOperand::CreateExpr(
+ MCOp = MCOperand::createExpr(
NVPTXFloatMCExpr::CreateConstantFPDouble(Val, OutContext));
break;
}
@@ -335,7 +335,7 @@ MCOperand NVPTXAsmPrinter::GetSymbolRef(
const MCExpr *Expr;
Expr = MCSymbolRefExpr::Create(Symbol, MCSymbolRefExpr::VK_None,
OutContext);
- return MCOperand::CreateExpr(Expr);
+ return MCOperand::createExpr(Expr);
}
void NVPTXAsmPrinter::printReturnValStr(const Function *F, raw_ostream &O) {
Modified: llvm/trunk/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp?rev=237275&r1=237274&r2=237275&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp Wed May 13 13:37:00 2015
@@ -539,22 +539,22 @@ public:
void addRegGPRCOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateReg(RRegs[getReg()]));
+ Inst.addOperand(MCOperand::createReg(RRegs[getReg()]));
}
void addRegGPRCNoR0Operands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateReg(RRegsNoR0[getReg()]));
+ Inst.addOperand(MCOperand::createReg(RRegsNoR0[getReg()]));
}
void addRegG8RCOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateReg(XRegs[getReg()]));
+ Inst.addOperand(MCOperand::createReg(XRegs[getReg()]));
}
void addRegG8RCNoX0Operands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateReg(XRegsNoX0[getReg()]));
+ Inst.addOperand(MCOperand::createReg(XRegsNoX0[getReg()]));
}
void addRegGxRCOperands(MCInst &Inst, unsigned N) const {
@@ -573,83 +573,83 @@ public:
void addRegF4RCOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateReg(FRegs[getReg()]));
+ Inst.addOperand(MCOperand::createReg(FRegs[getReg()]));
}
void addRegF8RCOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateReg(FRegs[getReg()]));
+ Inst.addOperand(MCOperand::createReg(FRegs[getReg()]));
}
void addRegVRRCOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateReg(VRegs[getReg()]));
+ Inst.addOperand(MCOperand::createReg(VRegs[getReg()]));
}
void addRegVSRCOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateReg(VSRegs[getVSReg()]));
+ Inst.addOperand(MCOperand::createReg(VSRegs[getVSReg()]));
}
void addRegVSFRCOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateReg(VSFRegs[getVSReg()]));
+ Inst.addOperand(MCOperand::createReg(VSFRegs[getVSReg()]));
}
void addRegVSSRCOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateReg(VSSRegs[getVSReg()]));
+ Inst.addOperand(MCOperand::createReg(VSSRegs[getVSReg()]));
}
void addRegQFRCOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateReg(QFRegs[getReg()]));
+ Inst.addOperand(MCOperand::createReg(QFRegs[getReg()]));
}
void addRegQSRCOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateReg(QFRegs[getReg()]));
+ Inst.addOperand(MCOperand::createReg(QFRegs[getReg()]));
}
void addRegQBRCOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateReg(QFRegs[getReg()]));
+ Inst.addOperand(MCOperand::createReg(QFRegs[getReg()]));
}
void addRegCRBITRCOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateReg(CRBITRegs[getCRBit()]));
+ Inst.addOperand(MCOperand::createReg(CRBITRegs[getCRBit()]));
}
void addRegCRRCOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateReg(CRRegs[getCCReg()]));
+ Inst.addOperand(MCOperand::createReg(CRRegs[getCCReg()]));
}
void addCRBitMaskOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateReg(CRRegs[getCRBitMask()]));
+ Inst.addOperand(MCOperand::createReg(CRRegs[getCRBitMask()]));
}
void addImmOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
if (Kind == Immediate)
- Inst.addOperand(MCOperand::CreateImm(getImm()));
+ Inst.addOperand(MCOperand::createImm(getImm()));
else
- Inst.addOperand(MCOperand::CreateExpr(getExpr()));
+ Inst.addOperand(MCOperand::createExpr(getExpr()));
}
void addS16ImmOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
switch (Kind) {
case Immediate:
- Inst.addOperand(MCOperand::CreateImm(getImm()));
+ Inst.addOperand(MCOperand::createImm(getImm()));
break;
case ContextImmediate:
- Inst.addOperand(MCOperand::CreateImm(getImmS16Context()));
+ Inst.addOperand(MCOperand::createImm(getImmS16Context()));
break;
default:
- Inst.addOperand(MCOperand::CreateExpr(getExpr()));
+ Inst.addOperand(MCOperand::createExpr(getExpr()));
break;
}
}
@@ -658,13 +658,13 @@ public:
assert(N == 1 && "Invalid number of operands!");
switch (Kind) {
case Immediate:
- Inst.addOperand(MCOperand::CreateImm(getImm()));
+ Inst.addOperand(MCOperand::createImm(getImm()));
break;
case ContextImmediate:
- Inst.addOperand(MCOperand::CreateImm(getImmU16Context()));
+ Inst.addOperand(MCOperand::createImm(getImmU16Context()));
break;
default:
- Inst.addOperand(MCOperand::CreateExpr(getExpr()));
+ Inst.addOperand(MCOperand::createExpr(getExpr()));
break;
}
}
@@ -672,14 +672,14 @@ public:
void addBranchTargetOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
if (Kind == Immediate)
- Inst.addOperand(MCOperand::CreateImm(getImm() / 4));
+ Inst.addOperand(MCOperand::createImm(getImm() / 4));
else
- Inst.addOperand(MCOperand::CreateExpr(getExpr()));
+ Inst.addOperand(MCOperand::createExpr(getExpr()));
}
void addTLSRegOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateExpr(getTLSReg()));
+ Inst.addOperand(MCOperand::createExpr(getTLSReg()));
}
StringRef getToken() const {
@@ -801,24 +801,24 @@ void PPCOperand::print(raw_ostream &OS)
static void
addNegOperand(MCInst &Inst, MCOperand &Op, MCContext &Ctx) {
if (Op.isImm()) {
- Inst.addOperand(MCOperand::CreateImm(-Op.getImm()));
+ Inst.addOperand(MCOperand::createImm(-Op.getImm()));
return;
}
const MCExpr *Expr = Op.getExpr();
if (const MCUnaryExpr *UnExpr = dyn_cast<MCUnaryExpr>(Expr)) {
if (UnExpr->getOpcode() == MCUnaryExpr::Minus) {
- Inst.addOperand(MCOperand::CreateExpr(UnExpr->getSubExpr()));
+ Inst.addOperand(MCOperand::createExpr(UnExpr->getSubExpr()));
return;
}
} else if (const MCBinaryExpr *BinExpr = dyn_cast<MCBinaryExpr>(Expr)) {
if (BinExpr->getOpcode() == MCBinaryExpr::Sub) {
const MCExpr *NE = MCBinaryExpr::CreateSub(BinExpr->getRHS(),
BinExpr->getLHS(), Ctx);
- Inst.addOperand(MCOperand::CreateExpr(NE));
+ Inst.addOperand(MCOperand::createExpr(NE));
return;
}
}
- Inst.addOperand(MCOperand::CreateExpr(MCUnaryExpr::CreateMinus(Expr, Ctx)));
+ Inst.addOperand(MCOperand::createExpr(MCUnaryExpr::CreateMinus(Expr, Ctx)));
}
void PPCAsmParser::ProcessInstruction(MCInst &Inst,
@@ -832,7 +832,7 @@ void PPCAsmParser::ProcessInstruction(MC
MCInst TmpInst;
TmpInst.setOpcode((Opcode == PPC::DCBTx || Opcode == PPC::DCBTT) ?
PPC::DCBT : PPC::DCBTST);
- TmpInst.addOperand(MCOperand::CreateImm(
+ TmpInst.addOperand(MCOperand::createImm(
(Opcode == PPC::DCBTx || Opcode == PPC::DCBTSTx) ? 0 : 16));
TmpInst.addOperand(Inst.getOperand(0));
TmpInst.addOperand(Inst.getOperand(1));
@@ -912,9 +912,9 @@ void PPCAsmParser::ProcessInstruction(MC
TmpInst.setOpcode(Opcode == PPC::EXTLWI? PPC::RLWINM : PPC::RLWINMo);
TmpInst.addOperand(Inst.getOperand(0));
TmpInst.addOperand(Inst.getOperand(1));
- TmpInst.addOperand(MCOperand::CreateImm(B));
- TmpInst.addOperand(MCOperand::CreateImm(0));
- TmpInst.addOperand(MCOperand::CreateImm(N - 1));
+ TmpInst.addOperand(MCOperand::createImm(B));
+ TmpInst.addOperand(MCOperand::createImm(0));
+ TmpInst.addOperand(MCOperand::createImm(N - 1));
Inst = TmpInst;
break;
}
@@ -926,9 +926,9 @@ void PPCAsmParser::ProcessInstruction(MC
TmpInst.setOpcode(Opcode == PPC::EXTRWI? PPC::RLWINM : PPC::RLWINMo);
TmpInst.addOperand(Inst.getOperand(0));
TmpInst.addOperand(Inst.getOperand(1));
- TmpInst.addOperand(MCOperand::CreateImm(B + N));
- TmpInst.addOperand(MCOperand::CreateImm(32 - N));
- TmpInst.addOperand(MCOperand::CreateImm(31));
+ TmpInst.addOperand(MCOperand::createImm(B + N));
+ TmpInst.addOperand(MCOperand::createImm(32 - N));
+ TmpInst.addOperand(MCOperand::createImm(31));
Inst = TmpInst;
break;
}
@@ -941,9 +941,9 @@ void PPCAsmParser::ProcessInstruction(MC
TmpInst.addOperand(Inst.getOperand(0));
TmpInst.addOperand(Inst.getOperand(0));
TmpInst.addOperand(Inst.getOperand(1));
- TmpInst.addOperand(MCOperand::CreateImm(32 - B));
- TmpInst.addOperand(MCOperand::CreateImm(B));
- TmpInst.addOperand(MCOperand::CreateImm((B + N) - 1));
+ TmpInst.addOperand(MCOperand::createImm(32 - B));
+ TmpInst.addOperand(MCOperand::createImm(B));
+ TmpInst.addOperand(MCOperand::createImm((B + N) - 1));
Inst = TmpInst;
break;
}
@@ -956,9 +956,9 @@ void PPCAsmParser::ProcessInstruction(MC
TmpInst.addOperand(Inst.getOperand(0));
TmpInst.addOperand(Inst.getOperand(0));
TmpInst.addOperand(Inst.getOperand(1));
- TmpInst.addOperand(MCOperand::CreateImm(32 - (B + N)));
- TmpInst.addOperand(MCOperand::CreateImm(B));
- TmpInst.addOperand(MCOperand::CreateImm((B + N) - 1));
+ TmpInst.addOperand(MCOperand::createImm(32 - (B + N)));
+ TmpInst.addOperand(MCOperand::createImm(B));
+ TmpInst.addOperand(MCOperand::createImm((B + N) - 1));
Inst = TmpInst;
break;
}
@@ -969,9 +969,9 @@ void PPCAsmParser::ProcessInstruction(MC
TmpInst.setOpcode(Opcode == PPC::ROTRWI? PPC::RLWINM : PPC::RLWINMo);
TmpInst.addOperand(Inst.getOperand(0));
TmpInst.addOperand(Inst.getOperand(1));
- TmpInst.addOperand(MCOperand::CreateImm(32 - N));
- TmpInst.addOperand(MCOperand::CreateImm(0));
- TmpInst.addOperand(MCOperand::CreateImm(31));
+ TmpInst.addOperand(MCOperand::createImm(32 - N));
+ TmpInst.addOperand(MCOperand::createImm(0));
+ TmpInst.addOperand(MCOperand::createImm(31));
Inst = TmpInst;
break;
}
@@ -982,9 +982,9 @@ void PPCAsmParser::ProcessInstruction(MC
TmpInst.setOpcode(Opcode == PPC::SLWI? PPC::RLWINM : PPC::RLWINMo);
TmpInst.addOperand(Inst.getOperand(0));
TmpInst.addOperand(Inst.getOperand(1));
- TmpInst.addOperand(MCOperand::CreateImm(N));
- TmpInst.addOperand(MCOperand::CreateImm(0));
- TmpInst.addOperand(MCOperand::CreateImm(31 - N));
+ TmpInst.addOperand(MCOperand::createImm(N));
+ TmpInst.addOperand(MCOperand::createImm(0));
+ TmpInst.addOperand(MCOperand::createImm(31 - N));
Inst = TmpInst;
break;
}
@@ -995,9 +995,9 @@ void PPCAsmParser::ProcessInstruction(MC
TmpInst.setOpcode(Opcode == PPC::SRWI? PPC::RLWINM : PPC::RLWINMo);
TmpInst.addOperand(Inst.getOperand(0));
TmpInst.addOperand(Inst.getOperand(1));
- TmpInst.addOperand(MCOperand::CreateImm(32 - N));
- TmpInst.addOperand(MCOperand::CreateImm(N));
- TmpInst.addOperand(MCOperand::CreateImm(31));
+ TmpInst.addOperand(MCOperand::createImm(32 - N));
+ TmpInst.addOperand(MCOperand::createImm(N));
+ TmpInst.addOperand(MCOperand::createImm(31));
Inst = TmpInst;
break;
}
@@ -1008,9 +1008,9 @@ void PPCAsmParser::ProcessInstruction(MC
TmpInst.setOpcode(Opcode == PPC::CLRRWI? PPC::RLWINM : PPC::RLWINMo);
TmpInst.addOperand(Inst.getOperand(0));
TmpInst.addOperand(Inst.getOperand(1));
- TmpInst.addOperand(MCOperand::CreateImm(0));
- TmpInst.addOperand(MCOperand::CreateImm(0));
- TmpInst.addOperand(MCOperand::CreateImm(31 - N));
+ TmpInst.addOperand(MCOperand::createImm(0));
+ TmpInst.addOperand(MCOperand::createImm(0));
+ TmpInst.addOperand(MCOperand::createImm(31 - N));
Inst = TmpInst;
break;
}
@@ -1022,9 +1022,9 @@ void PPCAsmParser::ProcessInstruction(MC
TmpInst.setOpcode(Opcode == PPC::CLRLSLWI? PPC::RLWINM : PPC::RLWINMo);
TmpInst.addOperand(Inst.getOperand(0));
TmpInst.addOperand(Inst.getOperand(1));
- TmpInst.addOperand(MCOperand::CreateImm(N));
- TmpInst.addOperand(MCOperand::CreateImm(B - N));
- TmpInst.addOperand(MCOperand::CreateImm(31 - N));
+ TmpInst.addOperand(MCOperand::createImm(N));
+ TmpInst.addOperand(MCOperand::createImm(B - N));
+ TmpInst.addOperand(MCOperand::createImm(31 - N));
Inst = TmpInst;
break;
}
@@ -1036,8 +1036,8 @@ void PPCAsmParser::ProcessInstruction(MC
TmpInst.setOpcode(Opcode == PPC::EXTLDI? PPC::RLDICR : PPC::RLDICRo);
TmpInst.addOperand(Inst.getOperand(0));
TmpInst.addOperand(Inst.getOperand(1));
- TmpInst.addOperand(MCOperand::CreateImm(B));
- TmpInst.addOperand(MCOperand::CreateImm(N - 1));
+ TmpInst.addOperand(MCOperand::createImm(B));
+ TmpInst.addOperand(MCOperand::createImm(N - 1));
Inst = TmpInst;
break;
}
@@ -1049,8 +1049,8 @@ void PPCAsmParser::ProcessInstruction(MC
TmpInst.setOpcode(Opcode == PPC::EXTRDI? PPC::RLDICL : PPC::RLDICLo);
TmpInst.addOperand(Inst.getOperand(0));
TmpInst.addOperand(Inst.getOperand(1));
- TmpInst.addOperand(MCOperand::CreateImm(B + N));
- TmpInst.addOperand(MCOperand::CreateImm(64 - N));
+ TmpInst.addOperand(MCOperand::createImm(B + N));
+ TmpInst.addOperand(MCOperand::createImm(64 - N));
Inst = TmpInst;
break;
}
@@ -1063,8 +1063,8 @@ void PPCAsmParser::ProcessInstruction(MC
TmpInst.addOperand(Inst.getOperand(0));
TmpInst.addOperand(Inst.getOperand(0));
TmpInst.addOperand(Inst.getOperand(1));
- TmpInst.addOperand(MCOperand::CreateImm(64 - (B + N)));
- TmpInst.addOperand(MCOperand::CreateImm(B));
+ TmpInst.addOperand(MCOperand::createImm(64 - (B + N)));
+ TmpInst.addOperand(MCOperand::createImm(B));
Inst = TmpInst;
break;
}
@@ -1075,8 +1075,8 @@ void PPCAsmParser::ProcessInstruction(MC
TmpInst.setOpcode(Opcode == PPC::ROTRDI? PPC::RLDICL : PPC::RLDICLo);
TmpInst.addOperand(Inst.getOperand(0));
TmpInst.addOperand(Inst.getOperand(1));
- TmpInst.addOperand(MCOperand::CreateImm(64 - N));
- TmpInst.addOperand(MCOperand::CreateImm(0));
+ TmpInst.addOperand(MCOperand::createImm(64 - N));
+ TmpInst.addOperand(MCOperand::createImm(0));
Inst = TmpInst;
break;
}
@@ -1087,8 +1087,8 @@ void PPCAsmParser::ProcessInstruction(MC
TmpInst.setOpcode(Opcode == PPC::SLDI? PPC::RLDICR : PPC::RLDICRo);
TmpInst.addOperand(Inst.getOperand(0));
TmpInst.addOperand(Inst.getOperand(1));
- TmpInst.addOperand(MCOperand::CreateImm(N));
- TmpInst.addOperand(MCOperand::CreateImm(63 - N));
+ TmpInst.addOperand(MCOperand::createImm(N));
+ TmpInst.addOperand(MCOperand::createImm(63 - N));
Inst = TmpInst;
break;
}
@@ -1099,8 +1099,8 @@ void PPCAsmParser::ProcessInstruction(MC
TmpInst.setOpcode(Opcode == PPC::SRDI? PPC::RLDICL : PPC::RLDICLo);
TmpInst.addOperand(Inst.getOperand(0));
TmpInst.addOperand(Inst.getOperand(1));
- TmpInst.addOperand(MCOperand::CreateImm(64 - N));
- TmpInst.addOperand(MCOperand::CreateImm(N));
+ TmpInst.addOperand(MCOperand::createImm(64 - N));
+ TmpInst.addOperand(MCOperand::createImm(N));
Inst = TmpInst;
break;
}
@@ -1111,8 +1111,8 @@ void PPCAsmParser::ProcessInstruction(MC
TmpInst.setOpcode(Opcode == PPC::CLRRDI? PPC::RLDICR : PPC::RLDICRo);
TmpInst.addOperand(Inst.getOperand(0));
TmpInst.addOperand(Inst.getOperand(1));
- TmpInst.addOperand(MCOperand::CreateImm(0));
- TmpInst.addOperand(MCOperand::CreateImm(63 - N));
+ TmpInst.addOperand(MCOperand::createImm(0));
+ TmpInst.addOperand(MCOperand::createImm(63 - N));
Inst = TmpInst;
break;
}
@@ -1124,8 +1124,8 @@ void PPCAsmParser::ProcessInstruction(MC
TmpInst.setOpcode(Opcode == PPC::CLRLSLDI? PPC::RLDIC : PPC::RLDICo);
TmpInst.addOperand(Inst.getOperand(0));
TmpInst.addOperand(Inst.getOperand(1));
- TmpInst.addOperand(MCOperand::CreateImm(N));
- TmpInst.addOperand(MCOperand::CreateImm(B - N));
+ TmpInst.addOperand(MCOperand::createImm(N));
+ TmpInst.addOperand(MCOperand::createImm(B - N));
Inst = TmpInst;
break;
}
@@ -1141,8 +1141,8 @@ void PPCAsmParser::ProcessInstruction(MC
TmpInst.addOperand(Inst.getOperand(0));
TmpInst.addOperand(Inst.getOperand(1));
TmpInst.addOperand(Inst.getOperand(2));
- TmpInst.addOperand(MCOperand::CreateImm(MB));
- TmpInst.addOperand(MCOperand::CreateImm(ME));
+ TmpInst.addOperand(MCOperand::createImm(MB));
+ TmpInst.addOperand(MCOperand::createImm(ME));
Inst = TmpInst;
break;
}
@@ -1159,8 +1159,8 @@ void PPCAsmParser::ProcessInstruction(MC
TmpInst.addOperand(Inst.getOperand(0)); // The tied operand.
TmpInst.addOperand(Inst.getOperand(1));
TmpInst.addOperand(Inst.getOperand(2));
- TmpInst.addOperand(MCOperand::CreateImm(MB));
- TmpInst.addOperand(MCOperand::CreateImm(ME));
+ TmpInst.addOperand(MCOperand::createImm(MB));
+ TmpInst.addOperand(MCOperand::createImm(ME));
Inst = TmpInst;
break;
}
@@ -1176,8 +1176,8 @@ void PPCAsmParser::ProcessInstruction(MC
TmpInst.addOperand(Inst.getOperand(0));
TmpInst.addOperand(Inst.getOperand(1));
TmpInst.addOperand(Inst.getOperand(2));
- TmpInst.addOperand(MCOperand::CreateImm(MB));
- TmpInst.addOperand(MCOperand::CreateImm(ME));
+ TmpInst.addOperand(MCOperand::createImm(MB));
+ TmpInst.addOperand(MCOperand::createImm(ME));
Inst = TmpInst;
break;
}
Modified: llvm/trunk/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp?rev=237275&r1=237274&r2=237275&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp Wed May 13 13:37:00 2015
@@ -199,7 +199,7 @@ template <std::size_t N>
static DecodeStatus decodeRegisterClass(MCInst &Inst, uint64_t RegNo,
const unsigned (&Regs)[N]) {
assert(RegNo < N && "Invalid register number");
- Inst.addOperand(MCOperand::CreateReg(Regs[RegNo]));
+ Inst.addOperand(MCOperand::createReg(Regs[RegNo]));
return MCDisassembler::Success;
}
@@ -291,7 +291,7 @@ template<unsigned N>
static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm,
int64_t Address, const void *Decoder) {
assert(isUInt<N>(Imm) && "Invalid immediate");
- Inst.addOperand(MCOperand::CreateImm(Imm));
+ Inst.addOperand(MCOperand::createImm(Imm));
return MCDisassembler::Success;
}
@@ -299,7 +299,7 @@ template<unsigned N>
static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm,
int64_t Address, const void *Decoder) {
assert(isUInt<N>(Imm) && "Invalid immediate");
- Inst.addOperand(MCOperand::CreateImm(SignExtend64<N>(Imm)));
+ Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm)));
return MCDisassembler::Success;
}
@@ -322,19 +322,19 @@ static DecodeStatus decodeMemRIOperands(
case PPC::LFSU:
case PPC::LFDU:
// Add the tied output operand.
- Inst.addOperand(MCOperand::CreateReg(GP0Regs[Base]));
+ Inst.addOperand(MCOperand::createReg(GP0Regs[Base]));
break;
case PPC::STBU:
case PPC::STHU:
case PPC::STWU:
case PPC::STFSU:
case PPC::STFDU:
- Inst.insert(Inst.begin(), MCOperand::CreateReg(GP0Regs[Base]));
+ Inst.insert(Inst.begin(), MCOperand::createReg(GP0Regs[Base]));
break;
}
- Inst.addOperand(MCOperand::CreateImm(SignExtend64<16>(Disp)));
- Inst.addOperand(MCOperand::CreateReg(GP0Regs[Base]));
+ Inst.addOperand(MCOperand::createImm(SignExtend64<16>(Disp)));
+ Inst.addOperand(MCOperand::createReg(GP0Regs[Base]));
return MCDisassembler::Success;
}
@@ -350,12 +350,12 @@ static DecodeStatus decodeMemRIXOperands
if (Inst.getOpcode() == PPC::LDU)
// Add the tied output operand.
- Inst.addOperand(MCOperand::CreateReg(GP0Regs[Base]));
+ Inst.addOperand(MCOperand::createReg(GP0Regs[Base]));
else if (Inst.getOpcode() == PPC::STDU)
- Inst.insert(Inst.begin(), MCOperand::CreateReg(GP0Regs[Base]));
+ Inst.insert(Inst.begin(), MCOperand::createReg(GP0Regs[Base]));
- Inst.addOperand(MCOperand::CreateImm(SignExtend64<16>(Disp << 2)));
- Inst.addOperand(MCOperand::CreateReg(GP0Regs[Base]));
+ Inst.addOperand(MCOperand::createImm(SignExtend64<16>(Disp << 2)));
+ Inst.addOperand(MCOperand::createReg(GP0Regs[Base]));
return MCDisassembler::Success;
}
@@ -366,7 +366,7 @@ static DecodeStatus decodeCRBitMOperand(
unsigned Zeros = countTrailingZeros(Imm);
assert(Zeros < 8 && "Invalid CR bit value");
- Inst.addOperand(MCOperand::CreateReg(CRRegs[7 - Zeros]));
+ Inst.addOperand(MCOperand::createReg(CRRegs[7 - Zeros]));
return MCDisassembler::Success;
}
Modified: llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cpp?rev=237275&r1=237274&r2=237275&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cpp Wed May 13 13:37:00 2015
@@ -512,7 +512,7 @@ void PPCAsmPrinter::EmitInstruction(cons
// Step 1: lwz %Rt, .L$poff - .L$pb(%Ri)
TmpInst.getOperand(1) =
- MCOperand::CreateExpr(MCBinaryExpr::CreateSub(Exp, PB, OutContext));
+ MCOperand::createExpr(MCBinaryExpr::CreateSub(Exp, PB, OutContext));
TmpInst.getOperand(0) = TR;
TmpInst.getOperand(2) = PICR;
EmitToStreamer(*OutStreamer, TmpInst);
@@ -549,7 +549,7 @@ void PPCAsmPrinter::EmitInstruction(cons
const MCExpr *Exp =
MCSymbolRefExpr::Create(MOSymbol, MCSymbolRefExpr::VK_GOT,
OutContext);
- TmpInst.getOperand(1) = MCOperand::CreateExpr(Exp);
+ TmpInst.getOperand(1) = MCOperand::createExpr(Exp);
} else {
MCSymbol *TOCEntry = lookUpOrCreateTOCEntry(MOSymbol);
@@ -560,7 +560,7 @@ void PPCAsmPrinter::EmitInstruction(cons
MCSymbolRefExpr::Create(OutContext.GetOrCreateSymbol(Twine(".LTOC")),
OutContext);
Exp = MCBinaryExpr::CreateSub(Exp, PB, OutContext);
- TmpInst.getOperand(1) = MCOperand::CreateExpr(Exp);
+ TmpInst.getOperand(1) = MCOperand::createExpr(Exp);
}
EmitToStreamer(*OutStreamer, TmpInst);
return;
@@ -594,7 +594,7 @@ void PPCAsmPrinter::EmitInstruction(cons
const MCExpr *Exp =
MCSymbolRefExpr::Create(TOCEntry, MCSymbolRefExpr::VK_PPC_TOC,
OutContext);
- TmpInst.getOperand(1) = MCOperand::CreateExpr(Exp);
+ TmpInst.getOperand(1) = MCOperand::createExpr(Exp);
EmitToStreamer(*OutStreamer, TmpInst);
return;
}
@@ -641,7 +641,7 @@ void PPCAsmPrinter::EmitInstruction(cons
const MCExpr *Exp =
MCSymbolRefExpr::Create(MOSymbol, MCSymbolRefExpr::VK_PPC_TOC_HA,
OutContext);
- TmpInst.getOperand(2) = MCOperand::CreateExpr(Exp);
+ TmpInst.getOperand(2) = MCOperand::createExpr(Exp);
EmitToStreamer(*OutStreamer, TmpInst);
return;
}
@@ -683,7 +683,7 @@ void PPCAsmPrinter::EmitInstruction(cons
const MCExpr *Exp =
MCSymbolRefExpr::Create(MOSymbol, MCSymbolRefExpr::VK_PPC_TOC_LO,
OutContext);
- TmpInst.getOperand(1) = MCOperand::CreateExpr(Exp);
+ TmpInst.getOperand(1) = MCOperand::createExpr(Exp);
EmitToStreamer(*OutStreamer, TmpInst);
return;
}
@@ -717,7 +717,7 @@ void PPCAsmPrinter::EmitInstruction(cons
const MCExpr *Exp =
MCSymbolRefExpr::Create(MOSymbol, MCSymbolRefExpr::VK_PPC_TOC_LO,
OutContext);
- TmpInst.getOperand(2) = MCOperand::CreateExpr(Exp);
+ TmpInst.getOperand(2) = MCOperand::createExpr(Exp);
EmitToStreamer(*OutStreamer, TmpInst);
return;
}
@@ -750,7 +750,7 @@ void PPCAsmPrinter::EmitInstruction(cons
const MCExpr *Exp =
MCSymbolRefExpr::Create(MOSymbol, MCSymbolRefExpr::VK_PPC_GOT_TPREL_LO,
OutContext);
- TmpInst.getOperand(1) = MCOperand::CreateExpr(Exp);
+ TmpInst.getOperand(1) = MCOperand::createExpr(Exp);
EmitToStreamer(*OutStreamer, TmpInst);
return;
}
Modified: llvm/trunk/lib/Target/PowerPC/PPCMCInstLower.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCMCInstLower.cpp?rev=237275&r1=237274&r2=237275&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCMCInstLower.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCMCInstLower.cpp Wed May 13 13:37:00 2015
@@ -167,7 +167,7 @@ static MCOperand GetSymbolRef(const Mach
break;
}
- return MCOperand::CreateExpr(Expr);
+ return MCOperand::createExpr(Expr);
}
void llvm::LowerPPCMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI,
@@ -187,13 +187,13 @@ void llvm::LowerPPCMachineInstrToMCInst(
assert(MO.getReg() > PPC::NoRegister &&
MO.getReg() < PPC::NUM_TARGET_REGS &&
"Invalid register for this target!");
- MCOp = MCOperand::CreateReg(MO.getReg());
+ MCOp = MCOperand::createReg(MO.getReg());
break;
case MachineOperand::MO_Immediate:
- MCOp = MCOperand::CreateImm(MO.getImm());
+ MCOp = MCOperand::createImm(MO.getImm());
break;
case MachineOperand::MO_MachineBasicBlock:
- MCOp = MCOperand::CreateExpr(MCSymbolRefExpr::Create(
+ MCOp = MCOperand::createExpr(MCSymbolRefExpr::Create(
MO.getMBB()->getSymbol(), AP.OutContext));
break;
case MachineOperand::MO_GlobalAddress:
Modified: llvm/trunk/lib/Target/R600/AMDGPUMCInstLower.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/AMDGPUMCInstLower.cpp?rev=237275&r1=237274&r2=237275&view=diff
==============================================================================
--- llvm/trunk/lib/Target/R600/AMDGPUMCInstLower.cpp (original)
+++ llvm/trunk/lib/Target/R600/AMDGPUMCInstLower.cpp Wed May 13 13:37:00 2015
@@ -58,32 +58,32 @@ void AMDGPUMCInstLower::lower(const Mach
default:
llvm_unreachable("unknown operand type");
case MachineOperand::MO_Immediate:
- MCOp = MCOperand::CreateImm(MO.getImm());
+ MCOp = MCOperand::createImm(MO.getImm());
break;
case MachineOperand::MO_Register:
- MCOp = MCOperand::CreateReg(MO.getReg());
+ MCOp = MCOperand::createReg(MO.getReg());
break;
case MachineOperand::MO_MachineBasicBlock:
- MCOp = MCOperand::CreateExpr(MCSymbolRefExpr::Create(
+ MCOp = MCOperand::createExpr(MCSymbolRefExpr::Create(
MO.getMBB()->getSymbol(), Ctx));
break;
case MachineOperand::MO_GlobalAddress: {
const GlobalValue *GV = MO.getGlobal();
MCSymbol *Sym = Ctx.GetOrCreateSymbol(StringRef(GV->getName()));
- MCOp = MCOperand::CreateExpr(MCSymbolRefExpr::Create(Sym, Ctx));
+ MCOp = MCOperand::createExpr(MCSymbolRefExpr::Create(Sym, Ctx));
break;
}
case MachineOperand::MO_TargetIndex: {
assert(MO.getIndex() == AMDGPU::TI_CONSTDATA_START);
MCSymbol *Sym = Ctx.GetOrCreateSymbol(StringRef(END_OF_TEXT_LABEL_NAME));
const MCSymbolRefExpr *Expr = MCSymbolRefExpr::Create(Sym, Ctx);
- MCOp = MCOperand::CreateExpr(Expr);
+ MCOp = MCOperand::createExpr(Expr);
break;
}
case MachineOperand::MO_ExternalSymbol: {
MCSymbol *Sym = Ctx.GetOrCreateSymbol(StringRef(MO.getSymbolName()));
const MCSymbolRefExpr *Expr = MCSymbolRefExpr::Create(Sym, Ctx);
- MCOp = MCOperand::CreateExpr(Expr);
+ MCOp = MCOperand::createExpr(Expr);
break;
}
}
Modified: llvm/trunk/lib/Target/R600/AsmParser/AMDGPUAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/AsmParser/AMDGPUAsmParser.cpp?rev=237275&r1=237274&r2=237275&view=diff
==============================================================================
--- llvm/trunk/lib/Target/R600/AsmParser/AMDGPUAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/R600/AsmParser/AMDGPUAsmParser.cpp Wed May 13 13:37:00 2015
@@ -91,7 +91,7 @@ public:
};
void addImmOperands(MCInst &Inst, unsigned N) const {
- Inst.addOperand(MCOperand::CreateImm(getImm()));
+ Inst.addOperand(MCOperand::createImm(getImm()));
}
StringRef getToken() const {
@@ -99,7 +99,7 @@ public:
}
void addRegOperands(MCInst &Inst, unsigned N) const {
- Inst.addOperand(MCOperand::CreateReg(getReg()));
+ Inst.addOperand(MCOperand::createReg(getReg()));
}
void addRegOrImmOperands(MCInst &Inst, unsigned N) const {
@@ -110,7 +110,7 @@ public:
}
void addRegWithInputModsOperands(MCInst &Inst, unsigned N) const {
- Inst.addOperand(MCOperand::CreateImm(
+ Inst.addOperand(MCOperand::createImm(
Reg.Modifiers == -1 ? 0 : Reg.Modifiers));
addRegOperands(Inst, N);
}
@@ -120,7 +120,7 @@ public:
addImmOperands(Inst, N);
else {
assert(isExpr());
- Inst.addOperand(MCOperand::CreateExpr(Expr));
+ Inst.addOperand(MCOperand::createExpr(Expr));
}
}
@@ -948,7 +948,7 @@ void AMDGPUAsmParser::cvtDSOffset01(MCIn
((AMDGPUOperand &)*Operands[Offset0Idx]).addImmOperands(Inst, 1); // offset0
((AMDGPUOperand &)*Operands[Offset1Idx]).addImmOperands(Inst, 1); // offset1
((AMDGPUOperand &)*Operands[GDSIdx]).addImmOperands(Inst, 1); // gds
- Inst.addOperand(MCOperand::CreateReg(AMDGPU::M0)); // m0
+ Inst.addOperand(MCOperand::createReg(AMDGPU::M0)); // m0
}
void AMDGPUAsmParser::cvtDS(MCInst &Inst, const OperandVector &Operands) {
@@ -981,7 +981,7 @@ void AMDGPUAsmParser::cvtDS(MCInst &Inst
unsigned GDSIdx = OptionalIdx[AMDGPUOperand::ImmTyGDS];
((AMDGPUOperand &)*Operands[GDSIdx]).addImmOperands(Inst, 1); // gds
}
- Inst.addOperand(MCOperand::CreateReg(AMDGPU::M0)); // m0
+ Inst.addOperand(MCOperand::createReg(AMDGPU::M0)); // m0
}
Modified: llvm/trunk/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp?rev=237275&r1=237274&r2=237275&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp Wed May 13 13:37:00 2015
@@ -250,7 +250,7 @@ public:
void addRegOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateReg(getReg()));
+ Inst.addOperand(MCOperand::createReg(getReg()));
}
void addImmOperands(MCInst &Inst, unsigned N) const {
@@ -262,26 +262,26 @@ public:
void addExpr(MCInst &Inst, const MCExpr *Expr) const{
// Add as immediate when possible. Null MCExpr = 0.
if (!Expr)
- Inst.addOperand(MCOperand::CreateImm(0));
+ Inst.addOperand(MCOperand::createImm(0));
else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
- Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
+ Inst.addOperand(MCOperand::createImm(CE->getValue()));
else
- Inst.addOperand(MCOperand::CreateExpr(Expr));
+ Inst.addOperand(MCOperand::createExpr(Expr));
}
void addMEMrrOperands(MCInst &Inst, unsigned N) const {
assert(N == 2 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateReg(getMemBase()));
+ Inst.addOperand(MCOperand::createReg(getMemBase()));
assert(getMemOffsetReg() != 0 && "Invalid offset");
- Inst.addOperand(MCOperand::CreateReg(getMemOffsetReg()));
+ Inst.addOperand(MCOperand::createReg(getMemOffsetReg()));
}
void addMEMriOperands(MCInst &Inst, unsigned N) const {
assert(N == 2 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateReg(getMemBase()));
+ Inst.addOperand(MCOperand::createReg(getMemBase()));
const MCExpr *Expr = getMemOff();
addExpr(Inst, Expr);
Modified: llvm/trunk/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp?rev=237275&r1=237274&r2=237275&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp (original)
+++ llvm/trunk/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp Wed May 13 13:37:00 2015
@@ -113,7 +113,7 @@ static DecodeStatus DecodeIntRegsRegiste
if (RegNo > 31)
return MCDisassembler::Fail;
unsigned Reg = IntRegDecoderTable[RegNo];
- Inst.addOperand(MCOperand::CreateReg(Reg));
+ Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success;
}
@@ -124,7 +124,7 @@ static DecodeStatus DecodeI64RegsRegiste
if (RegNo > 31)
return MCDisassembler::Fail;
unsigned Reg = IntRegDecoderTable[RegNo];
- Inst.addOperand(MCOperand::CreateReg(Reg));
+ Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success;
}
@@ -136,7 +136,7 @@ static DecodeStatus DecodeFPRegsRegister
if (RegNo > 31)
return MCDisassembler::Fail;
unsigned Reg = FPRegDecoderTable[RegNo];
- Inst.addOperand(MCOperand::CreateReg(Reg));
+ Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success;
}
@@ -148,7 +148,7 @@ static DecodeStatus DecodeDFPRegsRegiste
if (RegNo > 31)
return MCDisassembler::Fail;
unsigned Reg = DFPRegDecoderTable[RegNo];
- Inst.addOperand(MCOperand::CreateReg(Reg));
+ Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success;
}
@@ -163,7 +163,7 @@ static DecodeStatus DecodeQFPRegsRegiste
unsigned Reg = QFPRegDecoderTable[RegNo];
if (Reg == ~0U)
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateReg(Reg));
+ Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success;
}
@@ -172,7 +172,7 @@ static DecodeStatus DecodeFCCRegsRegiste
const void *Decoder) {
if (RegNo > 3)
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateReg(FCCRegDecoderTable[RegNo]));
+ Inst.addOperand(MCOperand::createReg(FCCRegDecoderTable[RegNo]));
return MCDisassembler::Success;
}
@@ -280,7 +280,7 @@ static DecodeStatus DecodeMem(MCInst &MI
// Decode imm|rs2.
if (isImm)
- MI.addOperand(MCOperand::CreateImm(simm13));
+ MI.addOperand(MCOperand::createImm(simm13));
else {
status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder);
if (status != MCDisassembler::Success)
@@ -358,14 +358,14 @@ static DecodeStatus DecodeCall(MCInst &M
tgt <<= 2;
if (!tryAddingSymbolicOperand(tgt+Address, false, Address,
0, 30, MI, Decoder))
- MI.addOperand(MCOperand::CreateImm(tgt));
+ MI.addOperand(MCOperand::createImm(tgt));
return MCDisassembler::Success;
}
static DecodeStatus DecodeSIMM13(MCInst &MI, unsigned insn,
uint64_t Address, const void *Decoder) {
unsigned tgt = SignExtend32<13>(fieldFromInstruction(insn, 0, 13));
- MI.addOperand(MCOperand::CreateImm(tgt));
+ MI.addOperand(MCOperand::createImm(tgt));
return MCDisassembler::Success;
}
@@ -394,7 +394,7 @@ static DecodeStatus DecodeJMPL(MCInst &M
// Decode RS1 | SIMM13.
if (isImm)
- MI.addOperand(MCOperand::CreateImm(simm13));
+ MI.addOperand(MCOperand::createImm(simm13));
else {
status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder);
if (status != MCDisassembler::Success)
@@ -422,7 +422,7 @@ static DecodeStatus DecodeReturn(MCInst
// Decode RS2 | SIMM13.
if (isImm)
- MI.addOperand(MCOperand::CreateImm(simm13));
+ MI.addOperand(MCOperand::createImm(simm13));
else {
status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder);
if (status != MCDisassembler::Success)
@@ -456,7 +456,7 @@ static DecodeStatus DecodeSWAP(MCInst &M
// Decode RS1 | SIMM13.
if (isImm)
- MI.addOperand(MCOperand::CreateImm(simm13));
+ MI.addOperand(MCOperand::createImm(simm13));
else {
status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder);
if (status != MCDisassembler::Success)
Modified: llvm/trunk/lib/Target/Sparc/SparcAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcAsmPrinter.cpp?rev=237275&r1=237274&r2=237275&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/SparcAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/Sparc/SparcAsmPrinter.cpp Wed May 13 13:37:00 2015
@@ -81,7 +81,7 @@ static MCOperand createSparcMCOperand(Sp
const MCSymbolRefExpr *MCSym = MCSymbolRefExpr::Create(Sym,
OutContext);
const SparcMCExpr *expr = SparcMCExpr::Create(Kind, MCSym, OutContext);
- return MCOperand::CreateExpr(expr);
+ return MCOperand::createExpr(expr);
}
static MCOperand createPCXCallOP(MCSymbol *Label,
@@ -104,7 +104,7 @@ static MCOperand createPCXRelExprOp(Spar
const MCBinaryExpr *Add = MCBinaryExpr::CreateAdd(GOT, Sub, OutContext);
const SparcMCExpr *expr = SparcMCExpr::Create(Kind,
Add, OutContext);
- return MCOperand::CreateExpr(expr);
+ return MCOperand::createExpr(expr);
}
static void EmitCall(MCStreamer &OutStreamer,
@@ -182,7 +182,7 @@ void SparcAsmPrinter::LowerGETPCXAndEmit
assert(MO.getReg() != SP::O7 &&
"%o7 is assigned as destination for getpcx!");
- MCOperand MCRegOP = MCOperand::CreateReg(MO.getReg());
+ MCOperand MCRegOP = MCOperand::createReg(MO.getReg());
if (TM.getRelocationModel() != Reloc::PIC_) {
@@ -199,7 +199,7 @@ void SparcAsmPrinter::LowerGETPCXAndEmit
EmitHiLo(*OutStreamer, GOTLabel,
SparcMCExpr::VK_Sparc_H44, SparcMCExpr::VK_Sparc_M44,
MCRegOP, OutContext, STI);
- MCOperand imm = MCOperand::CreateExpr(MCConstantExpr::Create(12,
+ MCOperand imm = MCOperand::createExpr(MCConstantExpr::Create(12,
OutContext));
EmitSHL(*OutStreamer, MCRegOP, imm, MCRegOP, STI);
MCOperand lo = createSparcMCOperand(SparcMCExpr::VK_Sparc_L44,
@@ -211,11 +211,11 @@ void SparcAsmPrinter::LowerGETPCXAndEmit
EmitHiLo(*OutStreamer, GOTLabel,
SparcMCExpr::VK_Sparc_HH, SparcMCExpr::VK_Sparc_HM,
MCRegOP, OutContext, STI);
- MCOperand imm = MCOperand::CreateExpr(MCConstantExpr::Create(32,
+ MCOperand imm = MCOperand::createExpr(MCConstantExpr::Create(32,
OutContext));
EmitSHL(*OutStreamer, MCRegOP, imm, MCRegOP, STI);
// Use register %o7 to load the lower 32 bits.
- MCOperand RegO7 = MCOperand::CreateReg(SP::O7);
+ MCOperand RegO7 = MCOperand::createReg(SP::O7);
EmitHiLo(*OutStreamer, GOTLabel,
SparcMCExpr::VK_Sparc_HI, SparcMCExpr::VK_Sparc_LO,
RegO7, OutContext, STI);
@@ -229,7 +229,7 @@ void SparcAsmPrinter::LowerGETPCXAndEmit
MCSymbol *EndLabel = OutContext.CreateTempSymbol();
MCSymbol *SethiLabel = OutContext.CreateTempSymbol();
- MCOperand RegO7 = MCOperand::CreateReg(SP::O7);
+ MCOperand RegO7 = MCOperand::createReg(SP::O7);
// <StartLabel>:
// call <EndLabel>
Modified: llvm/trunk/lib/Target/Sparc/SparcMCInstLower.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcMCInstLower.cpp?rev=237275&r1=237274&r2=237275&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/SparcMCInstLower.cpp (original)
+++ llvm/trunk/lib/Target/Sparc/SparcMCInstLower.cpp Wed May 13 13:37:00 2015
@@ -63,7 +63,7 @@ static MCOperand LowerSymbolOperand(cons
AP.OutContext);
const SparcMCExpr *expr = SparcMCExpr::Create(Kind, MCSym,
AP.OutContext);
- return MCOperand::CreateExpr(expr);
+ return MCOperand::createExpr(expr);
}
static MCOperand LowerOperand(const MachineInstr *MI,
@@ -74,10 +74,10 @@ static MCOperand LowerOperand(const Mach
case MachineOperand::MO_Register:
if (MO.isImplicit())
break;
- return MCOperand::CreateReg(MO.getReg());
+ return MCOperand::createReg(MO.getReg());
case MachineOperand::MO_Immediate:
- return MCOperand::CreateImm(MO.getImm());
+ return MCOperand::createImm(MO.getImm());
case MachineOperand::MO_MachineBasicBlock:
case MachineOperand::MO_GlobalAddress:
Modified: llvm/trunk/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp?rev=237275&r1=237274&r2=237275&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp Wed May 13 13:37:00 2015
@@ -120,11 +120,11 @@ private:
void addExpr(MCInst &Inst, const MCExpr *Expr) const {
// Add as immediates when possible. Null MCExpr = 0.
if (!Expr)
- Inst.addOperand(MCOperand::CreateImm(0));
+ Inst.addOperand(MCOperand::createImm(0));
else if (auto *CE = dyn_cast<MCConstantExpr>(Expr))
- Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
+ Inst.addOperand(MCOperand::createImm(CE->getValue()));
else
- Inst.addOperand(MCOperand::CreateExpr(Expr));
+ Inst.addOperand(MCOperand::createExpr(Expr));
}
public:
@@ -253,9 +253,9 @@ public:
void addBDVAddrOperands(MCInst &Inst, unsigned N) const {
assert(N == 3 && "Invalid number of operands");
assert(isMem(BDVMem) && "Invalid operand type");
- Inst.addOperand(MCOperand::CreateReg(Mem.Base));
+ Inst.addOperand(MCOperand::createReg(Mem.Base));
addExpr(Inst, Mem.Disp);
- Inst.addOperand(MCOperand::CreateReg(Mem.Index));
+ Inst.addOperand(MCOperand::createReg(Mem.Index));
}
// Override MCParsedAsmOperand.
@@ -267,12 +267,12 @@ public:
// to an instruction.
void addRegOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands");
- Inst.addOperand(MCOperand::CreateReg(getReg()));
+ Inst.addOperand(MCOperand::createReg(getReg()));
}
void addAccessRegOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands");
assert(Kind == KindAccessReg && "Invalid operand type");
- Inst.addOperand(MCOperand::CreateImm(AccessReg));
+ Inst.addOperand(MCOperand::createImm(AccessReg));
}
void addImmOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands");
@@ -281,20 +281,20 @@ public:
void addBDAddrOperands(MCInst &Inst, unsigned N) const {
assert(N == 2 && "Invalid number of operands");
assert(isMem(BDMem) && "Invalid operand type");
- Inst.addOperand(MCOperand::CreateReg(Mem.Base));
+ Inst.addOperand(MCOperand::createReg(Mem.Base));
addExpr(Inst, Mem.Disp);
}
void addBDXAddrOperands(MCInst &Inst, unsigned N) const {
assert(N == 3 && "Invalid number of operands");
assert(isMem(BDXMem) && "Invalid operand type");
- Inst.addOperand(MCOperand::CreateReg(Mem.Base));
+ Inst.addOperand(MCOperand::createReg(Mem.Base));
addExpr(Inst, Mem.Disp);
- Inst.addOperand(MCOperand::CreateReg(Mem.Index));
+ Inst.addOperand(MCOperand::createReg(Mem.Index));
}
void addBDLAddrOperands(MCInst &Inst, unsigned N) const {
assert(N == 3 && "Invalid number of operands");
assert(isMem(BDLMem) && "Invalid operand type");
- Inst.addOperand(MCOperand::CreateReg(Mem.Base));
+ Inst.addOperand(MCOperand::createReg(Mem.Base));
addExpr(Inst, Mem.Disp);
addExpr(Inst, Mem.Length);
}
Modified: llvm/trunk/lib/Target/SystemZ/Disassembler/SystemZDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/Disassembler/SystemZDisassembler.cpp?rev=237275&r1=237274&r2=237275&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/Disassembler/SystemZDisassembler.cpp (original)
+++ llvm/trunk/lib/Target/SystemZ/Disassembler/SystemZDisassembler.cpp Wed May 13 13:37:00 2015
@@ -52,7 +52,7 @@ static DecodeStatus decodeRegisterClass(
RegNo = Regs[RegNo];
if (RegNo == 0)
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateReg(RegNo));
+ Inst.addOperand(MCOperand::createReg(RegNo));
return MCDisassembler::Success;
}
@@ -126,7 +126,7 @@ template<unsigned N>
static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm) {
if (!isUInt<N>(Imm))
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateImm(Imm));
+ Inst.addOperand(MCOperand::createImm(Imm));
return MCDisassembler::Success;
}
@@ -134,7 +134,7 @@ template<unsigned N>
static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm) {
if (!isUInt<N>(Imm))
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateImm(SignExtend64<N>(Imm)));
+ Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm)));
return MCDisassembler::Success;
}
@@ -208,7 +208,7 @@ template<unsigned N>
static DecodeStatus decodePCDBLOperand(MCInst &Inst, uint64_t Imm,
uint64_t Address) {
assert(isUInt<N>(Imm) && "Invalid PC-relative offset");
- Inst.addOperand(MCOperand::CreateImm(SignExtend64<N>(Imm) * 2 + Address));
+ Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm) * 2 + Address));
return MCDisassembler::Success;
}
@@ -229,8 +229,8 @@ static DecodeStatus decodeBDAddr12Operan
uint64_t Base = Field >> 12;
uint64_t Disp = Field & 0xfff;
assert(Base < 16 && "Invalid BDAddr12");
- Inst.addOperand(MCOperand::CreateReg(Base == 0 ? 0 : Regs[Base]));
- Inst.addOperand(MCOperand::CreateImm(Disp));
+ Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base]));
+ Inst.addOperand(MCOperand::createImm(Disp));
return MCDisassembler::Success;
}
@@ -239,8 +239,8 @@ static DecodeStatus decodeBDAddr20Operan
uint64_t Base = Field >> 20;
uint64_t Disp = ((Field << 12) & 0xff000) | ((Field >> 8) & 0xfff);
assert(Base < 16 && "Invalid BDAddr20");
- Inst.addOperand(MCOperand::CreateReg(Base == 0 ? 0 : Regs[Base]));
- Inst.addOperand(MCOperand::CreateImm(SignExtend64<20>(Disp)));
+ Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base]));
+ Inst.addOperand(MCOperand::createImm(SignExtend64<20>(Disp)));
return MCDisassembler::Success;
}
@@ -250,9 +250,9 @@ static DecodeStatus decodeBDXAddr12Opera
uint64_t Base = (Field >> 12) & 0xf;
uint64_t Disp = Field & 0xfff;
assert(Index < 16 && "Invalid BDXAddr12");
- Inst.addOperand(MCOperand::CreateReg(Base == 0 ? 0 : Regs[Base]));
- Inst.addOperand(MCOperand::CreateImm(Disp));
- Inst.addOperand(MCOperand::CreateReg(Index == 0 ? 0 : Regs[Index]));
+ Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base]));
+ Inst.addOperand(MCOperand::createImm(Disp));
+ Inst.addOperand(MCOperand::createReg(Index == 0 ? 0 : Regs[Index]));
return MCDisassembler::Success;
}
@@ -262,9 +262,9 @@ static DecodeStatus decodeBDXAddr20Opera
uint64_t Base = (Field >> 20) & 0xf;
uint64_t Disp = ((Field & 0xfff00) >> 8) | ((Field & 0xff) << 12);
assert(Index < 16 && "Invalid BDXAddr20");
- Inst.addOperand(MCOperand::CreateReg(Base == 0 ? 0 : Regs[Base]));
- Inst.addOperand(MCOperand::CreateImm(SignExtend64<20>(Disp)));
- Inst.addOperand(MCOperand::CreateReg(Index == 0 ? 0 : Regs[Index]));
+ Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base]));
+ Inst.addOperand(MCOperand::createImm(SignExtend64<20>(Disp)));
+ Inst.addOperand(MCOperand::createReg(Index == 0 ? 0 : Regs[Index]));
return MCDisassembler::Success;
}
@@ -274,9 +274,9 @@ static DecodeStatus decodeBDLAddr12Len8O
uint64_t Base = (Field >> 12) & 0xf;
uint64_t Disp = Field & 0xfff;
assert(Length < 256 && "Invalid BDLAddr12Len8");
- Inst.addOperand(MCOperand::CreateReg(Base == 0 ? 0 : Regs[Base]));
- Inst.addOperand(MCOperand::CreateImm(Disp));
- Inst.addOperand(MCOperand::CreateImm(Length + 1));
+ Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base]));
+ Inst.addOperand(MCOperand::createImm(Disp));
+ Inst.addOperand(MCOperand::createImm(Length + 1));
return MCDisassembler::Success;
}
@@ -286,9 +286,9 @@ static DecodeStatus decodeBDVAddr12Opera
uint64_t Base = (Field >> 12) & 0xf;
uint64_t Disp = Field & 0xfff;
assert(Index < 32 && "Invalid BDVAddr12");
- Inst.addOperand(MCOperand::CreateReg(Base == 0 ? 0 : Regs[Base]));
- Inst.addOperand(MCOperand::CreateImm(Disp));
- Inst.addOperand(MCOperand::CreateReg(SystemZMC::VR128Regs[Index]));
+ Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base]));
+ Inst.addOperand(MCOperand::createImm(Disp));
+ Inst.addOperand(MCOperand::createReg(SystemZMC::VR128Regs[Index]));
return MCDisassembler::Success;
}
Modified: llvm/trunk/lib/Target/SystemZ/SystemZMCInstLower.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZMCInstLower.cpp?rev=237275&r1=237274&r2=237275&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZMCInstLower.cpp (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZMCInstLower.cpp Wed May 13 13:37:00 2015
@@ -79,14 +79,14 @@ SystemZMCInstLower::getExpr(const Machin
MCOperand SystemZMCInstLower::lowerOperand(const MachineOperand &MO) const {
switch (MO.getType()) {
case MachineOperand::MO_Register:
- return MCOperand::CreateReg(MO.getReg());
+ return MCOperand::createReg(MO.getReg());
case MachineOperand::MO_Immediate:
- return MCOperand::CreateImm(MO.getImm());
+ return MCOperand::createImm(MO.getImm());
default: {
MCSymbolRefExpr::VariantKind Kind = getVariantKind(MO.getTargetFlags());
- return MCOperand::CreateExpr(getExpr(MO, Kind));
+ return MCOperand::createExpr(getExpr(MO, Kind));
}
}
}
Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmInstrumentation.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmParser/X86AsmInstrumentation.cpp?rev=237275&r1=237274&r2=237275&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/AsmParser/X86AsmInstrumentation.cpp (original)
+++ llvm/trunk/lib/Target/X86/AsmParser/X86AsmInstrumentation.cpp Wed May 13 13:37:00 2015
@@ -245,7 +245,7 @@ protected:
assert(VT == MVT::i32 || VT == MVT::i64);
MCInst Inst;
Inst.setOpcode(VT == MVT::i32 ? X86::LEA32r : X86::LEA64r);
- Inst.addOperand(MCOperand::CreateReg(getX86SubSuperRegister(Reg, VT)));
+ Inst.addOperand(MCOperand::createReg(getX86SubSuperRegister(Reg, VT)));
Op.addMemOperands(Inst, 5);
EmitInstruction(Out, Inst);
}
@@ -642,7 +642,7 @@ void X86AddressSanitizer32::InstrumentMe
{
MCInst Inst;
Inst.setOpcode(X86::MOV8rm);
- Inst.addOperand(MCOperand::CreateReg(ShadowRegI8));
+ Inst.addOperand(MCOperand::createReg(ShadowRegI8));
const MCExpr *Disp = MCConstantExpr::Create(kShadowOffset, Ctx);
std::unique_ptr<X86Operand> Op(
X86Operand::CreateMem(getPointerWidth(), 0, Disp, ShadowRegI32, 0, 1,
@@ -725,7 +725,7 @@ void X86AddressSanitizer32::InstrumentMe
X86Operand::CreateMem(getPointerWidth(), 0, Disp, ShadowRegI32, 0, 1,
SMLoc(), SMLoc()));
Op->addMemOperands(Inst, 5);
- Inst.addOperand(MCOperand::CreateImm(0));
+ Inst.addOperand(MCOperand::createImm(0));
EmitInstruction(Out, Inst);
}
MCSymbol *DoneSym = Ctx.CreateTempSymbol();
@@ -913,7 +913,7 @@ void X86AddressSanitizer64::InstrumentMe
{
MCInst Inst;
Inst.setOpcode(X86::MOV8rm);
- Inst.addOperand(MCOperand::CreateReg(ShadowRegI8));
+ Inst.addOperand(MCOperand::createReg(ShadowRegI8));
const MCExpr *Disp = MCConstantExpr::Create(kShadowOffset, Ctx);
std::unique_ptr<X86Operand> Op(
X86Operand::CreateMem(getPointerWidth(), 0, Disp, ShadowRegI64, 0, 1,
@@ -996,7 +996,7 @@ void X86AddressSanitizer64::InstrumentMe
X86Operand::CreateMem(getPointerWidth(), 0, Disp, ShadowRegI64, 0, 1,
SMLoc(), SMLoc()));
Op->addMemOperands(Inst, 5);
- Inst.addOperand(MCOperand::CreateImm(0));
+ Inst.addOperand(MCOperand::createImm(0));
EmitInstruction(Out, Inst);
}
Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp?rev=237275&r1=237274&r2=237275&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp (original)
+++ llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp Wed May 13 13:37:00 2015
@@ -2333,8 +2333,8 @@ static bool convertToSExti8(MCInst &Inst
MCInst TmpInst;
TmpInst.setOpcode(Opcode);
if (!isCmp)
- TmpInst.addOperand(MCOperand::CreateReg(Reg));
- TmpInst.addOperand(MCOperand::CreateReg(Reg));
+ TmpInst.addOperand(MCOperand::createReg(Reg));
+ TmpInst.addOperand(MCOperand::createReg(Reg));
TmpInst.addOperand(Inst.getOperand(0));
Inst = TmpInst;
return true;
Modified: llvm/trunk/lib/Target/X86/AsmParser/X86Operand.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmParser/X86Operand.h?rev=237275&r1=237274&r2=237275&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/AsmParser/X86Operand.h (original)
+++ llvm/trunk/lib/Target/X86/AsmParser/X86Operand.h Wed May 13 13:37:00 2015
@@ -357,14 +357,14 @@ struct X86Operand : public MCParsedAsmOp
void addExpr(MCInst &Inst, const MCExpr *Expr) const {
// Add as immediates when possible.
if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
- Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
+ Inst.addOperand(MCOperand::createImm(CE->getValue()));
else
- Inst.addOperand(MCOperand::CreateExpr(Expr));
+ Inst.addOperand(MCOperand::createExpr(Expr));
}
void addRegOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateReg(getReg()));
+ Inst.addOperand(MCOperand::createReg(getReg()));
}
static unsigned getGR32FromGR64(unsigned RegNo) {
@@ -395,7 +395,7 @@ struct X86Operand : public MCParsedAsmOp
unsigned RegNo = getReg();
if (X86MCRegisterClasses[X86::GR64RegClassID].contains(RegNo))
RegNo = getGR32FromGR64(RegNo);
- Inst.addOperand(MCOperand::CreateReg(RegNo));
+ Inst.addOperand(MCOperand::createReg(RegNo));
}
void addAVX512RCOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
@@ -408,40 +408,40 @@ struct X86Operand : public MCParsedAsmOp
void addMemOperands(MCInst &Inst, unsigned N) const {
assert((N == 5) && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateReg(getMemBaseReg()));
- Inst.addOperand(MCOperand::CreateImm(getMemScale()));
- Inst.addOperand(MCOperand::CreateReg(getMemIndexReg()));
+ Inst.addOperand(MCOperand::createReg(getMemBaseReg()));
+ Inst.addOperand(MCOperand::createImm(getMemScale()));
+ Inst.addOperand(MCOperand::createReg(getMemIndexReg()));
addExpr(Inst, getMemDisp());
- Inst.addOperand(MCOperand::CreateReg(getMemSegReg()));
+ Inst.addOperand(MCOperand::createReg(getMemSegReg()));
}
void addAbsMemOperands(MCInst &Inst, unsigned N) const {
assert((N == 1) && "Invalid number of operands!");
// Add as immediates when possible.
if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemDisp()))
- Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
+ Inst.addOperand(MCOperand::createImm(CE->getValue()));
else
- Inst.addOperand(MCOperand::CreateExpr(getMemDisp()));
+ Inst.addOperand(MCOperand::createExpr(getMemDisp()));
}
void addSrcIdxOperands(MCInst &Inst, unsigned N) const {
assert((N == 2) && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateReg(getMemBaseReg()));
- Inst.addOperand(MCOperand::CreateReg(getMemSegReg()));
+ Inst.addOperand(MCOperand::createReg(getMemBaseReg()));
+ Inst.addOperand(MCOperand::createReg(getMemSegReg()));
}
void addDstIdxOperands(MCInst &Inst, unsigned N) const {
assert((N == 1) && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateReg(getMemBaseReg()));
+ Inst.addOperand(MCOperand::createReg(getMemBaseReg()));
}
void addMemOffsOperands(MCInst &Inst, unsigned N) const {
assert((N == 2) && "Invalid number of operands!");
// Add as immediates when possible.
if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemDisp()))
- Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
+ Inst.addOperand(MCOperand::createImm(CE->getValue()));
else
- Inst.addOperand(MCOperand::CreateExpr(getMemDisp()));
- Inst.addOperand(MCOperand::CreateReg(getMemSegReg()));
+ Inst.addOperand(MCOperand::createExpr(getMemDisp()));
+ Inst.addOperand(MCOperand::createReg(getMemSegReg()));
}
static std::unique_ptr<X86Operand> CreateToken(StringRef Str, SMLoc Loc) {
Modified: llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.cpp?rev=237275&r1=237274&r2=237275&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.cpp (original)
+++ llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.cpp Wed May 13 13:37:00 2015
@@ -180,7 +180,7 @@ static void translateRegister(MCInst &mc
#undef ENTRY
uint8_t llvmRegnum = llvmRegnums[reg];
- mcInst.addOperand(MCOperand::CreateReg(llvmRegnum));
+ mcInst.addOperand(MCOperand::createReg(llvmRegnum));
}
/// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the
@@ -248,11 +248,11 @@ static bool translateSrcIndex(MCInst &mc
assert(insn.mode == MODE_16BIT);
baseRegNo = insn.prefixPresent[0x67] ? X86::ESI : X86::SI;
}
- MCOperand baseReg = MCOperand::CreateReg(baseRegNo);
+ MCOperand baseReg = MCOperand::createReg(baseRegNo);
mcInst.addOperand(baseReg);
MCOperand segmentReg;
- segmentReg = MCOperand::CreateReg(segmentRegnums[insn.segmentOverride]);
+ segmentReg = MCOperand::createReg(segmentRegnums[insn.segmentOverride]);
mcInst.addOperand(segmentReg);
return false;
}
@@ -273,7 +273,7 @@ static bool translateDstIndex(MCInst &mc
assert(insn.mode == MODE_16BIT);
baseRegNo = insn.prefixPresent[0x67] ? X86::EDI : X86::DI;
}
- MCOperand baseReg = MCOperand::CreateReg(baseRegNo);
+ MCOperand baseReg = MCOperand::createReg(baseRegNo);
mcInst.addOperand(baseReg);
return false;
}
@@ -539,13 +539,13 @@ static void translateImmediate(MCInst &m
case TYPE_XMM32:
case TYPE_XMM64:
case TYPE_XMM128:
- mcInst.addOperand(MCOperand::CreateReg(X86::XMM0 + (immediate >> 4)));
+ mcInst.addOperand(MCOperand::createReg(X86::XMM0 + (immediate >> 4)));
return;
case TYPE_XMM256:
- mcInst.addOperand(MCOperand::CreateReg(X86::YMM0 + (immediate >> 4)));
+ mcInst.addOperand(MCOperand::createReg(X86::YMM0 + (immediate >> 4)));
return;
case TYPE_XMM512:
- mcInst.addOperand(MCOperand::CreateReg(X86::ZMM0 + (immediate >> 4)));
+ mcInst.addOperand(MCOperand::createReg(X86::ZMM0 + (immediate >> 4)));
return;
case TYPE_REL8:
isBranch = true;
@@ -568,12 +568,12 @@ static void translateImmediate(MCInst &m
if(!tryAddingSymbolicOperand(immediate + pcrel, isBranch, insn.startLocation,
insn.immediateOffset, insn.immediateSize,
mcInst, Dis))
- mcInst.addOperand(MCOperand::CreateImm(immediate));
+ mcInst.addOperand(MCOperand::createImm(immediate));
if (type == TYPE_MOFFS8 || type == TYPE_MOFFS16 ||
type == TYPE_MOFFS32 || type == TYPE_MOFFS64) {
MCOperand segmentReg;
- segmentReg = MCOperand::CreateReg(segmentRegnums[insn.segmentOverride]);
+ segmentReg = MCOperand::createReg(segmentRegnums[insn.segmentOverride]);
mcInst.addOperand(segmentReg);
}
}
@@ -606,7 +606,7 @@ static bool translateRMRegister(MCInst &
return true;
#define ENTRY(x) \
case EA_REG_##x: \
- mcInst.addOperand(MCOperand::CreateReg(X86::x)); break;
+ mcInst.addOperand(MCOperand::createReg(X86::x)); break;
ALL_REGS
#undef ENTRY
}
@@ -651,12 +651,12 @@ static bool translateRMMemory(MCInst &mc
return true;
#define ENTRY(x) \
case SIB_BASE_##x: \
- baseReg = MCOperand::CreateReg(X86::x); break;
+ baseReg = MCOperand::createReg(X86::x); break;
ALL_SIB_BASES
#undef ENTRY
}
} else {
- baseReg = MCOperand::CreateReg(0);
+ baseReg = MCOperand::createReg(0);
}
// Check whether we are handling VSIB addressing mode for GATHER.
@@ -706,7 +706,7 @@ static bool translateRMMemory(MCInst &mc
return true;
#define ENTRY(x) \
case SIB_INDEX_##x: \
- indexReg = MCOperand::CreateReg(X86::x); break;
+ indexReg = MCOperand::createReg(X86::x); break;
EA_BASES_32BIT
EA_BASES_64BIT
REGS_XMM
@@ -715,10 +715,10 @@ static bool translateRMMemory(MCInst &mc
#undef ENTRY
}
} else {
- indexReg = MCOperand::CreateReg(0);
+ indexReg = MCOperand::createReg(0);
}
- scaleAmount = MCOperand::CreateImm(insn.sibScale);
+ scaleAmount = MCOperand::createImm(insn.sibScale);
} else {
switch (insn.eaBase) {
case EA_BASE_NONE:
@@ -732,31 +732,31 @@ static bool translateRMMemory(MCInst &mc
tryAddingPcLoadReferenceComment(insn.startLocation +
insn.displacementOffset,
insn.displacement + pcrel, Dis);
- baseReg = MCOperand::CreateReg(X86::RIP); // Section 2.2.1.6
+ baseReg = MCOperand::createReg(X86::RIP); // Section 2.2.1.6
}
else
- baseReg = MCOperand::CreateReg(0);
+ baseReg = MCOperand::createReg(0);
- indexReg = MCOperand::CreateReg(0);
+ indexReg = MCOperand::createReg(0);
break;
case EA_BASE_BX_SI:
- baseReg = MCOperand::CreateReg(X86::BX);
- indexReg = MCOperand::CreateReg(X86::SI);
+ baseReg = MCOperand::createReg(X86::BX);
+ indexReg = MCOperand::createReg(X86::SI);
break;
case EA_BASE_BX_DI:
- baseReg = MCOperand::CreateReg(X86::BX);
- indexReg = MCOperand::CreateReg(X86::DI);
+ baseReg = MCOperand::createReg(X86::BX);
+ indexReg = MCOperand::createReg(X86::DI);
break;
case EA_BASE_BP_SI:
- baseReg = MCOperand::CreateReg(X86::BP);
- indexReg = MCOperand::CreateReg(X86::SI);
+ baseReg = MCOperand::createReg(X86::BP);
+ indexReg = MCOperand::createReg(X86::SI);
break;
case EA_BASE_BP_DI:
- baseReg = MCOperand::CreateReg(X86::BP);
- indexReg = MCOperand::CreateReg(X86::DI);
+ baseReg = MCOperand::createReg(X86::BP);
+ indexReg = MCOperand::createReg(X86::DI);
break;
default:
- indexReg = MCOperand::CreateReg(0);
+ indexReg = MCOperand::createReg(0);
switch (insn.eaBase) {
default:
debug("Unexpected eaBase");
@@ -767,7 +767,7 @@ static bool translateRMMemory(MCInst &mc
// placeholders to keep the compiler happy.
#define ENTRY(x) \
case EA_BASE_##x: \
- baseReg = MCOperand::CreateReg(X86::x); break;
+ baseReg = MCOperand::createReg(X86::x); break;
ALL_EA_BASES
#undef ENTRY
#define ENTRY(x) case EA_REG_##x:
@@ -779,12 +779,12 @@ static bool translateRMMemory(MCInst &mc
}
}
- scaleAmount = MCOperand::CreateImm(1);
+ scaleAmount = MCOperand::createImm(1);
}
- displacement = MCOperand::CreateImm(insn.displacement);
+ displacement = MCOperand::createImm(insn.displacement);
- segmentReg = MCOperand::CreateReg(segmentRegnums[insn.segmentOverride]);
+ segmentReg = MCOperand::createReg(segmentRegnums[insn.segmentOverride]);
mcInst.addOperand(baseReg);
mcInst.addOperand(scaleAmount);
@@ -856,7 +856,7 @@ static bool translateRM(MCInst &mcInst,
/// @param stackPos - The stack position to translate.
static void translateFPRegister(MCInst &mcInst,
uint8_t stackPos) {
- mcInst.addOperand(MCOperand::CreateReg(X86::ST0 + stackPos));
+ mcInst.addOperand(MCOperand::createReg(X86::ST0 + stackPos));
}
/// translateMaskRegister - Translates a 3-bit mask register number to
@@ -872,7 +872,7 @@ static bool translateMaskRegister(MCInst
return true;
}
- mcInst.addOperand(MCOperand::CreateReg(X86::K0 + maskRegNum));
+ mcInst.addOperand(MCOperand::createReg(X86::K0 + maskRegNum));
return false;
}
Modified: llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp?rev=237275&r1=237274&r2=237275&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp Wed May 13 13:37:00 2015
@@ -1475,7 +1475,7 @@ EncodeInstruction(const MCInst &MI, raw_
RegNum |= Val;
}
}
- EmitImmediate(MCOperand::CreateImm(RegNum), MI.getLoc(), 1, FK_Data_1,
+ EmitImmediate(MCOperand::createImm(RegNum), MI.getLoc(), 1, FK_Data_1,
CurByte, OS, Fixups);
} else {
EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(),
Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=237275&r1=237274&r2=237275&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Wed May 13 13:37:00 2015
@@ -6113,7 +6113,7 @@ void X86InstrInfo::getNoopForMachoTarget
void X86InstrInfo::getUnconditionalBranch(
MCInst &Branch, const MCSymbolRefExpr *BranchTarget) const {
Branch.setOpcode(X86::JMP_1);
- Branch.addOperand(MCOperand::CreateExpr(BranchTarget));
+ Branch.addOperand(MCOperand::createExpr(BranchTarget));
}
// This code must remain in sync with getJumpInstrTableEntryBound in this class!
Modified: llvm/trunk/lib/Target/X86/X86MCInstLower.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86MCInstLower.cpp?rev=237275&r1=237274&r2=237275&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86MCInstLower.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86MCInstLower.cpp Wed May 13 13:37:00 2015
@@ -288,7 +288,7 @@ MCOperand X86MCInstLower::LowerSymbolOpe
Expr = MCBinaryExpr::CreateAdd(Expr,
MCConstantExpr::Create(MO.getOffset(), Ctx),
Ctx);
- return MCOperand::CreateExpr(Expr);
+ return MCOperand::createExpr(Expr);
}
@@ -412,10 +412,10 @@ void X86MCInstLower::Lower(const Machine
case MachineOperand::MO_Register:
// Ignore all implicit register operands.
if (MO.isImplicit()) continue;
- MCOp = MCOperand::CreateReg(MO.getReg());
+ MCOp = MCOperand::createReg(MO.getReg());
break;
case MachineOperand::MO_Immediate:
- MCOp = MCOperand::CreateImm(MO.getImm());
+ MCOp = MCOperand::createImm(MO.getImm());
break;
case MachineOperand::MO_MachineBasicBlock:
case MachineOperand::MO_GlobalAddress:
@@ -714,28 +714,28 @@ void X86AsmPrinter::LowerTlsAddr(X86MCIn
MCInst LEA;
if (is64Bits) {
LEA.setOpcode(X86::LEA64r);
- LEA.addOperand(MCOperand::CreateReg(X86::RDI)); // dest
- LEA.addOperand(MCOperand::CreateReg(X86::RIP)); // base
- LEA.addOperand(MCOperand::CreateImm(1)); // scale
- LEA.addOperand(MCOperand::CreateReg(0)); // index
- LEA.addOperand(MCOperand::CreateExpr(symRef)); // disp
- LEA.addOperand(MCOperand::CreateReg(0)); // seg
+ LEA.addOperand(MCOperand::createReg(X86::RDI)); // dest
+ LEA.addOperand(MCOperand::createReg(X86::RIP)); // base
+ LEA.addOperand(MCOperand::createImm(1)); // scale
+ LEA.addOperand(MCOperand::createReg(0)); // index
+ LEA.addOperand(MCOperand::createExpr(symRef)); // disp
+ LEA.addOperand(MCOperand::createReg(0)); // seg
} else if (SRVK == MCSymbolRefExpr::VK_TLSLDM) {
LEA.setOpcode(X86::LEA32r);
- LEA.addOperand(MCOperand::CreateReg(X86::EAX)); // dest
- LEA.addOperand(MCOperand::CreateReg(X86::EBX)); // base
- LEA.addOperand(MCOperand::CreateImm(1)); // scale
- LEA.addOperand(MCOperand::CreateReg(0)); // index
- LEA.addOperand(MCOperand::CreateExpr(symRef)); // disp
- LEA.addOperand(MCOperand::CreateReg(0)); // seg
+ LEA.addOperand(MCOperand::createReg(X86::EAX)); // dest
+ LEA.addOperand(MCOperand::createReg(X86::EBX)); // base
+ LEA.addOperand(MCOperand::createImm(1)); // scale
+ LEA.addOperand(MCOperand::createReg(0)); // index
+ LEA.addOperand(MCOperand::createExpr(symRef)); // disp
+ LEA.addOperand(MCOperand::createReg(0)); // seg
} else {
LEA.setOpcode(X86::LEA32r);
- LEA.addOperand(MCOperand::CreateReg(X86::EAX)); // dest
- LEA.addOperand(MCOperand::CreateReg(0)); // base
- LEA.addOperand(MCOperand::CreateImm(1)); // scale
- LEA.addOperand(MCOperand::CreateReg(X86::EBX)); // index
- LEA.addOperand(MCOperand::CreateExpr(symRef)); // disp
- LEA.addOperand(MCOperand::CreateReg(0)); // seg
+ LEA.addOperand(MCOperand::createReg(X86::EAX)); // dest
+ LEA.addOperand(MCOperand::createReg(0)); // base
+ LEA.addOperand(MCOperand::createImm(1)); // scale
+ LEA.addOperand(MCOperand::createReg(X86::EBX)); // index
+ LEA.addOperand(MCOperand::createExpr(symRef)); // disp
+ LEA.addOperand(MCOperand::createReg(0)); // seg
}
EmitAndCountInstruction(LEA);
@@ -813,7 +813,6 @@ void X86AsmPrinter::LowerSTATEPOINT(cons
assert(Subtarget->is64Bit() && "Statepoint currently only supports X86-64");
StatepointOpers SOpers(&MI);
-
if (unsigned PatchBytes = SOpers.getNumPatchBytes()) {
EmitNops(*OutStreamer, PatchBytes, Subtarget->is64Bit(),
getSubtargetInfo());
@@ -834,7 +833,7 @@ void X86AsmPrinter::LowerSTATEPOINT(cons
// symbol is to far away. (TODO: support non-relative addressing)
break;
case MachineOperand::MO_Immediate:
- CallTargetMCOp = MCOperand::CreateImm(CallTarget.getImm());
+ CallTargetMCOp = MCOperand::createImm(CallTarget.getImm());
CallOpcode = X86::CALL64pcrel32;
// Currently, we only support relative addressing with statepoints.
// Otherwise, we'll need a scratch register to hold the target
@@ -842,7 +841,7 @@ void X86AsmPrinter::LowerSTATEPOINT(cons
// address is to far away. (TODO: support non-relative addressing)
break;
case MachineOperand::MO_Register:
- CallTargetMCOp = MCOperand::CreateReg(CallTarget.getReg());
+ CallTargetMCOp = MCOperand::createReg(CallTarget.getReg());
CallOpcode = X86::CALL64r;
break;
default:
@@ -898,7 +897,7 @@ void X86AsmPrinter::LowerPATCHPOINT(cons
llvm_unreachable("Unrecognized callee operand type.");
case MachineOperand::MO_Immediate:
if (CalleeMO.getImm())
- CalleeMCOp = MCOperand::CreateImm(CalleeMO.getImm());
+ CalleeMCOp = MCOperand::createImm(CalleeMO.getImm());
break;
case MachineOperand::MO_ExternalSymbol:
case MachineOperand::MO_GlobalAddress:
Modified: llvm/trunk/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp?rev=237275&r1=237274&r2=237275&view=diff
==============================================================================
--- llvm/trunk/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp (original)
+++ llvm/trunk/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp Wed May 13 13:37:00 2015
@@ -204,7 +204,7 @@ static DecodeStatus DecodeGRRegsRegister
if (RegNo > 11)
return MCDisassembler::Fail;
unsigned Reg = getReg(Decoder, XCore::GRRegsRegClassID, RegNo);
- Inst.addOperand(MCOperand::CreateReg(Reg));
+ Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success;
}
@@ -216,7 +216,7 @@ static DecodeStatus DecodeRRegsRegisterC
if (RegNo > 15)
return MCDisassembler::Fail;
unsigned Reg = getReg(Decoder, XCore::RRegsRegClassID, RegNo);
- Inst.addOperand(MCOperand::CreateReg(Reg));
+ Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success;
}
@@ -227,13 +227,13 @@ static DecodeStatus DecodeBitpOperand(MC
static unsigned Values[] = {
32 /*bpw*/, 1, 2, 3, 4, 5, 6, 7, 8, 16, 24, 32
};
- Inst.addOperand(MCOperand::CreateImm(Values[Val]));
+ Inst.addOperand(MCOperand::createImm(Values[Val]));
return MCDisassembler::Success;
}
static DecodeStatus DecodeNegImmOperand(MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder) {
- Inst.addOperand(MCOperand::CreateImm(-(int64_t)Val));
+ Inst.addOperand(MCOperand::createImm(-(int64_t)Val));
return MCDisassembler::Success;
}
@@ -362,7 +362,7 @@ Decode2RImmInstruction(MCInst &Inst, uns
if (S != MCDisassembler::Success)
return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
- Inst.addOperand(MCOperand::CreateImm(Op1));
+ Inst.addOperand(MCOperand::createImm(Op1));
DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
return S;
}
@@ -403,7 +403,7 @@ DecodeRUSInstruction(MCInst &Inst, unsig
return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
- Inst.addOperand(MCOperand::CreateImm(Op2));
+ Inst.addOperand(MCOperand::createImm(Op2));
return S;
}
@@ -552,7 +552,7 @@ Decode3RImmInstruction(MCInst &Inst, uns
unsigned Op1, Op2, Op3;
DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3);
if (S == MCDisassembler::Success) {
- Inst.addOperand(MCOperand::CreateImm(Op1));
+ Inst.addOperand(MCOperand::createImm(Op1));
DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
}
@@ -567,7 +567,7 @@ Decode2RUSInstruction(MCInst &Inst, unsi
if (S == MCDisassembler::Success) {
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
- Inst.addOperand(MCOperand::CreateImm(Op3));
+ Inst.addOperand(MCOperand::createImm(Op3));
}
return S;
}
@@ -623,7 +623,7 @@ DecodeL2RUSInstruction(MCInst &Inst, uns
if (S == MCDisassembler::Success) {
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
- Inst.addOperand(MCOperand::CreateImm(Op3));
+ Inst.addOperand(MCOperand::createImm(Op3));
}
return S;
}
Modified: llvm/trunk/lib/Target/XCore/XCoreMCInstLower.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreMCInstLower.cpp?rev=237275&r1=237274&r2=237275&view=diff
==============================================================================
--- llvm/trunk/lib/Target/XCore/XCoreMCInstLower.cpp (original)
+++ llvm/trunk/lib/Target/XCore/XCoreMCInstLower.cpp Wed May 13 13:37:00 2015
@@ -68,14 +68,14 @@ MCOperand XCoreMCInstLower::LowerSymbolO
const MCSymbolRefExpr *MCSym = MCSymbolRefExpr::Create(Symbol, Kind, *Ctx);
if (!Offset)
- return MCOperand::CreateExpr(MCSym);
+ return MCOperand::createExpr(MCSym);
// Assume offset is never negative.
assert(Offset > 0);
const MCConstantExpr *OffsetExpr = MCConstantExpr::Create(Offset, *Ctx);
const MCBinaryExpr *Add = MCBinaryExpr::CreateAdd(MCSym, OffsetExpr, *Ctx);
- return MCOperand::CreateExpr(Add);
+ return MCOperand::createExpr(Add);
}
MCOperand XCoreMCInstLower::LowerOperand(const MachineOperand &MO,
@@ -87,9 +87,9 @@ MCOperand XCoreMCInstLower::LowerOperand
case MachineOperand::MO_Register:
// Ignore all implicit register operands.
if (MO.isImplicit()) break;
- return MCOperand::CreateReg(MO.getReg());
+ return MCOperand::createReg(MO.getReg());
case MachineOperand::MO_Immediate:
- return MCOperand::CreateImm(MO.getImm() + offset);
+ return MCOperand::createImm(MO.getImm() + offset);
case MachineOperand::MO_MachineBasicBlock:
case MachineOperand::MO_GlobalAddress:
case MachineOperand::MO_ExternalSymbol:
Modified: llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp?rev=237275&r1=237274&r2=237275&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Wed May 13 13:37:00 2015
@@ -1870,7 +1870,7 @@ static void emitConvertFuncs(CodeGenTarg
break;
CvtOS << " case " << Name << ":\n"
- << " Inst.addOperand(MCOperand::CreateImm(" << Val << "));\n"
+ << " Inst.addOperand(MCOperand::createImm(" << Val << "));\n"
<< " break;\n";
OpOS << " case " << Name << ":\n"
@@ -1901,7 +1901,7 @@ static void emitConvertFuncs(CodeGenTarg
if (!IsNewConverter)
break;
CvtOS << " case " << Name << ":\n"
- << " Inst.addOperand(MCOperand::CreateReg(" << Reg << "));\n"
+ << " Inst.addOperand(MCOperand::createReg(" << Reg << "));\n"
<< " break;\n";
OpOS << " case " << Name << ":\n"
Modified: llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.cpp?rev=237275&r1=237274&r2=237275&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.cpp Wed May 13 13:37:00 2015
@@ -1054,7 +1054,7 @@ void FilterChooser::emitBinaryParser(raw
<< "(MI, tmp, Address, Decoder)"
<< Emitter->GuardPostfix << "\n";
else
- o.indent(Indentation) << "MI.addOperand(MCOperand::CreateImm(tmp));\n";
+ o.indent(Indentation) << "MI.addOperand(MCOperand::createImm(tmp));\n";
}
Modified: llvm/trunk/utils/TableGen/PseudoLoweringEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/PseudoLoweringEmitter.cpp?rev=237275&r1=237274&r2=237275&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/PseudoLoweringEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/PseudoLoweringEmitter.cpp Wed May 13 13:37:00 2015
@@ -232,12 +232,12 @@ void PseudoLoweringEmitter::emitLowering
<< " TmpInst.addOperand(MCOp);\n";
break;
case OpData::Imm:
- o << " TmpInst.addOperand(MCOperand::CreateImm("
+ o << " TmpInst.addOperand(MCOperand::createImm("
<< Expansion.OperandMap[MIOpNo + i].Data.Imm << "));\n";
break;
case OpData::Reg: {
Record *Reg = Expansion.OperandMap[MIOpNo + i].Data.Reg;
- o << " TmpInst.addOperand(MCOperand::CreateReg(";
+ o << " TmpInst.addOperand(MCOperand::createReg(";
// "zero_reg" is special.
if (Reg->getName() == "zero_reg")
o << "0";
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