[PATCH] [Hexagon] Remove dead constant assignment in hardware loop pass
Brendon Cahoon
bcahoon at codeaurora.org
Tue May 12 14:11:30 PDT 2015
Hi sundeepk, iajbar,
After converting a loop to a hardware loop, the pass should remove any unnecessary instructions from the old compare-and-branch code. This patch removes a dead constant assignment that was used in the compare instruction.
REPOSITORY
rL LLVM
http://reviews.llvm.org/D9720
Files:
lib/Target/Hexagon/HexagonHardwareLoops.cpp
test/CodeGen/Hexagon/hwloop-ph-deadcode.ll
Index: lib/Target/Hexagon/HexagonHardwareLoops.cpp
===================================================================
--- lib/Target/Hexagon/HexagonHardwareLoops.cpp
+++ lib/Target/Hexagon/HexagonHardwareLoops.cpp
@@ -670,6 +670,7 @@
MachineBasicBlock *DefBB = MRI->getVRegDef(R)->getParent();
if (!MDT->properlyDominates(DefBB, Header))
return nullptr;
+ OldInsts.push_back(MRI->getVRegDef(R));
}
return computeCount(L, InitialValue, EndValue, IVReg, IVBump, Cmp);
@@ -693,12 +694,14 @@
// If so, use the immediate value rather than the register.
if (Start->isReg()) {
const MachineInstr *StartValInstr = MRI->getVRegDef(Start->getReg());
- if (StartValInstr && StartValInstr->getOpcode() == Hexagon::A2_tfrsi)
+ if (StartValInstr && (StartValInstr->getOpcode() == Hexagon::A2_tfrsi ||
+ StartValInstr->getOpcode() == Hexagon::A2_tfrpi))
Start = &StartValInstr->getOperand(1);
}
if (End->isReg()) {
const MachineInstr *EndValInstr = MRI->getVRegDef(End->getReg());
- if (EndValInstr && EndValInstr->getOpcode() == Hexagon::A2_tfrsi)
+ if (EndValInstr && (EndValInstr->getOpcode() == Hexagon::A2_tfrsi ||
+ EndValInstr->getOpcode() == Hexagon::A2_tfrpi))
End = &EndValInstr->getOperand(1);
}
@@ -1832,11 +1835,14 @@
// created PHI node in the preheader.
for (unsigned i = 1, n = PN->getNumOperands(); i < n; i += 2) {
unsigned PredR = PN->getOperand(i).getReg();
+ unsigned PredRSub = PN->getOperand(i).getSubReg();
MachineBasicBlock *PredB = PN->getOperand(i+1).getMBB();
if (PredB == Latch)
continue;
- NewPN->addOperand(MachineOperand::CreateReg(PredR, false));
+ MachineOperand MO = MachineOperand::CreateReg(PredR, false);
+ MO.setSubReg(PredRSub);
+ NewPN->addOperand(MO);
NewPN->addOperand(MachineOperand::CreateMBB(PredB));
}
Index: test/CodeGen/Hexagon/hwloop-ph-deadcode.ll
===================================================================
--- /dev/null
+++ test/CodeGen/Hexagon/hwloop-ph-deadcode.ll
@@ -0,0 +1,23 @@
+; RUN: llc -march=hexagon -mcpu=hexagonv5 -O2 -disable-block-placement=0 < %s | FileCheck %s
+
+; Test that there is no redundant register assignment in the hardware loop
+; preheader.
+
+; CHECK-NOT: r{{.*}} = #5
+
+ at g = external global i32
+
+define void @foo() #0 {
+entry:
+ br i1 undef, label %if.end38, label %for.body
+
+for.body:
+ %loopIdx.051 = phi i32 [ %inc, %for.body ], [ 0, %entry ]
+ store i32 1, i32* @g, align 4
+ %inc = add i32 %loopIdx.051, 1
+ %cmp9 = icmp ult i32 %inc, 5
+ br i1 %cmp9, label %for.body, label %if.end38
+
+if.end38:
+ ret void
+}
EMAIL PREFERENCES
http://reviews.llvm.org/settings/panel/emailpreferences/
-------------- next part --------------
A non-text attachment was scrubbed...
Name: D9720.25623.patch
Type: text/x-patch
Size: 2744 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20150512/f104497b/attachment.bin>
More information about the llvm-commits
mailing list