[llvm] r237142 - R600/SI: Remove M0Reg register class

[Tom Stellard]

Author: tstellar
Date: Tue May 12 10:00:52 2015
New Revision: 237142

URL: http://llvm.org/viewvc/llvm-project?rev=237142&view=rev
Log:
R600/SI: Remove M0Reg register class

It is no longer used.

Modified:
    llvm/trunk/lib/Target/R600/SIFixSGPRCopies.cpp
    llvm/trunk/lib/Target/R600/SIRegisterInfo.cpp
    llvm/trunk/lib/Target/R600/SIRegisterInfo.td
    llvm/trunk/test/CodeGen/R600/ds_read2st64.ll

Modified: llvm/trunk/lib/Target/R600/SIFixSGPRCopies.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/SIFixSGPRCopies.cpp?rev=237142&r1=237141&r2=237142&view=diff
==============================================================================
--- llvm/trunk/lib/Target/R600/SIFixSGPRCopies.cpp (original)
+++ llvm/trunk/lib/Target/R600/SIFixSGPRCopies.cpp Tue May 12 10:00:52 2015
@@ -194,7 +194,6 @@ bool SIFixSGPRCopies::isVGPRToSGPRCopy(c
   const TargetRegisterClass *SrcRC;
 
   if (!TargetRegisterInfo::isVirtualRegister(SrcReg) ||
-      DstRC == &AMDGPU::M0RegRegClass ||
       MRI.getRegClass(SrcReg) == &AMDGPU::VReg_1RegClass)
     return false;
 

Modified: llvm/trunk/lib/Target/R600/SIRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/SIRegisterInfo.cpp?rev=237142&r1=237141&r2=237142&view=diff
==============================================================================
--- llvm/trunk/lib/Target/R600/SIRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/R600/SIRegisterInfo.cpp Tue May 12 10:00:52 2015
@@ -347,7 +347,6 @@ const TargetRegisterClass *SIRegisterInf
   assert(!TargetRegisterInfo::isVirtualRegister(Reg));
 
   static const TargetRegisterClass *BaseClasses[] = {
-    &AMDGPU::M0RegRegClass,
     &AMDGPU::VGPR_32RegClass,
     &AMDGPU::SReg_32RegClass,
     &AMDGPU::VReg_64RegClass,

Modified: llvm/trunk/lib/Target/R600/SIRegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/SIRegisterInfo.td?rev=237142&r1=237141&r2=237142&view=diff
==============================================================================
--- llvm/trunk/lib/Target/R600/SIRegisterInfo.td (original)
+++ llvm/trunk/lib/Target/R600/SIRegisterInfo.td Tue May 12 10:00:52 2015
@@ -182,11 +182,10 @@ def SCCReg : RegisterClass<"AMDGPU", [i3
 
 def VCCReg : RegisterClass<"AMDGPU", [i64, i1], 64, (add VCC)>;
 def EXECReg : RegisterClass<"AMDGPU", [i64, i1], 64, (add EXEC)>;
-def M0Reg : RegisterClass<"AMDGPU", [i32], 32, (add M0)>;
 
 // Register class for all scalar registers (SGPRs + Special Registers)
 def SReg_32 : RegisterClass<"AMDGPU", [i32, f32], 32,
-  (add SGPR_32, M0Reg, VCC_LO, VCC_HI, EXEC_LO, EXEC_HI, FLAT_SCR_LO, FLAT_SCR_HI)
+  (add SGPR_32, M0, VCC_LO, VCC_HI, EXEC_LO, EXEC_HI, FLAT_SCR_LO, FLAT_SCR_HI)
 >;
 
 def SGPR_64 : RegisterClass<"AMDGPU", [v2i32, i64, f64], 64, (add SGPR_64Regs)>;

Modified: llvm/trunk/test/CodeGen/R600/ds_read2st64.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/ds_read2st64.ll?rev=237142&r1=237141&r2=237142&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/R600/ds_read2st64.ll (original)
+++ llvm/trunk/test/CodeGen/R600/ds_read2st64.ll Tue May 12 10:00:52 2015
@@ -65,8 +65,8 @@ define void @simple_read2st64_f32_max_of
 
 ; SI-LABEL: @simple_read2st64_f32_over_max_offset
 ; SI-NOT: ds_read2st64_b32
-; SI: ds_read_b32 {{v[0-9]+}}, {{v[0-9]+}} offset:256
 ; SI: v_add_i32_e32 [[BIGADD:v[0-9]+]], 0x10000, {{v[0-9]+}}
+; SI: ds_read_b32 {{v[0-9]+}}, {{v[0-9]+}} offset:256
 ; SI: ds_read_b32 {{v[0-9]+}}, [[BIGADD]]
 ; SI: s_endpgm
 define void @simple_read2st64_f32_over_max_offset(float addrspace(1)* %out, float addrspace(3)* %lds) #0 {