[PATCH] [LLVM - ARM/AArch64] Add ACLE special register intrinsics (10.1)

[Renato Golin]

Hi Luke,

Nice patch! I have some early inline comments, but I'll review the bulk of it later.

I also noticed you have added no new tests, did you forget to "git add" the files?

cheers,
--renato


================
Comment at: lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp:4029
@@ -4028,3 +4028,3 @@
     Value *RegValue = I.getArgOperand(1);
-    SDValue Chain = getValue(RegValue).getOperand(0);
+    SDValue Chain = getRoot();
     SDValue RegName =
----------------
Good catch! This could even be moved inside the DAG.setRoot() call below, like the others.

================
Comment at: lib/Target/ARM/ARMISelLowering.cpp:4119
@@ +4118,3 @@
+
+  SDValue Read = DAG.getNode(ISD::READ_REGISTER, DL,
+                             DAG.getVTList(MVT::i32, MVT::i32), Op);
----------------
Maybe an assert on Op.getValueType() being 64-bits would be good here.

================
Comment at: lib/Target/ARM/ARMISelLowering.cpp:6542
@@ -6510,1 +6541,3 @@
     llvm_unreachable("Don't know how to custom expand this!");
+  case ISD::READ_REGISTER:
+    Res = ExpandREAD_REGISTER(N, DAG);
----------------
I'm a bit rusty in SelectionDAG, but can we always guarantee that we'll only have 64-bit types here?

http://reviews.llvm.org/D9699

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