[PATCH] [mips] [IAS] Slightly improve shift instruction generation in expandLoadImm.

[Daniel Sanders]

LGTM with the emission of a redundant instruction avoided.


================
Comment at: lib/Target/Mips/AsmParser/MipsAsmParser.cpp:1822-1823
@@ +1821,4 @@
+    if (Bits31To16 == 0) {
+      createLShiftOri<32>(0, Reg, IDLoc, Instructions);
+      createLShiftOri<0>(Bits15To0, Reg, IDLoc, Instructions);
+    } else {
----------------
Shouldn't this be:
  createLShiftOri<32>(Bits15To0, Reg, IDLoc, Instructions);
It looks like it will emit:
  dsll $Reg, $Reg, 32
  ori $Reg, $Reg, 0
  ori $Reg, $Reg, Bits15To0
at the moment.

================
Comment at: lib/Target/Mips/AsmParser/MipsAsmParser.cpp:1982
@@ -1966,2 +1981,3 @@
+    createLShiftOri<0>(MCOperand::CreateExpr(LoExpr), RegNo, SMLoc(),
                          Instructions);
   }
----------------
Nit: Indentation

http://reviews.llvm.org/D8974

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