[llvm] r236099 - [mips] Correct 128-bit shifts on 64-bit targets.
Tom Stellard
tom at stellard.net
Wed Apr 29 08:22:28 PDT 2015
On Wed, Apr 29, 2015 at 02:59:08PM +0000, Daniel Sanders wrote:
> Hi Tom,
>
> I'd like to merge this into 3.6.1 too. Is that ok with you?
>
Yes, go ahead and merge it.
-Tom
> > -----Original Message-----
> > From: llvm-commits-bounces at cs.uiuc.edu [mailto:llvm-commits-
> > bounces at cs.uiuc.edu] On Behalf Of Daniel Sanders
> > Sent: 29 April 2015 13:29
> > To: llvm-commits at cs.uiuc.edu
> > Subject: [llvm] r236099 - [mips] Correct 128-bit shifts on 64-bit targets.
> >
> > Author: dsanders
> > Date: Wed Apr 29 07:28:58 2015
> > New Revision: 236099
> >
> > URL: http://llvm.org/viewvc/llvm-project?rev=236099&view=rev
> > Log:
> > [mips] Correct 128-bit shifts on 64-bit targets.
> >
> > Summary:
> > The existing code was correct for 32-bit GPR's but not 64-bit GPR's. It now
> > accounts for both cases.
> >
> > Reviewers: vkalintiris
> >
> > Reviewed By: vkalintiris
> >
> > Subscribers: llvm-commits, mohit.bhakkad, sagar
> >
> > Differential Revision: http://reviews.llvm.org/D9337
> >
> > Modified:
> > llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
> > llvm/trunk/test/CodeGen/Mips/llvm-ir/ashr.ll
> > llvm/trunk/test/CodeGen/Mips/llvm-ir/lshr.ll
> > llvm/trunk/test/CodeGen/Mips/llvm-ir/shl.ll
> >
> > Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
> > URL: http://llvm.org/viewvc/llvm-
> > project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=236099&r1=2
> > 36098&r2=236099&view=diff
> > ==========================================================
> > ====================
> > --- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original)
> > +++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Wed Apr 29 07:28:58
> > 2015
> > @@ -2074,7 +2074,7 @@ SDValue MipsTargetLowering::lowerShiftLe
> > SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo);
> > SDValue ShiftLeftLo = DAG.getNode(ISD::SHL, DL, VT, Lo, Shamt);
> > SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
> > - DAG.getConstant(0x20, DL, MVT::i32));
> > + DAG.getConstant(VT.getSizeInBits(), DL, MVT::i32));
> > Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond,
> > DAG.getConstant(0, DL, VT), ShiftLeftLo);
> > Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftLeftLo, Or);
> > @@ -2113,12 +2113,12 @@ SDValue MipsTargetLowering::lowerShiftRi
> > SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL,
> > DL, VT, Hi, Shamt);
> > SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
> > - DAG.getConstant(0x20, DL, MVT::i32));
> > - SDValue Shift31 = DAG.getNode(ISD::SRA, DL, VT, Hi,
> > - DAG.getConstant(31, DL, VT));
> > + DAG.getConstant(VT.getSizeInBits(), DL, MVT::i32));
> > + SDValue Ext = DAG.getNode(ISD::SRA, DL, VT, Hi,
> > + DAG.getConstant(VT.getSizeInBits() - 1, DL, VT));
> > Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftRightHi, Or);
> > Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond,
> > - IsSRA ? Shift31 : DAG.getConstant(0, DL, VT), ShiftRightHi);
> > + IsSRA ? Ext : DAG.getConstant(0, DL, VT), ShiftRightHi);
> >
> > SDValue Ops[2] = {Lo, Hi};
> > return DAG.getMergeValues(Ops, DL);
> >
> > Modified: llvm/trunk/test/CodeGen/Mips/llvm-ir/ashr.ll
> > URL: http://llvm.org/viewvc/llvm-
> > project/llvm/trunk/test/CodeGen/Mips/llvm-
> > ir/ashr.ll?rev=236099&r1=236098&r2=236099&view=diff
> > ==========================================================
> > ====================
> > --- llvm/trunk/test/CodeGen/Mips/llvm-ir/ashr.ll (original)
> > +++ llvm/trunk/test/CodeGen/Mips/llvm-ir/ashr.ll Wed Apr 29 07:28:58 2015
> > @@ -145,7 +145,7 @@ entry:
> >
> > ; M3: sll $[[T0:[0-9]+]], $7, 0
> > ; M3: dsrav $[[T1:[0-9]+]], $4, $7
> > - ; M3: andi $[[T2:[0-9]+]], $[[T0]], 32
> > + ; M3: andi $[[T2:[0-9]+]], $[[T0]], 64
> > ; M3: bnez $[[T3:[0-9]+]], $[[BB0:BB[0-9_]+]]
> > ; M3: move $3, $[[T1]]
> > ; M3: dsrlv $[[T4:[0-9]+]], $5, $7
> > @@ -156,7 +156,7 @@ entry:
> > ; M3: $[[BB0]]:
> > ; M3: beqz $[[T3]], $[[BB1:BB[0-9_]+]]
> > ; M3: nop
> > - ; M3: dsra $2, $4, 31
> > + ; M3: dsra $2, $4, 63
> > ; M3: $[[BB1]]:
> > ; M3: jr $ra
> > ; M3: nop
> > @@ -168,18 +168,18 @@ entry:
> > ; GP64-NOT-R6: dsllv $[[T4:[0-9]+]], $[[T1]], $[[T3]]
> > ; GP64-NOT-R6: or $3, $[[T4]], $[[T0]]
> > ; GP64-NOT-R6: dsrav $2, $4, $7
> > - ; GP64-NOT-R6: andi $[[T5:[0-9]+]], $[[T2]], 32
> > + ; GP64-NOT-R6: andi $[[T5:[0-9]+]], $[[T2]], 64
> > ; GP64-NOT-R6: movn $3, $2, $[[T5]]
> > - ; GP64-NOT-R6: dsra $[[T6:[0-9]+]], $4, 31
> > + ; GP64-NOT-R6: dsra $[[T6:[0-9]+]], $4, 63
> > ; GP64-NOT-R6: jr $ra
> > ; GP64-NOT-R6: movn $2, $[[T6]], $[[T5]]
> >
> > ; 64R6: dsrav $[[T0:[0-9]+]], $4, $7
> > ; 64R6: sll $[[T1:[0-9]+]], $7, 0
> > - ; 64R6: andi $[[T2:[0-9]+]], $[[T1]], 32
> > + ; 64R6: andi $[[T2:[0-9]+]], $[[T1]], 64
> > ; 64R6: sll $[[T3:[0-9]+]], $[[T2]], 0
> > ; 64R6: seleqz $[[T4:[0-9]+]], $[[T0]], $[[T3]]
> > - ; 64R6: dsra $[[T5:[0-9]+]], $4, 31
> > + ; 64R6: dsra $[[T5:[0-9]+]], $4, 63
> > ; 64R6: selnez $[[T6:[0-9]+]], $[[T5]], $[[T3]]
> > ; 64R6: or $2, $[[T6]], $[[T4]]
> > ; 64R6: dsrlv $[[T7:[0-9]+]], $5, $7
> >
> > Modified: llvm/trunk/test/CodeGen/Mips/llvm-ir/lshr.ll
> > URL: http://llvm.org/viewvc/llvm-
> > project/llvm/trunk/test/CodeGen/Mips/llvm-
> > ir/lshr.ll?rev=236099&r1=236098&r2=236099&view=diff
> > ==========================================================
> > ====================
> > --- llvm/trunk/test/CodeGen/Mips/llvm-ir/lshr.ll (original)
> > +++ llvm/trunk/test/CodeGen/Mips/llvm-ir/lshr.ll Wed Apr 29 07:28:58 2015
> > @@ -139,7 +139,7 @@ entry:
> >
> > ; M3: sll $[[T0:[0-9]+]], $7, 0
> > ; M3: dsrlv $[[T1:[0-9]+]], $4, $7
> > - ; M3: andi $[[T2:[0-9]+]], $[[T0]], 32
> > + ; M3: andi $[[T2:[0-9]+]], $[[T0]], 64
> > ; M3: bnez $[[T3:[0-9]+]], $[[BB0:BB[0-9_]+]]
> > ; M3: move $3, $[[T1]]
> > ; M3: dsrlv $[[T4:[0-9]+]], $5, $7
> > @@ -162,7 +162,7 @@ entry:
> > ; GP64-NOT-R6: dsllv $[[T4:[0-9]+]], $[[T1]], $[[T3]]
> > ; GP64-NOT-R6: or $3, $[[T4]], $[[T0]]
> > ; GP64-NOT-R6: dsrlv $2, $4, $7
> > - ; GP64-NOT-R6: andi $[[T5:[0-9]+]], $[[T2]], 32
> > + ; GP64-NOT-R6: andi $[[T5:[0-9]+]], $[[T2]], 64
> > ; GP64-NOT-R6: movn $3, $2, $[[T5]]
> > ; GP64-NOT-R6: jr $ra
> > ; GP64-NOT-R6: movn $2, $zero, $1
> > @@ -173,7 +173,7 @@ entry:
> > ; 64R6: not $[[T3:[0-9]+]], $[[T2]]
> > ; 64R6: dsllv $[[T4:[0-9]+]], $[[T1]], $[[T3]]
> > ; 64R6: or $[[T5:[0-9]+]], $[[T4]], $[[T0]]
> > - ; 64R6: andi $[[T6:[0-9]+]], $[[T2]], 32
> > + ; 64R6: andi $[[T6:[0-9]+]], $[[T2]], 64
> > ; 64R6: sll $[[T7:[0-9]+]], $[[T6]], 0
> > ; 64R6: seleqz $[[T8:[0-9]+]], $[[T5]], $[[T7]]
> > ; 64R6: dsrlv $[[T9:[0-9]+]], $4, $7
> >
> > Modified: llvm/trunk/test/CodeGen/Mips/llvm-ir/shl.ll
> > URL: http://llvm.org/viewvc/llvm-
> > project/llvm/trunk/test/CodeGen/Mips/llvm-
> > ir/shl.ll?rev=236099&r1=236098&r2=236099&view=diff
> > ==========================================================
> > ====================
> > --- llvm/trunk/test/CodeGen/Mips/llvm-ir/shl.ll (original)
> > +++ llvm/trunk/test/CodeGen/Mips/llvm-ir/shl.ll Wed Apr 29 07:28:58 2015
> > @@ -151,7 +151,7 @@ entry:
> >
> > ; M3: sll $[[T0:[0-9]+]], $7, 0
> > ; M3: dsllv $[[T1:[0-9]+]], $5, $7
> > - ; M3: andi $[[T2:[0-9]+]], $[[T0]], 32
> > + ; M3: andi $[[T2:[0-9]+]], $[[T0]], 64
> > ; M3: bnez $[[T3:[0-9]+]], $[[BB0:BB[0-9_]+]]
> > ; M3: move $2, $[[T1]]
> > ; M3: dsllv $[[T4:[0-9]+]], $4, $7
> > @@ -174,7 +174,7 @@ entry:
> > ; GP64-NOT-R6: dsrlv $[[T4:[0-9]+]], $[[T1]], $[[T3]]
> > ; GP64-NOT-R6: or $2, $[[T0]], $[[T4]]
> > ; GP64-NOT-R6: dsllv $3, $5, $7
> > - ; GP64-NOT-R6: andi $[[T5:[0-9]+]], $[[T2]], 32
> > + ; GP64-NOT-R6: andi $[[T5:[0-9]+]], $[[T2]], 64
> > ; GP64-NOT-R6: movn $2, $3, $[[T5]]
> > ; GP64-NOT-R6: jr $ra
> > ; GP64-NOT-R6: movn $3, $zero, $1
> > @@ -185,7 +185,7 @@ entry:
> > ; 64R6: not $[[T3:[0-9]+]], $[[T2]]
> > ; 64R6: dsrlv $[[T4:[0-9]+]], $[[T1]], $[[T3]]
> > ; 64R6: or $[[T5:[0-9]+]], $[[T0]], $[[T4]]
> > - ; 64R6: andi $[[T6:[0-9]+]], $[[T2]], 32
> > + ; 64R6: andi $[[T6:[0-9]+]], $[[T2]], 64
> > ; 64R6: sll $[[T7:[0-9]+]], $[[T6]], 0
> > ; 64R6: seleqz $[[T8:[0-9]+]], $[[T5]], $[[T7]]
> > ; 64R6: dsllv $[[T9:[0-9]+]], $5, $7
> >
> >
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