[llvm] r236107 - Sparc: Prefer reg+reg address encoding when only one register used.
James Y Knight
jyknight at google.com
Wed Apr 29 07:54:44 PDT 2015
Author: jyknight
Date: Wed Apr 29 09:54:44 2015
New Revision: 236107
URL: http://llvm.org/viewvc/llvm-project?rev=236107&view=rev
Log:
Sparc: Prefer reg+reg address encoding when only one register used.
Reg+%g0 is preferred to Reg+imm0 by the manual, and is what GCC produces.
Futhermore, reg+imm is invalid for the (not yet supported) "alternate
address space" instructions.
Differential Revision: http://reviews.llvm.org/D8753
Modified:
llvm/trunk/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
llvm/trunk/test/MC/Disassembler/Sparc/sparc-mem.txt
llvm/trunk/test/MC/Sparc/sparc-ctrl-instructions.s
llvm/trunk/test/MC/Sparc/sparc-mem-instructions.s
Modified: llvm/trunk/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp?rev=236107&r1=236106&r2=236107&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp Wed Apr 29 09:54:44 2015
@@ -360,11 +360,11 @@ public:
}
static std::unique_ptr<SparcOperand>
- CreateMEMri(unsigned Base, const MCExpr *Off, SMLoc S, SMLoc E) {
- auto Op = make_unique<SparcOperand>(k_MemoryImm);
+ CreateMEMr(unsigned Base, SMLoc S, SMLoc E) {
+ auto Op = make_unique<SparcOperand>(k_MemoryReg);
Op->Mem.Base = Base;
- Op->Mem.OffsetReg = 0;
- Op->Mem.Off = Off;
+ Op->Mem.OffsetReg = Sparc::G0; // always 0
+ Op->Mem.Off = nullptr;
Op->StartLoc = S;
Op->EndLoc = E;
return Op;
@@ -556,7 +556,7 @@ SparcAsmParser::parseMEMOperand(OperandV
case AsmToken::Comma:
case AsmToken::RBrac:
case AsmToken::EndOfStatement:
- Operands.push_back(SparcOperand::CreateMEMri(BaseReg, nullptr, S, E));
+ Operands.push_back(SparcOperand::CreateMEMr(BaseReg, S, E));
return MatchOperand_Success;
case AsmToken:: Plus:
Modified: llvm/trunk/test/MC/Disassembler/Sparc/sparc-mem.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Sparc/sparc-mem.txt?rev=236107&r1=236106&r2=236107&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Sparc/sparc-mem.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Sparc/sparc-mem.txt Wed Apr 29 09:54:44 2015
@@ -9,6 +9,9 @@
# CHECK: ldsb [%g1], %o4
0xd8 0x48 0x60 0x00
+# CHECK: ldsb [%g1], %o4
+0xd8 0x48 0x40 0x00
+
# CHECK: ldsh [%i0+%l6], %o2
0xd4 0x56 0x00 0x16
@@ -18,6 +21,9 @@
# CHECK: ldsh [%g1], %o4
0xd8 0x50 0x60 0x00
+# CHECK: ldsh [%g1], %o4
+0xd8 0x50 0x40 0x00
+
# CHECK: ldub [%i0+%l6], %o2
0xd4 0x0e 0x00 0x16
@@ -27,6 +33,9 @@
# CHECK: ldub [%g1], %o2
0xd4 0x08 0x60 0x00
+# CHECK: ldub [%g1], %o2
+0xd4 0x08 0x40 0x00
+
# CHECK: lduh [%i0+%l6], %o2
0xd4 0x16 0x00 0x16
@@ -36,6 +45,9 @@
# CHECK: lduh [%g1], %o2
0xd4 0x10 0x60 0x00
+# CHECK: lduh [%g1], %o2
+0xd4 0x10 0x40 0x00
+
# CHECK: ld [%i0+%l6], %o2
0xd4 0x06 0x00 0x16
@@ -45,6 +57,9 @@
# CHECK: ld [%g1], %o2
0xd4 0x00 0x60 0x00
+# CHECK: ld [%g1], %o2
+0xd4 0x00 0x40 0x00
+
# CHECK: ld [%i0+%l6], %f2
0xc5 0x06 0x00 0x16
@@ -54,6 +69,9 @@
# CHECK: ld [%g1], %f2
0xc5 0x00 0x60 0x00
+# CHECK: ld [%g1], %f2
+0xc5 0x00 0x40 0x00
+
# CHECK: ldd [%i0+%l6], %f2
0xc5 0x1e 0x00 0x16
@@ -63,6 +81,9 @@
# CHECK: ldd [%g1], %f2
0xc5 0x18 0x60 0x00
+# CHECK: ldd [%g1], %f2
+0xc5 0x18 0x40 0x00
+
# CHECK: ldq [%i0+%l6], %f4
0xc9 0x16 0x00 0x16
@@ -72,6 +93,9 @@
# CHECK: ldq [%g1], %f4
0xc9 0x10 0x60 0x00
+# CHECK: ldq [%g1], %f4
+0xc9 0x10 0x40 0x00
+
# CHECK: ldx [%i0+%l6], %o2
0xd4 0x5e 0x00 0x16
@@ -81,6 +105,9 @@
# CHECK: ldx [%g1], %o2
0xd4 0x58 0x60 0x00
+# CHECK: ldx [%g1], %o2
+0xd4 0x58 0x40 0x00
+
# CHECK: ldsw [%i0+%l6], %o2
0xd4 0x46 0x00 0x16
@@ -90,6 +117,9 @@
# CHECK: ldsw [%g1], %o2
0xd4 0x40 0x60 0x00
+# CHECK: ldsw [%g1], %o2
+0xd4 0x40 0x40 0x00
+
# CHECK: stb %o2, [%i0+%l6]
0xd4 0x2e 0x00 0x16
@@ -99,6 +129,9 @@
# CHECK: stb %o2, [%g1]
0xd4 0x28 0x60 0x00
+# CHECK: stb %o2, [%g1]
+0xd4 0x28 0x40 0x00
+
# CHECK: sth %o2, [%i0+%l6]
0xd4 0x36 0x00 0x16
@@ -108,6 +141,9 @@
# CHECK: sth %o2, [%g1]
0xd4 0x30 0x60 0x00
+# CHECK: sth %o2, [%g1]
+0xd4 0x30 0x40 0x00
+
# CHECK: st %o2, [%i0+%l6]
0xd4 0x26 0x00 0x16
@@ -117,6 +153,9 @@
# CHECK: st %o2, [%g1]
0xd4 0x20 0x60 0x00
+# CHECK: st %o2, [%g1]
+0xd4 0x20 0x40 0x00
+
# CHECK: st %f2, [%i0+%l6]
0xc5 0x26 0x00 0x16
@@ -126,6 +165,9 @@
# CHECK: st %f2, [%g1]
0xc5 0x20 0x60 0x00
+# CHECK: st %f2, [%g1]
+0xc5 0x20 0x40 0x00
+
# CHECK: std %f2, [%i0+%l6]
0xc5 0x3e 0x00 0x16
@@ -135,6 +177,9 @@
# CHECK: std %f2, [%g1]
0xc5 0x38 0x60 0x00
+# CHECK: std %f2, [%g1]
+0xc5 0x38 0x40 0x00
+
# CHECK: stq %f4, [%i0+%l6]
0xc9 0x36 0x00 0x16
@@ -144,6 +189,9 @@
# CHECK: stq %f4, [%g1]
0xc9 0x30 0x60 0x00
+# CHECK: stq %f4, [%g1]
+0xc9 0x30 0x40 0x00
+
# CHECK: stx %o2, [%i0+%l6]
0xd4 0x76 0x00 0x16
@@ -153,6 +201,9 @@
# CHECK: stx %o2, [%g1]
0xd4 0x70 0x60 0x00
+# CHECK: stx %o2, [%g1]
+0xd4 0x70 0x40 0x00
+
# CHECK: swap [%i0+%l6], %o2
0xd4 0x7e 0x00 0x16
@@ -161,3 +212,6 @@
# CHECK: swap [%g1], %o2
0xd4 0x78 0x60 0x00
+
+# CHECK: swap [%g1], %o2
+0xd4 0x78 0x40 0x00
Modified: llvm/trunk/test/MC/Sparc/sparc-ctrl-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Sparc/sparc-ctrl-instructions.s?rev=236107&r1=236106&r2=236107&view=diff
==============================================================================
--- llvm/trunk/test/MC/Sparc/sparc-ctrl-instructions.s (original)
+++ llvm/trunk/test/MC/Sparc/sparc-ctrl-instructions.s Wed Apr 29 09:54:44 2015
@@ -11,7 +11,7 @@
! CHECK: call %o1+8 ! encoding: [0x9f,0xc2,0x60,0x08]
call %o1 + 8
- ! CHECK: call %g1 ! encoding: [0x9f,0xc0,0x60,0x00]
+ ! CHECK: call %g1 ! encoding: [0x9f,0xc0,0x40,0x00]
call %g1
! CHECK: call %g1+%lo(sym) ! encoding: [0x9f,0xc0,0b011000AA,A]
@@ -24,7 +24,7 @@
! CHECK: jmp %o1+8 ! encoding: [0x81,0xc2,0x60,0x08]
jmp %o1 + 8
- ! CHECK: jmp %g1 ! encoding: [0x81,0xc0,0x60,0x00]
+ ! CHECK: jmp %g1 ! encoding: [0x81,0xc0,0x40,0x00]
jmp %g1
! CHECK: jmp %g1+%lo(sym) ! encoding: [0x81,0xc0,0b011000AA,A]
@@ -37,7 +37,7 @@
! CHECK: jmpl %o1+8, %g2 ! encoding: [0x85,0xc2,0x60,0x08]
jmpl %o1 + 8, %g2
- ! CHECK: jmpl %g1, %g2 ! encoding: [0x85,0xc0,0x60,0x00]
+ ! CHECK: jmpl %g1, %g2 ! encoding: [0x85,0xc0,0x40,0x00]
jmpl %g1, %g2
! CHECK: jmpl %g1+%lo(sym), %g2 ! encoding: [0x85,0xc0,0b011000AA,A]
Modified: llvm/trunk/test/MC/Sparc/sparc-mem-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Sparc/sparc-mem-instructions.s?rev=236107&r1=236106&r2=236107&view=diff
==============================================================================
--- llvm/trunk/test/MC/Sparc/sparc-mem-instructions.s (original)
+++ llvm/trunk/test/MC/Sparc/sparc-mem-instructions.s Wed Apr 29 09:54:44 2015
@@ -5,54 +5,54 @@
ldsb [%i0 + %l6], %o2
! CHECK: ldsb [%i0+32], %o2 ! encoding: [0xd4,0x4e,0x20,0x20]
ldsb [%i0 + 32], %o2
- ! CHECK: ldsb [%g1], %o4 ! encoding: [0xd8,0x48,0x60,0x00]
+ ! CHECK: ldsb [%g1], %o4 ! encoding: [0xd8,0x48,0x40,0x00]
ldsb [%g1], %o4
! CHECK: ldsh [%i0+%l6], %o2 ! encoding: [0xd4,0x56,0x00,0x16]
ldsh [%i0 + %l6], %o2
! CHECK: ldsh [%i0+32], %o2 ! encoding: [0xd4,0x56,0x20,0x20]
ldsh [%i0 + 32], %o2
- ! CHECK: ldsh [%g1], %o4 ! encoding: [0xd8,0x50,0x60,0x00]
+ ! CHECK: ldsh [%g1], %o4 ! encoding: [0xd8,0x50,0x40,0x00]
ldsh [%g1], %o4
! CHECK: ldub [%i0+%l6], %o2 ! encoding: [0xd4,0x0e,0x00,0x16]
ldub [%i0 + %l6], %o2
! CHECK: ldub [%i0+32], %o2 ! encoding: [0xd4,0x0e,0x20,0x20]
ldub [%i0 + 32], %o2
- ! CHECK: ldub [%g1], %o2 ! encoding: [0xd4,0x08,0x60,0x00]
+ ! CHECK: ldub [%g1], %o2 ! encoding: [0xd4,0x08,0x40,0x00]
ldub [%g1], %o2
! CHECK: lduh [%i0+%l6], %o2 ! encoding: [0xd4,0x16,0x00,0x16]
lduh [%i0 + %l6], %o2
! CHECK: lduh [%i0+32], %o2 ! encoding: [0xd4,0x16,0x20,0x20]
lduh [%i0 + 32], %o2
- ! CHECK: lduh [%g1], %o2 ! encoding: [0xd4,0x10,0x60,0x00]
+ ! CHECK: lduh [%g1], %o2 ! encoding: [0xd4,0x10,0x40,0x00]
lduh [%g1], %o2
! CHECK: ld [%i0+%l6], %o2 ! encoding: [0xd4,0x06,0x00,0x16]
ld [%i0 + %l6], %o2
! CHECK: ld [%i0+32], %o2 ! encoding: [0xd4,0x06,0x20,0x20]
ld [%i0 + 32], %o2
- ! CHECK: ld [%g1], %o2 ! encoding: [0xd4,0x00,0x60,0x00]
+ ! CHECK: ld [%g1], %o2 ! encoding: [0xd4,0x00,0x40,0x00]
ld [%g1], %o2
! CHECK: stb %o2, [%i0+%l6] ! encoding: [0xd4,0x2e,0x00,0x16]
stb %o2, [%i0 + %l6]
! CHECK: stb %o2, [%i0+32] ! encoding: [0xd4,0x2e,0x20,0x20]
stb %o2, [%i0 + 32]
- ! CHECK: stb %o2, [%g1] ! encoding: [0xd4,0x28,0x60,0x00]
+ ! CHECK: stb %o2, [%g1] ! encoding: [0xd4,0x28,0x40,0x00]
stb %o2, [%g1]
! CHECK: sth %o2, [%i0+%l6] ! encoding: [0xd4,0x36,0x00,0x16]
sth %o2, [%i0 + %l6]
! CHECK: sth %o2, [%i0+32] ! encoding: [0xd4,0x36,0x20,0x20]
sth %o2, [%i0 + 32]
- ! CHECK: sth %o2, [%g1] ! encoding: [0xd4,0x30,0x60,0x00]
+ ! CHECK: sth %o2, [%g1] ! encoding: [0xd4,0x30,0x40,0x00]
sth %o2, [%g1]
! CHECK: st %o2, [%i0+%l6] ! encoding: [0xd4,0x26,0x00,0x16]
st %o2, [%i0 + %l6]
! CHECK: st %o2, [%i0+32] ! encoding: [0xd4,0x26,0x20,0x20]
st %o2, [%i0 + 32]
- ! CHECK: st %o2, [%g1] ! encoding: [0xd4,0x20,0x60,0x00]
+ ! CHECK: st %o2, [%g1] ! encoding: [0xd4,0x20,0x40,0x00]
st %o2, [%g1]
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