[llvm] r235977 - [DebugInfo] Add debug locations to constant SD nodes
Daniel Jasper
djasper at google.com
Tue Apr 28 06:28:24 PDT 2015
This breaks test/DebugInfo/constant-sdnodes-have-dbg-location.ll (
http://bb.pgr.jp/builders/cmake-llvm-x86_64-linux/builds/23870). Do you
have a quick fix? Otherwise I'll roll this back.
On Tue, Apr 28, 2015 at 1:56 PM, Sergey Dmitrouk <sdmitrouk at accesssoftek.com
> wrote:
> Modified: llvm/trunk/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp?rev=235977&r1=235976&r2=235977&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp (original)
> +++ llvm/trunk/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp Tue Apr 28
> 06:56:37 2015
> @@ -131,7 +131,7 @@ class SystemZDAGToDAGISel : public Selec
>
> // Used by SystemZOperands.td to create integer constants.
> inline SDValue getImm(const SDNode *Node, uint64_t Imm) const {
> - return CurDAG->getTargetConstant(Imm, Node->getValueType(0));
> + return CurDAG->getTargetConstant(Imm, SDLoc(Node),
> Node->getValueType(0));
> }
>
> const SystemZTargetMachine &getTargetMachine() const {
> @@ -596,7 +596,7 @@ void SystemZDAGToDAGISel::getAddressOper
> }
>
> // Lower the displacement to a TargetConstant.
> - Disp = CurDAG->getTargetConstant(AM.Disp, VT);
> + Disp = CurDAG->getTargetConstant(AM.Disp, SDLoc(Base), VT);
> }
>
> void SystemZDAGToDAGISel::getAddressOperands(const SystemZAddressingMode
> &AM,
> @@ -864,6 +864,7 @@ SDValue SystemZDAGToDAGISel::convertTo(S
> }
>
> SDNode *SystemZDAGToDAGISel::tryRISBGZero(SDNode *N) {
> + SDLoc DL(N);
> EVT VT = N->getValueType(0);
> RxSBGOperands RISBG(SystemZ::RISBG, SDValue(N, 0));
> unsigned Count = 0;
> @@ -889,7 +890,7 @@ SDNode *SystemZDAGToDAGISel::tryRISBGZer
> // Force the new mask into the DAG, since it may include known-one
> bits.
> auto *MaskN = cast<ConstantSDNode>(N->getOperand(1).getNode());
> if (MaskN->getZExtValue() != RISBG.Mask) {
> - SDValue NewMask = CurDAG->getConstant(RISBG.Mask, VT);
> + SDValue NewMask = CurDAG->getConstant(RISBG.Mask, DL, VT);
> N = CurDAG->UpdateNodeOperands(N, N->getOperand(0), NewMask);
> return SelectCode(N);
> }
> @@ -909,14 +910,14 @@ SDNode *SystemZDAGToDAGISel::tryRISBGZer
> RISBG.End &= 31;
> }
> SDValue Ops[5] = {
> - getUNDEF(SDLoc(N), OpcodeVT),
> - convertTo(SDLoc(N), OpcodeVT, RISBG.Input),
> - CurDAG->getTargetConstant(RISBG.Start, MVT::i32),
> - CurDAG->getTargetConstant(RISBG.End | 128, MVT::i32),
> - CurDAG->getTargetConstant(RISBG.Rotate, MVT::i32)
> + getUNDEF(DL, OpcodeVT),
> + convertTo(DL, OpcodeVT, RISBG.Input),
> + CurDAG->getTargetConstant(RISBG.Start, DL, MVT::i32),
> + CurDAG->getTargetConstant(RISBG.End | 128, DL, MVT::i32),
> + CurDAG->getTargetConstant(RISBG.Rotate, DL, MVT::i32)
> };
> - N = CurDAG->getMachineNode(Opcode, SDLoc(N), OpcodeVT, Ops);
> - return convertTo(SDLoc(N), VT, SDValue(N, 0)).getNode();
> + N = CurDAG->getMachineNode(Opcode, DL, OpcodeVT, Ops);
> + return convertTo(DL, VT, SDValue(N, 0)).getNode();
> }
>
> SDNode *SystemZDAGToDAGISel::tryRxSBG(SDNode *N, unsigned Opcode) {
> @@ -955,16 +956,17 @@ SDNode *SystemZDAGToDAGISel::tryRxSBG(SD
> Opcode = SystemZ::RISBGN;
> }
>
> + SDLoc DL(N);
> EVT VT = N->getValueType(0);
> SDValue Ops[5] = {
> - convertTo(SDLoc(N), MVT::i64, Op0),
> - convertTo(SDLoc(N), MVT::i64, RxSBG[I].Input),
> - CurDAG->getTargetConstant(RxSBG[I].Start, MVT::i32),
> - CurDAG->getTargetConstant(RxSBG[I].End, MVT::i32),
> - CurDAG->getTargetConstant(RxSBG[I].Rotate, MVT::i32)
> + convertTo(DL, MVT::i64, Op0),
> + convertTo(DL, MVT::i64, RxSBG[I].Input),
> + CurDAG->getTargetConstant(RxSBG[I].Start, DL, MVT::i32),
> + CurDAG->getTargetConstant(RxSBG[I].End, DL, MVT::i32),
> + CurDAG->getTargetConstant(RxSBG[I].Rotate, DL, MVT::i32)
> };
> - N = CurDAG->getMachineNode(Opcode, SDLoc(N), MVT::i64, Ops);
> - return convertTo(SDLoc(N), VT, SDValue(N, 0)).getNode();
> + N = CurDAG->getMachineNode(Opcode, DL, MVT::i64, Ops);
> + return convertTo(DL, VT, SDValue(N, 0)).getNode();
> }
>
> SDNode *SystemZDAGToDAGISel::splitLargeImmediate(unsigned Opcode, SDNode
> *Node,
> @@ -972,12 +974,12 @@ SDNode *SystemZDAGToDAGISel::splitLargeI
> uint64_t LowerVal) {
> EVT VT = Node->getValueType(0);
> SDLoc DL(Node);
> - SDValue Upper = CurDAG->getConstant(UpperVal, VT);
> + SDValue Upper = CurDAG->getConstant(UpperVal, DL, VT);
> if (Op0.getNode())
> Upper = CurDAG->getNode(Opcode, DL, VT, Op0, Upper);
> Upper = SDValue(Select(Upper.getNode()), 0);
>
> - SDValue Lower = CurDAG->getConstant(LowerVal, VT);
> + SDValue Lower = CurDAG->getConstant(LowerVal, DL, VT);
> SDValue Or = CurDAG->getNode(Opcode, DL, VT, Upper, Lower);
> return Or.getNode();
> }
> @@ -1111,7 +1113,7 @@ SDNode *SystemZDAGToDAGISel::Select(SDNo
> uint64_t ConstCCMask =
> cast<ConstantSDNode>(CCMask.getNode())->getZExtValue();
> // Invert the condition.
> - CCMask = CurDAG->getConstant(ConstCCValid ^ ConstCCMask,
> + CCMask = CurDAG->getConstant(ConstCCValid ^ ConstCCMask,
> SDLoc(Node),
> CCMask.getValueType());
> SDValue Op4 = Node->getOperand(4);
> Node = CurDAG->UpdateNodeOperands(Node, Op1, Op0, CCValid, CCMask,
> Op4);
>
> Modified: llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp?rev=235977&r1=235976&r2=235977&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp Tue Apr 28
> 06:56:37 2015
> @@ -591,35 +591,35 @@ LowerAsmOperandForConstraint(SDValue Op,
> case 'I': // Unsigned 8-bit constant
> if (auto *C = dyn_cast<ConstantSDNode>(Op))
> if (isUInt<8>(C->getZExtValue()))
> - Ops.push_back(DAG.getTargetConstant(C->getZExtValue(),
> + Ops.push_back(DAG.getTargetConstant(C->getZExtValue(),
> SDLoc(Op),
> Op.getValueType()));
> return;
>
> case 'J': // Unsigned 12-bit constant
> if (auto *C = dyn_cast<ConstantSDNode>(Op))
> if (isUInt<12>(C->getZExtValue()))
> - Ops.push_back(DAG.getTargetConstant(C->getZExtValue(),
> + Ops.push_back(DAG.getTargetConstant(C->getZExtValue(),
> SDLoc(Op),
> Op.getValueType()));
> return;
>
> case 'K': // Signed 16-bit constant
> if (auto *C = dyn_cast<ConstantSDNode>(Op))
> if (isInt<16>(C->getSExtValue()))
> - Ops.push_back(DAG.getTargetConstant(C->getSExtValue(),
> + Ops.push_back(DAG.getTargetConstant(C->getSExtValue(),
> SDLoc(Op),
> Op.getValueType()));
> return;
>
> case 'L': // Signed 20-bit displacement (on all targets we support)
> if (auto *C = dyn_cast<ConstantSDNode>(Op))
> if (isInt<20>(C->getSExtValue()))
> - Ops.push_back(DAG.getTargetConstant(C->getSExtValue(),
> + Ops.push_back(DAG.getTargetConstant(C->getSExtValue(),
> SDLoc(Op),
> Op.getValueType()));
> return;
>
> case 'M': // 0x7fffffff
> if (auto *C = dyn_cast<ConstantSDNode>(Op))
> if (C->getZExtValue() == 0x7fffffff)
> - Ops.push_back(DAG.getTargetConstant(C->getZExtValue(),
> + Ops.push_back(DAG.getTargetConstant(C->getZExtValue(),
> SDLoc(Op),
> Op.getValueType()));
> return;
> }
> @@ -753,7 +753,8 @@ LowerFormalArguments(SDValue Chain, Call
> EVT PtrVT = getPointerTy();
> SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
> if (VA.getLocVT() == MVT::i32 || VA.getLocVT() == MVT::f32)
> - FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN,
> DAG.getIntPtrConstant(4));
> + FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN,
> + DAG.getIntPtrConstant(4, DL));
> ArgValue = DAG.getLoad(LocVT, DL, Chain, FIN,
> MachinePointerInfo::getFixedStack(FI),
> false, false, false, 0);
> @@ -854,7 +855,8 @@ SystemZTargetLowering::LowerCall(CallLow
>
> // Mark the start of the call.
> if (!IsTailCall)
> - Chain = DAG.getCALLSEQ_START(Chain, DAG.getConstant(NumBytes, PtrVT,
> true),
> + Chain = DAG.getCALLSEQ_START(Chain,
> + DAG.getConstant(NumBytes, DL, PtrVT,
> true),
> DL);
>
> // Copy argument values to their designated locations.
> @@ -890,7 +892,7 @@ SystemZTargetLowering::LowerCall(CallLow
> if (VA.getLocVT() == MVT::i32 || VA.getLocVT() == MVT::f32)
> Offset += 4;
> SDValue Address = DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr,
> - DAG.getIntPtrConstant(Offset));
> + DAG.getIntPtrConstant(Offset, DL));
>
> // Emit the store.
> MemOpChains.push_back(DAG.getStore(Chain, DL, ArgValue, Address,
> @@ -956,8 +958,8 @@ SystemZTargetLowering::LowerCall(CallLow
>
> // Mark the end of the call, which is glued to the call itself.
> Chain = DAG.getCALLSEQ_END(Chain,
> - DAG.getConstant(NumBytes, PtrVT, true),
> - DAG.getConstant(0, PtrVT, true),
> + DAG.getConstant(NumBytes, DL, PtrVT, true),
> + DAG.getConstant(0, DL, PtrVT, true),
> Glue, DL);
> Glue = Chain.getValue(1);
>
> @@ -1179,7 +1181,7 @@ static IPMConversion getIPMConversion(un
>
> // If C can be converted to a comparison against zero, adjust the operands
> // as necessary.
> -static void adjustZeroCmp(SelectionDAG &DAG, Comparison &C) {
> +static void adjustZeroCmp(SelectionDAG &DAG, SDLoc DL, Comparison &C) {
> if (C.ICmpType == SystemZICMP::UnsignedOnly)
> return;
>
> @@ -1193,13 +1195,13 @@ static void adjustZeroCmp(SelectionDAG &
> (Value == 1 && C.CCMask == SystemZ::CCMASK_CMP_LT) ||
> (Value == 1 && C.CCMask == SystemZ::CCMASK_CMP_GE)) {
> C.CCMask ^= SystemZ::CCMASK_CMP_EQ;
> - C.Op1 = DAG.getConstant(0, C.Op1.getValueType());
> + C.Op1 = DAG.getConstant(0, DL, C.Op1.getValueType());
> }
> }
>
> // If a comparison described by C is suitable for CLI(Y), CHHSI or CLHHSI,
> // adjust the operands as necessary.
> -static void adjustSubwordCmp(SelectionDAG &DAG, Comparison &C) {
> +static void adjustSubwordCmp(SelectionDAG &DAG, SDLoc DL, Comparison &C) {
> // For us to make any changes, it must a comparison between a single-use
> // load and a constant.
> if (!C.Op0.hasOneUse() ||
> @@ -1264,7 +1266,7 @@ static void adjustSubwordCmp(SelectionDA
> // Make sure that the second operand is an i32 with the right value.
> if (C.Op1.getValueType() != MVT::i32 ||
> Value != ConstOp1->getZExtValue())
> - C.Op1 = DAG.getConstant(Value, MVT::i32);
> + C.Op1 = DAG.getConstant(Value, DL, MVT::i32);
> }
>
> // Return true if Op is either an unextended load, or a load suitable
> @@ -1360,7 +1362,7 @@ static unsigned reverseCCMask(unsigned C
> // Check whether C tests for equality between X and Y and whether X - Y
> // or Y - X is also computed. In that case it's better to compare the
> // result of the subtraction against zero.
> -static void adjustForSubtraction(SelectionDAG &DAG, Comparison &C) {
> +static void adjustForSubtraction(SelectionDAG &DAG, SDLoc DL, Comparison
> &C) {
> if (C.CCMask == SystemZ::CCMASK_CMP_EQ ||
> C.CCMask == SystemZ::CCMASK_CMP_NE) {
> for (auto I = C.Op0->use_begin(), E = C.Op0->use_end(); I != E; ++I) {
> @@ -1369,7 +1371,7 @@ static void adjustForSubtraction(Selecti
> ((N->getOperand(0) == C.Op0 && N->getOperand(1) == C.Op1) ||
> (N->getOperand(0) == C.Op1 && N->getOperand(1) == C.Op0))) {
> C.Op0 = SDValue(N, 0);
> - C.Op1 = DAG.getConstant(0, N->getValueType(0));
> + C.Op1 = DAG.getConstant(0, DL, N->getValueType(0));
> return;
> }
> }
> @@ -1425,7 +1427,7 @@ static void adjustForLTGFR(Comparison &C
> // If C compares the truncation of an extending load, try to compare
> // the untruncated value instead. This exposes more opportunities to
> // reuse CC.
> -static void adjustICmpTruncate(SelectionDAG &DAG, Comparison &C) {
> +static void adjustICmpTruncate(SelectionDAG &DAG, SDLoc DL, Comparison
> &C) {
> if (C.Op0.getOpcode() == ISD::TRUNCATE &&
> C.Op0.getOperand(0).getOpcode() == ISD::LOAD &&
> C.Op1.getOpcode() == ISD::Constant &&
> @@ -1437,7 +1439,7 @@ static void adjustICmpTruncate(Selection
> if ((Type == ISD::ZEXTLOAD && C.ICmpType !=
> SystemZICMP::SignedOnly) ||
> (Type == ISD::SEXTLOAD && C.ICmpType !=
> SystemZICMP::UnsignedOnly)) {
> C.Op0 = C.Op0.getOperand(0);
> - C.Op1 = DAG.getConstant(0, C.Op0.getValueType());
> + C.Op1 = DAG.getConstant(0, DL, C.Op0.getValueType());
> }
> }
> }
> @@ -1556,7 +1558,7 @@ static unsigned getTestUnderMaskCond(uns
>
> // See whether C can be implemented as a TEST UNDER MASK instruction.
> // Update the arguments with the TM version if so.
> -static void adjustForTestUnderMask(SelectionDAG &DAG, Comparison &C) {
> +static void adjustForTestUnderMask(SelectionDAG &DAG, SDLoc DL,
> Comparison &C) {
> // Check that we have a comparison with a constant.
> auto *ConstOp1 = dyn_cast<ConstantSDNode>(C.Op1);
> if (!ConstOp1)
> @@ -1634,7 +1636,7 @@ static void adjustForTestUnderMask(Selec
> if (Mask && Mask->getZExtValue() == MaskVal)
> C.Op1 = SDValue(Mask, 0);
> else
> - C.Op1 = DAG.getConstant(MaskVal, C.Op0.getValueType());
> + C.Op1 = DAG.getConstant(MaskVal, DL, C.Op0.getValueType());
> C.CCValid = SystemZ::CCMASK_TM;
> C.CCMask = NewCCMask;
> }
> @@ -1677,7 +1679,7 @@ static Comparison getIntrinsicCmp(Select
>
> // Decide how to implement a comparison of type Cond between CmpOp0 with
> CmpOp1.
> static Comparison getCmp(SelectionDAG &DAG, SDValue CmpOp0, SDValue
> CmpOp1,
> - ISD::CondCode Cond) {
> + ISD::CondCode Cond, SDLoc DL) {
> if (CmpOp1.getOpcode() == ISD::Constant) {
> uint64_t Constant = cast<ConstantSDNode>(CmpOp1)->getZExtValue();
> unsigned Opcode, CCValid;
> @@ -1709,11 +1711,11 @@ static Comparison getCmp(SelectionDAG &D
> else
> C.ICmpType = SystemZICMP::SignedOnly;
> C.CCMask &= ~SystemZ::CCMASK_CMP_UO;
> - adjustZeroCmp(DAG, C);
> - adjustSubwordCmp(DAG, C);
> - adjustForSubtraction(DAG, C);
> + adjustZeroCmp(DAG, DL, C);
> + adjustSubwordCmp(DAG, DL, C);
> + adjustForSubtraction(DAG, DL, C);
> adjustForLTGFR(C);
> - adjustICmpTruncate(DAG, C);
> + adjustICmpTruncate(DAG, DL, C);
> }
>
> if (shouldSwapCmpOperands(C)) {
> @@ -1721,7 +1723,7 @@ static Comparison getCmp(SelectionDAG &D
> C.CCMask = reverseCCMask(C.CCMask);
> }
>
> - adjustForTestUnderMask(DAG, C);
> + adjustForTestUnderMask(DAG, DL, C);
> return C;
> }
>
> @@ -1740,12 +1742,12 @@ static SDValue emitCmp(SelectionDAG &DAG
> }
> if (C.Opcode == SystemZISD::ICMP)
> return DAG.getNode(SystemZISD::ICMP, DL, MVT::Glue, C.Op0, C.Op1,
> - DAG.getConstant(C.ICmpType, MVT::i32));
> + DAG.getConstant(C.ICmpType, DL, MVT::i32));
> if (C.Opcode == SystemZISD::TM) {
> bool RegisterOnly = (bool(C.CCMask & SystemZ::CCMASK_TM_MIXED_MSB_0)
> !=
> bool(C.CCMask & SystemZ::CCMASK_TM_MIXED_MSB_1));
> return DAG.getNode(SystemZISD::TM, DL, MVT::Glue, C.Op0, C.Op1,
> - DAG.getConstant(RegisterOnly, MVT::i32));
> + DAG.getConstant(RegisterOnly, DL, MVT::i32));
> }
> return DAG.getNode(C.Opcode, DL, MVT::Glue, C.Op0, C.Op1);
> }
> @@ -1759,7 +1761,8 @@ static void lowerMUL_LOHI32(SelectionDAG
> Op0 = DAG.getNode(Extend, DL, MVT::i64, Op0);
> Op1 = DAG.getNode(Extend, DL, MVT::i64, Op1);
> SDValue Mul = DAG.getNode(ISD::MUL, DL, MVT::i64, Op0, Op1);
> - Hi = DAG.getNode(ISD::SRL, DL, MVT::i64, Mul, DAG.getConstant(32,
> MVT::i64));
> + Hi = DAG.getNode(ISD::SRL, DL, MVT::i64, Mul,
> + DAG.getConstant(32, DL, MVT::i64));
> Hi = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Hi);
> Lo = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Mul);
> }
> @@ -1791,18 +1794,18 @@ static SDValue emitSETCC(SelectionDAG &D
>
> if (Conversion.XORValue)
> Result = DAG.getNode(ISD::XOR, DL, MVT::i32, Result,
> - DAG.getConstant(Conversion.XORValue, MVT::i32));
> + DAG.getConstant(Conversion.XORValue, DL,
> MVT::i32));
>
> if (Conversion.AddValue)
> Result = DAG.getNode(ISD::ADD, DL, MVT::i32, Result,
> - DAG.getConstant(Conversion.AddValue, MVT::i32));
> + DAG.getConstant(Conversion.AddValue, DL,
> MVT::i32));
>
> // The SHR/AND sequence should get optimized to an RISBG.
> Result = DAG.getNode(ISD::SRL, DL, MVT::i32, Result,
> - DAG.getConstant(Conversion.Bit, MVT::i32));
> + DAG.getConstant(Conversion.Bit, DL, MVT::i32));
> if (Conversion.Bit != 31)
> Result = DAG.getNode(ISD::AND, DL, MVT::i32, Result,
> - DAG.getConstant(1, MVT::i32));
> + DAG.getConstant(1, DL, MVT::i32));
> return Result;
> }
>
> @@ -1813,7 +1816,7 @@ SDValue SystemZTargetLowering::lowerSETC
> ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
> SDLoc DL(Op);
>
> - Comparison C(getCmp(DAG, CmpOp0, CmpOp1, CC));
> + Comparison C(getCmp(DAG, CmpOp0, CmpOp1, CC, DL));
> SDValue Glue = emitCmp(DAG, DL, C);
> return emitSETCC(DAG, DL, Glue, C.CCValid, C.CCMask);
> }
> @@ -1825,11 +1828,11 @@ SDValue SystemZTargetLowering::lowerBR_C
> SDValue Dest = Op.getOperand(4);
> SDLoc DL(Op);
>
> - Comparison C(getCmp(DAG, CmpOp0, CmpOp1, CC));
> + Comparison C(getCmp(DAG, CmpOp0, CmpOp1, CC, DL));
> SDValue Glue = emitCmp(DAG, DL, C);
> return DAG.getNode(SystemZISD::BR_CCMASK, DL, Op.getValueType(),
> - Op.getOperand(0), DAG.getConstant(C.CCValid,
> MVT::i32),
> - DAG.getConstant(C.CCMask, MVT::i32), Dest, Glue);
> + Op.getOperand(0), DAG.getConstant(C.CCValid, DL,
> MVT::i32),
> + DAG.getConstant(C.CCMask, DL, MVT::i32), Dest, Glue);
> }
>
> // Return true if Pos is CmpOp and Neg is the negative of CmpOp,
> @@ -1850,7 +1853,7 @@ static SDValue getAbsolute(SelectionDAG
> Op = DAG.getNode(SystemZISD::IABS, DL, Op.getValueType(), Op);
> if (IsNegative)
> Op = DAG.getNode(ISD::SUB, DL, Op.getValueType(),
> - DAG.getConstant(0, Op.getValueType()), Op);
> + DAG.getConstant(0, DL, Op.getValueType()), Op);
> return Op;
> }
>
> @@ -1863,7 +1866,7 @@ SDValue SystemZTargetLowering::lowerSELE
> ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
> SDLoc DL(Op);
>
> - Comparison C(getCmp(DAG, CmpOp0, CmpOp1, CC));
> + Comparison C(getCmp(DAG, CmpOp0, CmpOp1, CC, DL));
>
> // Check for absolute and negative-absolute selections, including those
> // where the comparison value is sign-extended (for LPGFR and LNGFR).
> @@ -1898,14 +1901,14 @@ SDValue SystemZTargetLowering::lowerSELE
> if (!is32Bit(VT))
> Result = DAG.getNode(ISD::ANY_EXTEND, DL, VT, Result);
> // Sign-extend from the low bit.
> - SDValue ShAmt = DAG.getConstant(VT.getSizeInBits() - 1, MVT::i32);
> + SDValue ShAmt = DAG.getConstant(VT.getSizeInBits() - 1, DL,
> MVT::i32);
> SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, Result, ShAmt);
> return DAG.getNode(ISD::SRA, DL, VT, Shl, ShAmt);
> }
> }
>
> - SDValue Ops[] = {TrueOp, FalseOp, DAG.getConstant(C.CCValid, MVT::i32),
> - DAG.getConstant(C.CCMask, MVT::i32), Glue};
> + SDValue Ops[] = {TrueOp, FalseOp, DAG.getConstant(C.CCValid, DL,
> MVT::i32),
> + DAG.getConstant(C.CCMask, DL, MVT::i32), Glue};
>
> SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
> return DAG.getNode(SystemZISD::SELECT_CCMASK, DL, VTs, Ops);
> @@ -1945,7 +1948,7 @@ SDValue SystemZTargetLowering::lowerGlob
> // addition for it.
> if (Offset != 0)
> Result = DAG.getNode(ISD::ADD, DL, PtrVT, Result,
> - DAG.getConstant(Offset, PtrVT));
> + DAG.getConstant(Offset, DL, PtrVT));
>
> return Result;
> }
> @@ -2006,17 +2009,17 @@ SDValue SystemZTargetLowering::lowerGlob
>
> // The high part of the thread pointer is in access register 0.
> SDValue TPHi = DAG.getNode(SystemZISD::EXTRACT_ACCESS, DL, MVT::i32,
> - DAG.getConstant(0, MVT::i32));
> + DAG.getConstant(0, DL, MVT::i32));
> TPHi = DAG.getNode(ISD::ANY_EXTEND, DL, PtrVT, TPHi);
>
> // The low part of the thread pointer is in access register 1.
> SDValue TPLo = DAG.getNode(SystemZISD::EXTRACT_ACCESS, DL, MVT::i32,
> - DAG.getConstant(1, MVT::i32));
> + DAG.getConstant(1, DL, MVT::i32));
> TPLo = DAG.getNode(ISD::ZERO_EXTEND, DL, PtrVT, TPLo);
>
> // Merge them into a single 64-bit address.
> SDValue TPHiShifted = DAG.getNode(ISD::SHL, DL, PtrVT, TPHi,
> - DAG.getConstant(32, PtrVT));
> + DAG.getConstant(32, DL, PtrVT));
> SDValue TP = DAG.getNode(ISD::OR, DL, PtrVT, TPHiShifted, TPLo);
>
> // Get the offset of GA from the thread pointer, based on the TLS model.
> @@ -2153,7 +2156,7 @@ SDValue SystemZTargetLowering::lowerBITC
> } else {
> In64 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, In);
> In64 = DAG.getNode(ISD::SHL, DL, MVT::i64, In64,
> - DAG.getConstant(32, MVT::i64));
> + DAG.getConstant(32, DL, MVT::i64));
> }
> SDValue Out64 = DAG.getNode(ISD::BITCAST, DL, MVT::f64, In64);
> return DAG.getTargetExtractSubreg(SystemZ::subreg_h32,
> @@ -2168,7 +2171,7 @@ SDValue SystemZTargetLowering::lowerBITC
> return DAG.getTargetExtractSubreg(SystemZ::subreg_h32, DL,
> MVT::i32, Out64);
> SDValue Shift = DAG.getNode(ISD::SRL, DL, MVT::i64, Out64,
> - DAG.getConstant(32, MVT::i64));
> + DAG.getConstant(32, DL, MVT::i64));
> return DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Shift);
> }
> llvm_unreachable("Unexpected bitcast combination");
> @@ -2189,8 +2192,8 @@ SDValue SystemZTargetLowering::lowerVAST
> // The initial values of each field.
> const unsigned NumFields = 4;
> SDValue Fields[NumFields] = {
> - DAG.getConstant(FuncInfo->getVarArgsFirstGPR(), PtrVT),
> - DAG.getConstant(FuncInfo->getVarArgsFirstFPR(), PtrVT),
> + DAG.getConstant(FuncInfo->getVarArgsFirstGPR(), DL, PtrVT),
> + DAG.getConstant(FuncInfo->getVarArgsFirstFPR(), DL, PtrVT),
> DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT),
> DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), PtrVT)
> };
> @@ -2202,7 +2205,7 @@ SDValue SystemZTargetLowering::lowerVAST
> SDValue FieldAddr = Addr;
> if (Offset != 0)
> FieldAddr = DAG.getNode(ISD::ADD, DL, PtrVT, FieldAddr,
> - DAG.getIntPtrConstant(Offset));
> + DAG.getIntPtrConstant(Offset, DL));
> MemOps[I] = DAG.getStore(Chain, DL, Fields[I], FieldAddr,
> MachinePointerInfo(SV, Offset),
> false, false, 0);
> @@ -2220,7 +2223,7 @@ SDValue SystemZTargetLowering::lowerVACO
> const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
> SDLoc DL(Op);
>
> - return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
> DAG.getIntPtrConstant(32),
> + return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
> DAG.getIntPtrConstant(32, DL),
> /*Align*/8, /*isVolatile*/false,
> /*AlwaysInline*/false,
> /*isTailCall*/false,
> MachinePointerInfo(DstSV),
> MachinePointerInfo(SrcSV));
> @@ -2277,7 +2280,7 @@ SDValue SystemZTargetLowering::lowerSMUL
> // multiplication:
> //
> // (ll * rl) - (((lh & rl) + (ll & rh)) << 64)
> - SDValue C63 = DAG.getConstant(63, MVT::i64);
> + SDValue C63 = DAG.getConstant(63, DL, MVT::i64);
> SDValue LL = Op.getOperand(0);
> SDValue RL = Op.getOperand(1);
> SDValue LH = DAG.getNode(ISD::SRA, DL, VT, LL, C63);
> @@ -2427,7 +2430,7 @@ SDValue SystemZTargetLowering::lowerCTPO
> DAG.computeKnownBits(Op, KnownZero, KnownOne);
> unsigned NumSignificantBits = (~KnownZero).getActiveBits();
> if (NumSignificantBits == 0)
> - return DAG.getConstant(0, VT);
> + return DAG.getConstant(0, DL, VT);
>
> // Skip known-zero high parts of the operand.
> int64_t BitSize = (int64_t)1 << Log2_32_Ceil(NumSignificantBits);
> @@ -2441,16 +2444,17 @@ SDValue SystemZTargetLowering::lowerCTPO
> // Add up per-byte counts in a binary tree. All bits of Op at
> // position larger than BitSize remain zero throughout.
> for (int64_t I = BitSize / 2; I >= 8; I = I / 2) {
> - SDValue Tmp = DAG.getNode(ISD::SHL, DL, VT, Op, DAG.getConstant(I,
> VT));
> + SDValue Tmp = DAG.getNode(ISD::SHL, DL, VT, Op, DAG.getConstant(I,
> DL, VT));
> if (BitSize != OrigBitSize)
> Tmp = DAG.getNode(ISD::AND, DL, VT, Tmp,
> - DAG.getConstant(((uint64_t)1 << BitSize) - 1,
> VT));
> + DAG.getConstant(((uint64_t)1 << BitSize) - 1, DL,
> VT));
> Op = DAG.getNode(ISD::ADD, DL, VT, Op, Tmp);
> }
>
> // Extract overall result from high byte.
> if (BitSize > 8)
> - Op = DAG.getNode(ISD::SRL, DL, VT, Op, DAG.getConstant(BitSize - 8,
> VT));
> + Op = DAG.getNode(ISD::SRL, DL, VT, Op,
> + DAG.getConstant(BitSize - 8, DL, VT));
>
> return Op;
> }
> @@ -2501,23 +2505,23 @@ SDValue SystemZTargetLowering::lowerATOM
> if (Opcode == SystemZISD::ATOMIC_LOADW_SUB)
> if (auto *Const = dyn_cast<ConstantSDNode>(Src2)) {
> Opcode = SystemZISD::ATOMIC_LOADW_ADD;
> - Src2 = DAG.getConstant(-Const->getSExtValue(), Src2.getValueType());
> + Src2 = DAG.getConstant(-Const->getSExtValue(), DL,
> Src2.getValueType());
> }
>
> // Get the address of the containing word.
> SDValue AlignedAddr = DAG.getNode(ISD::AND, DL, PtrVT, Addr,
> - DAG.getConstant(-4, PtrVT));
> + DAG.getConstant(-4, DL, PtrVT));
>
> // Get the number of bits that the word must be rotated left in order
> // to bring the field to the top bits of a GR32.
> SDValue BitShift = DAG.getNode(ISD::SHL, DL, PtrVT, Addr,
> - DAG.getConstant(3, PtrVT));
> + DAG.getConstant(3, DL, PtrVT));
> BitShift = DAG.getNode(ISD::TRUNCATE, DL, WideVT, BitShift);
>
> // Get the complementing shift amount, for rotating a field in the top
> // bits back to its proper position.
> SDValue NegBitShift = DAG.getNode(ISD::SUB, DL, WideVT,
> - DAG.getConstant(0, WideVT), BitShift);
> + DAG.getConstant(0, DL, WideVT),
> BitShift);
>
> // Extend the source operand to 32 bits and prepare it for the inner
> loop.
> // ATOMIC_SWAPW uses RISBG to rotate the field left, but all other
> @@ -2526,23 +2530,23 @@ SDValue SystemZTargetLowering::lowerATOM
> // bits must be set, while for other opcodes they should be left clear.
> if (Opcode != SystemZISD::ATOMIC_SWAPW)
> Src2 = DAG.getNode(ISD::SHL, DL, WideVT, Src2,
> - DAG.getConstant(32 - BitSize, WideVT));
> + DAG.getConstant(32 - BitSize, DL, WideVT));
> if (Opcode == SystemZISD::ATOMIC_LOADW_AND ||
> Opcode == SystemZISD::ATOMIC_LOADW_NAND)
> Src2 = DAG.getNode(ISD::OR, DL, WideVT, Src2,
> - DAG.getConstant(uint32_t(-1) >> BitSize, WideVT));
> + DAG.getConstant(uint32_t(-1) >> BitSize, DL,
> WideVT));
>
> // Construct the ATOMIC_LOADW_* node.
> SDVTList VTList = DAG.getVTList(WideVT, MVT::Other);
> SDValue Ops[] = { ChainIn, AlignedAddr, Src2, BitShift, NegBitShift,
> - DAG.getConstant(BitSize, WideVT) };
> + DAG.getConstant(BitSize, DL, WideVT) };
> SDValue AtomicOp = DAG.getMemIntrinsicNode(Opcode, DL, VTList, Ops,
> NarrowVT, MMO);
>
> // Rotate the result of the final CS so that the field is in the lower
> // bits of a GR32, then truncate it.
> SDValue ResultShift = DAG.getNode(ISD::ADD, DL, WideVT, BitShift,
> - DAG.getConstant(BitSize, WideVT));
> + DAG.getConstant(BitSize, DL, WideVT));
> SDValue Result = DAG.getNode(ISD::ROTL, DL, WideVT, AtomicOp,
> ResultShift);
>
> SDValue RetOps[2] = { Result, AtomicOp.getValue(1) };
> @@ -2568,10 +2572,10 @@ SDValue SystemZTargetLowering::lowerATOM
> // available or the negative value is in the range of A(G)FHI.
> int64_t Value = (-Op2->getAPIntValue()).getSExtValue();
> if (isInt<32>(Value) || Subtarget.hasInterlockedAccess1())
> - NegSrc2 = DAG.getConstant(Value, MemVT);
> + NegSrc2 = DAG.getConstant(Value, DL, MemVT);
> } else if (Subtarget.hasInterlockedAccess1())
> // Use LAA(G) if available.
> - NegSrc2 = DAG.getNode(ISD::SUB, DL, MemVT, DAG.getConstant(0,
> MemVT),
> + NegSrc2 = DAG.getNode(ISD::SUB, DL, MemVT, DAG.getConstant(0, DL,
> MemVT),
> Src2);
>
> if (NegSrc2.getNode())
> @@ -2610,23 +2614,23 @@ SDValue SystemZTargetLowering::lowerATOM
>
> // Get the address of the containing word.
> SDValue AlignedAddr = DAG.getNode(ISD::AND, DL, PtrVT, Addr,
> - DAG.getConstant(-4, PtrVT));
> + DAG.getConstant(-4, DL, PtrVT));
>
> // Get the number of bits that the word must be rotated left in order
> // to bring the field to the top bits of a GR32.
> SDValue BitShift = DAG.getNode(ISD::SHL, DL, PtrVT, Addr,
> - DAG.getConstant(3, PtrVT));
> + DAG.getConstant(3, DL, PtrVT));
> BitShift = DAG.getNode(ISD::TRUNCATE, DL, WideVT, BitShift);
>
> // Get the complementing shift amount, for rotating a field in the top
> // bits back to its proper position.
> SDValue NegBitShift = DAG.getNode(ISD::SUB, DL, WideVT,
> - DAG.getConstant(0, WideVT), BitShift);
> + DAG.getConstant(0, DL, WideVT),
> BitShift);
>
> // Construct the ATOMIC_CMP_SWAPW node.
> SDVTList VTList = DAG.getVTList(WideVT, MVT::Other);
> SDValue Ops[] = { ChainIn, AlignedAddr, CmpVal, SwapVal, BitShift,
> - NegBitShift, DAG.getConstant(BitSize, WideVT) };
> + NegBitShift, DAG.getConstant(BitSize, DL, WideVT) };
> SDValue AtomicOp =
> DAG.getMemIntrinsicNode(SystemZISD::ATOMIC_CMP_SWAPW, DL,
> VTList, Ops, NarrowVT, MMO);
> return AtomicOp;
> @@ -2655,15 +2659,16 @@ SDValue SystemZTargetLowering::lowerPREF
> // Just preserve the chain.
> return Op.getOperand(0);
>
> + SDLoc DL(Op);
> bool IsWrite = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
> unsigned Code = IsWrite ? SystemZ::PFD_WRITE : SystemZ::PFD_READ;
> auto *Node = cast<MemIntrinsicSDNode>(Op.getNode());
> SDValue Ops[] = {
> Op.getOperand(0),
> - DAG.getConstant(Code, MVT::i32),
> + DAG.getConstant(Code, DL, MVT::i32),
> Op.getOperand(1)
> };
> - return DAG.getMemIntrinsicNode(SystemZISD::PREFETCH, SDLoc(Op),
> + return DAG.getMemIntrinsicNode(SystemZISD::PREFETCH, DL,
> Node->getVTList(), Ops,
> Node->getMemoryVT(),
> Node->getMemOperand());
> }
> @@ -2671,10 +2676,11 @@ SDValue SystemZTargetLowering::lowerPREF
> // Return an i32 that contains the value of CC immediately after After,
> // whose final operand must be MVT::Glue.
> static SDValue getCCResult(SelectionDAG &DAG, SDNode *After) {
> + SDLoc DL(After);
> SDValue Glue = SDValue(After, After->getNumValues() - 1);
> - SDValue IPM = DAG.getNode(SystemZISD::IPM, SDLoc(After), MVT::i32,
> Glue);
> - return DAG.getNode(ISD::SRL, SDLoc(After), MVT::i32, IPM,
> - DAG.getConstant(SystemZ::IPM_CC, MVT::i32));
> + SDValue IPM = DAG.getNode(SystemZISD::IPM, DL, MVT::i32, Glue);
> + return DAG.getNode(ISD::SRL, DL, MVT::i32, IPM,
> + DAG.getConstant(SystemZ::IPM_CC, DL, MVT::i32));
> }
>
> SDValue
> @@ -2851,9 +2857,10 @@ SDValue SystemZTargetLowering::PerformDA
> SDValue Ext = DAG.getNode(ISD::ANY_EXTEND, SDLoc(Inner), VT,
> Inner.getOperand(0));
> SDValue Shl = DAG.getNode(ISD::SHL, SDLoc(Inner), VT, Ext,
> - DAG.getConstant(NewShlAmt, ShiftVT));
> + DAG.getConstant(NewShlAmt,
> SDLoc(Inner),
> + ShiftVT));
> return DAG.getNode(ISD::SRA, SDLoc(N0), VT, Shl,
> - DAG.getConstant(NewSraAmt, ShiftVT));
> + DAG.getConstant(NewSraAmt, SDLoc(N0),
> ShiftVT));
> }
> }
> }
>
> Modified: llvm/trunk/lib/Target/SystemZ/SystemZOperands.td
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZOperands.td?rev=235977&r1=235976&r2=235977&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/SystemZ/SystemZOperands.td (original)
> +++ llvm/trunk/lib/Target/SystemZ/SystemZOperands.td Tue Apr 28 06:56:37
> 2015
> @@ -134,72 +134,79 @@ class BDLMode<string type, string bitsiz
> // Bits 0-15 (counting from the lsb).
> def LL16 : SDNodeXForm<imm, [{
> uint64_t Value = N->getZExtValue() & 0x000000000000FFFFULL;
> - return CurDAG->getTargetConstant(Value, MVT::i64);
> + return CurDAG->getTargetConstant(Value, SDLoc(N), MVT::i64);
> }]>;
>
> // Bits 16-31 (counting from the lsb).
> def LH16 : SDNodeXForm<imm, [{
> uint64_t Value = (N->getZExtValue() & 0x00000000FFFF0000ULL) >> 16;
> - return CurDAG->getTargetConstant(Value, MVT::i64);
> + return CurDAG->getTargetConstant(Value, SDLoc(N), MVT::i64);
> }]>;
>
> // Bits 32-47 (counting from the lsb).
> def HL16 : SDNodeXForm<imm, [{
> uint64_t Value = (N->getZExtValue() & 0x0000FFFF00000000ULL) >> 32;
> - return CurDAG->getTargetConstant(Value, MVT::i64);
> + return CurDAG->getTargetConstant(Value, SDLoc(N), MVT::i64);
> }]>;
>
> // Bits 48-63 (counting from the lsb).
> def HH16 : SDNodeXForm<imm, [{
> uint64_t Value = (N->getZExtValue() & 0xFFFF000000000000ULL) >> 48;
> - return CurDAG->getTargetConstant(Value, MVT::i64);
> + return CurDAG->getTargetConstant(Value, SDLoc(N), MVT::i64);
> }]>;
>
> // Low 32 bits.
> def LF32 : SDNodeXForm<imm, [{
> uint64_t Value = N->getZExtValue() & 0x00000000FFFFFFFFULL;
> - return CurDAG->getTargetConstant(Value, MVT::i64);
> + return CurDAG->getTargetConstant(Value, SDLoc(N), MVT::i64);
> }]>;
>
> // High 32 bits.
> def HF32 : SDNodeXForm<imm, [{
> uint64_t Value = N->getZExtValue() >> 32;
> - return CurDAG->getTargetConstant(Value, MVT::i64);
> + return CurDAG->getTargetConstant(Value, SDLoc(N), MVT::i64);
> }]>;
>
> // Truncate an immediate to a 8-bit signed quantity.
> def SIMM8 : SDNodeXForm<imm, [{
> - return CurDAG->getTargetConstant(int8_t(N->getZExtValue()), MVT::i64);
> + return CurDAG->getTargetConstant(int8_t(N->getZExtValue()), SDLoc(N),
> + MVT::i64);
> }]>;
>
> // Truncate an immediate to a 8-bit unsigned quantity.
> def UIMM8 : SDNodeXForm<imm, [{
> - return CurDAG->getTargetConstant(uint8_t(N->getZExtValue()), MVT::i64);
> + return CurDAG->getTargetConstant(uint8_t(N->getZExtValue()), SDLoc(N),
> + MVT::i64);
> }]>;
>
> // Truncate an immediate to a 16-bit signed quantity.
> def SIMM16 : SDNodeXForm<imm, [{
> - return CurDAG->getTargetConstant(int16_t(N->getZExtValue()), MVT::i64);
> + return CurDAG->getTargetConstant(int16_t(N->getZExtValue()), SDLoc(N),
> + MVT::i64);
> }]>;
>
> // Truncate an immediate to a 16-bit unsigned quantity.
> def UIMM16 : SDNodeXForm<imm, [{
> - return CurDAG->getTargetConstant(uint16_t(N->getZExtValue()), MVT::i64);
> + return CurDAG->getTargetConstant(uint16_t(N->getZExtValue()), SDLoc(N),
> + MVT::i64);
> }]>;
>
> // Truncate an immediate to a 32-bit signed quantity.
> def SIMM32 : SDNodeXForm<imm, [{
> - return CurDAG->getTargetConstant(int32_t(N->getZExtValue()), MVT::i64);
> + return CurDAG->getTargetConstant(int32_t(N->getZExtValue()), SDLoc(N),
> + MVT::i64);
> }]>;
>
> // Truncate an immediate to a 32-bit unsigned quantity.
> def UIMM32 : SDNodeXForm<imm, [{
> - return CurDAG->getTargetConstant(uint32_t(N->getZExtValue()), MVT::i64);
> + return CurDAG->getTargetConstant(uint32_t(N->getZExtValue()), SDLoc(N),
> + MVT::i64);
> }]>;
>
> // Negate and then truncate an immediate to a 32-bit unsigned quantity.
> def NEGIMM32 : SDNodeXForm<imm, [{
> - return CurDAG->getTargetConstant(uint32_t(-N->getZExtValue()),
> MVT::i64);
> + return CurDAG->getTargetConstant(uint32_t(-N->getZExtValue()), SDLoc(N),
> + MVT::i64);
> }]>;
>
>
> //===----------------------------------------------------------------------===//
>
> Modified: llvm/trunk/lib/Target/SystemZ/SystemZSelectionDAGInfo.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZSelectionDAGInfo.cpp?rev=235977&r1=235976&r2=235977&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/SystemZ/SystemZSelectionDAGInfo.cpp (original)
> +++ llvm/trunk/lib/Target/SystemZ/SystemZSelectionDAGInfo.cpp Tue Apr 28
> 06:56:37 2015
> @@ -46,10 +46,10 @@ static SDValue emitMemMem(SelectionDAG &
> // number of straight-line MVCs as 6 * 256 - 1.
> if (Size > 6 * 256)
> return DAG.getNode(Loop, DL, MVT::Other, Chain, Dst, Src,
> - DAG.getConstant(Size, PtrVT),
> - DAG.getConstant(Size / 256, PtrVT));
> + DAG.getConstant(Size, DL, PtrVT),
> + DAG.getConstant(Size / 256, DL, PtrVT));
> return DAG.getNode(Sequence, DL, MVT::Other, Chain, Dst, Src,
> - DAG.getConstant(Size, PtrVT));
> + DAG.getConstant(Size, DL, PtrVT));
> }
>
> SDValue SystemZSelectionDAGInfo::
> @@ -78,7 +78,8 @@ static SDValue memsetStore(SelectionDAG
> for (unsigned I = 1; I < Size; ++I)
> StoreVal |= ByteVal << (I * 8);
> return DAG.getStore(Chain, DL,
> - DAG.getConstant(StoreVal, MVT::getIntegerVT(Size *
> 8)),
> + DAG.getConstant(StoreVal, DL,
> + MVT::getIntegerVT(Size * 8)),
> Dst, DstPtrInfo, false, false, Align);
> }
>
> @@ -112,7 +113,7 @@ EmitTargetCodeForMemset(SelectionDAG &DA
> if (Size2 == 0)
> return Chain1;
> Dst = DAG.getNode(ISD::ADD, DL, PtrVT, Dst,
> - DAG.getConstant(Size1, PtrVT));
> + DAG.getConstant(Size1, DL, PtrVT));
> DstPtrInfo = DstPtrInfo.getWithOffset(Size1);
> SDValue Chain2 = memsetStore(DAG, DL, Chain, Dst, ByteVal, Size2,
> std::min(Align, Size1), DstPtrInfo);
> @@ -126,7 +127,7 @@ EmitTargetCodeForMemset(SelectionDAG &DA
> if (Bytes == 1)
> return Chain1;
> SDValue Dst2 = DAG.getNode(ISD::ADD, DL, PtrVT, Dst,
> - DAG.getConstant(1, PtrVT));
> + DAG.getConstant(1, DL, PtrVT));
> SDValue Chain2 = DAG.getStore(Chain, DL, Byte, Dst2,
> DstPtrInfo.getWithOffset(1),
> false, false, 1);
> @@ -146,7 +147,7 @@ EmitTargetCodeForMemset(SelectionDAG &DA
> Chain = DAG.getStore(Chain, DL, Byte, Dst, DstPtrInfo,
> false, false, Align);
> SDValue DstPlus1 = DAG.getNode(ISD::ADD, DL, PtrVT, Dst,
> - DAG.getConstant(1, PtrVT));
> + DAG.getConstant(1, DL, PtrVT));
> return emitMemMem(DAG, DL, SystemZISD::MVC, SystemZISD::MVC_LOOP,
> Chain, DstPlus1, Dst, Bytes - 1);
> }
> @@ -169,10 +170,10 @@ static SDValue emitCLC(SelectionDAG &DAG
> // needs 2 branches, whereas a straight-line sequence would need 3 or
> more.
> if (Size > 3 * 256)
> return DAG.getNode(SystemZISD::CLC_LOOP, DL, VTs, Chain, Src1, Src2,
> - DAG.getConstant(Size, PtrVT),
> - DAG.getConstant(Size / 256, PtrVT));
> + DAG.getConstant(Size, DL, PtrVT),
> + DAG.getConstant(Size / 256, DL, PtrVT));
> return DAG.getNode(SystemZISD::CLC, DL, VTs, Chain, Src1, Src2,
> - DAG.getConstant(Size, PtrVT));
> + DAG.getConstant(Size, DL, PtrVT));
> }
>
> // Convert the current CC value into an integer that is 0 if CC == 0,
> @@ -182,9 +183,9 @@ static SDValue emitCLC(SelectionDAG &DAG
> static SDValue addIPMSequence(SDLoc DL, SDValue Glue, SelectionDAG &DAG) {
> SDValue IPM = DAG.getNode(SystemZISD::IPM, DL, MVT::i32, Glue);
> SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i32, IPM,
> - DAG.getConstant(SystemZ::IPM_CC, MVT::i32));
> + DAG.getConstant(SystemZ::IPM_CC, DL,
> MVT::i32));
> SDValue ROTL = DAG.getNode(ISD::ROTL, DL, MVT::i32, SRL,
> - DAG.getConstant(31, MVT::i32));
> + DAG.getConstant(31, DL, MVT::i32));
> return ROTL;
> }
>
> @@ -213,7 +214,7 @@ EmitTargetCodeForMemchr(SelectionDAG &DA
> Length = DAG.getZExtOrTrunc(Length, DL, PtrVT);
> Char = DAG.getZExtOrTrunc(Char, DL, MVT::i32);
> Char = DAG.getNode(ISD::AND, DL, MVT::i32, Char,
> - DAG.getConstant(255, MVT::i32));
> + DAG.getConstant(255, DL, MVT::i32));
> SDValue Limit = DAG.getNode(ISD::ADD, DL, PtrVT, Src, Length);
> SDValue End = DAG.getNode(SystemZISD::SEARCH_STRING, DL, VTs, Chain,
> Limit, Src, Char);
> @@ -222,9 +223,10 @@ EmitTargetCodeForMemchr(SelectionDAG &DA
>
> // Now select between End and null, depending on whether the character
> // was found.
> - SDValue Ops[] = {End, DAG.getConstant(0, PtrVT),
> - DAG.getConstant(SystemZ::CCMASK_SRST, MVT::i32),
> - DAG.getConstant(SystemZ::CCMASK_SRST_FOUND, MVT::i32),
> Glue};
> + SDValue Ops[] = {End, DAG.getConstant(0, DL, PtrVT),
> + DAG.getConstant(SystemZ::CCMASK_SRST, DL, MVT::i32),
> + DAG.getConstant(SystemZ::CCMASK_SRST_FOUND, DL,
> MVT::i32),
> + Glue};
> VTs = DAG.getVTList(PtrVT, MVT::Glue);
> End = DAG.getNode(SystemZISD::SELECT_CCMASK, DL, VTs, Ops);
> return std::make_pair(End, Chain);
> @@ -237,7 +239,7 @@ EmitTargetCodeForStrcpy(SelectionDAG &DA
> MachinePointerInfo SrcPtrInfo, bool isStpcpy)
> const {
> SDVTList VTs = DAG.getVTList(Dest.getValueType(), MVT::Other);
> SDValue EndDest = DAG.getNode(SystemZISD::STPCPY, DL, VTs, Chain, Dest,
> Src,
> - DAG.getConstant(0, MVT::i32));
> + DAG.getConstant(0, DL, MVT::i32));
> return std::make_pair(isStpcpy ? EndDest : Dest, EndDest.getValue(1));
> }
>
> @@ -248,7 +250,7 @@ EmitTargetCodeForStrcmp(SelectionDAG &DA
> MachinePointerInfo Op2PtrInfo) const {
> SDVTList VTs = DAG.getVTList(Src1.getValueType(), MVT::Other,
> MVT::Glue);
> SDValue Unused = DAG.getNode(SystemZISD::STRCMP, DL, VTs, Chain, Src1,
> Src2,
> - DAG.getConstant(0, MVT::i32));
> + DAG.getConstant(0, DL, MVT::i32));
> Chain = Unused.getValue(1);
> SDValue Glue = Chain.getValue(2);
> return std::make_pair(addIPMSequence(DL, Glue, DAG), Chain);
> @@ -265,7 +267,7 @@ static std::pair<SDValue, SDValue> getBo
> EVT PtrVT = Src.getValueType();
> SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other, MVT::Glue);
> SDValue End = DAG.getNode(SystemZISD::SEARCH_STRING, DL, VTs, Chain,
> - Limit, Src, DAG.getConstant(0, MVT::i32));
> + Limit, Src, DAG.getConstant(0, DL, MVT::i32));
> Chain = End.getValue(1);
> SDValue Len = DAG.getNode(ISD::SUB, DL, PtrVT, End, Src);
> return std::make_pair(Len, Chain);
> @@ -275,7 +277,7 @@ std::pair<SDValue, SDValue> SystemZSelec
> EmitTargetCodeForStrlen(SelectionDAG &DAG, SDLoc DL, SDValue Chain,
> SDValue Src, MachinePointerInfo SrcPtrInfo) const
> {
> EVT PtrVT = Src.getValueType();
> - return getBoundedStrlen(DAG, DL, Chain, Src, DAG.getConstant(0, PtrVT));
> + return getBoundedStrlen(DAG, DL, Chain, Src, DAG.getConstant(0, DL,
> PtrVT));
> }
>
> std::pair<SDValue, SDValue> SystemZSelectionDAGInfo::
>
> Modified: llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp?rev=235977&r1=235976&r2=235977&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp Tue Apr 28 06:56:37 2015
> @@ -233,14 +233,15 @@ namespace {
>
> void EmitSpecialCodeForMain();
>
> - inline void getAddressOperands(X86ISelAddressMode &AM, SDValue &Base,
> - SDValue &Scale, SDValue &Index,
> - SDValue &Disp, SDValue &Segment) {
> + inline void getAddressOperands(X86ISelAddressMode &AM, SDLoc DL,
> + SDValue &Base, SDValue &Scale,
> + SDValue &Index, SDValue &Disp,
> + SDValue &Segment) {
> Base = (AM.BaseType == X86ISelAddressMode::FrameIndexBase)
> ? CurDAG->getTargetFrameIndex(AM.Base_FrameIndex,
> TLI->getPointerTy())
> : AM.Base_Reg;
> - Scale = getI8Imm(AM.Scale);
> + Scale = getI8Imm(AM.Scale, DL);
> Index = AM.IndexReg;
> // These are 32-bit even in 64-bit mode since RIP relative offset
> // is 32-bit.
> @@ -261,7 +262,7 @@ namespace {
> Disp = CurDAG->getTargetBlockAddress(AM.BlockAddr, MVT::i32,
> AM.Disp,
> AM.SymbolFlags);
> else
> - Disp = CurDAG->getTargetConstant(AM.Disp, MVT::i32);
> + Disp = CurDAG->getTargetConstant(AM.Disp, DL, MVT::i32);
>
> if (AM.Segment.getNode())
> Segment = AM.Segment;
> @@ -271,14 +272,14 @@ namespace {
>
> /// getI8Imm - Return a target constant with the specified value, of
> type
> /// i8.
> - inline SDValue getI8Imm(unsigned Imm) {
> - return CurDAG->getTargetConstant(Imm, MVT::i8);
> + inline SDValue getI8Imm(unsigned Imm, SDLoc DL) {
> + return CurDAG->getTargetConstant(Imm, DL, MVT::i8);
> }
>
> /// getI32Imm - Return a target constant with the specified value, of
> type
> /// i32.
> - inline SDValue getI32Imm(unsigned Imm) {
> - return CurDAG->getTargetConstant(Imm, MVT::i32);
> + inline SDValue getI32Imm(unsigned Imm, SDLoc DL) {
> + return CurDAG->getTargetConstant(Imm, DL, MVT::i32);
> }
>
> /// getGlobalBaseReg - Return an SDNode that returns the value of
> @@ -801,11 +802,11 @@ static bool FoldMaskAndShiftToExtract(Se
>
> MVT VT = N.getSimpleValueType();
> SDLoc DL(N);
> - SDValue Eight = DAG.getConstant(8, MVT::i8);
> - SDValue NewMask = DAG.getConstant(0xff, VT);
> + SDValue Eight = DAG.getConstant(8, DL, MVT::i8);
> + SDValue NewMask = DAG.getConstant(0xff, DL, VT);
> SDValue Srl = DAG.getNode(ISD::SRL, DL, VT, X, Eight);
> SDValue And = DAG.getNode(ISD::AND, DL, VT, Srl, NewMask);
> - SDValue ShlCount = DAG.getConstant(ScaleLog, MVT::i8);
> + SDValue ShlCount = DAG.getConstant(ScaleLog, DL, MVT::i8);
> SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, And, ShlCount);
>
> // Insert the new nodes into the topological ordering. We must do this
> in
> @@ -849,7 +850,7 @@ static bool FoldMaskedShiftToScaledMask(
>
> MVT VT = N.getSimpleValueType();
> SDLoc DL(N);
> - SDValue NewMask = DAG.getConstant(Mask >> ShiftAmt, VT);
> + SDValue NewMask = DAG.getConstant(Mask >> ShiftAmt, DL, VT);
> SDValue NewAnd = DAG.getNode(ISD::AND, DL, VT, X, NewMask);
> SDValue NewShift = DAG.getNode(ISD::SHL, DL, VT, NewAnd,
> Shift.getOperand(1));
>
> @@ -955,9 +956,9 @@ static bool FoldMaskAndShiftToScale(Sele
> X = NewX;
> }
> SDLoc DL(N);
> - SDValue NewSRLAmt = DAG.getConstant(ShiftAmt + AMShiftAmt, MVT::i8);
> + SDValue NewSRLAmt = DAG.getConstant(ShiftAmt + AMShiftAmt, DL, MVT::i8);
> SDValue NewSRL = DAG.getNode(ISD::SRL, DL, VT, X, NewSRLAmt);
> - SDValue NewSHLAmt = DAG.getConstant(AMShiftAmt, MVT::i8);
> + SDValue NewSHLAmt = DAG.getConstant(AMShiftAmt, DL, MVT::i8);
> SDValue NewSHL = DAG.getNode(ISD::SHL, DL, VT, NewSRL, NewSHLAmt);
>
> // Insert the new nodes into the topological ordering. We must do this
> in
> @@ -1198,7 +1199,7 @@ bool X86DAGToDAGISel::MatchAddressRecurs
> }
>
> // Ok, the transformation is legal and appears profitable. Go for it.
> - SDValue Zero = CurDAG->getConstant(0, N.getValueType());
> + SDValue Zero = CurDAG->getConstant(0, dl, N.getValueType());
> SDValue Neg = CurDAG->getNode(ISD::SUB, dl, N.getValueType(), Zero,
> RHS);
> AM.IndexReg = Neg;
> AM.Scale = 1;
> @@ -1357,7 +1358,7 @@ bool X86DAGToDAGISel::SelectAddr(SDNode
> if (!AM.IndexReg.getNode())
> AM.IndexReg = CurDAG->getRegister(0, VT);
>
> - getAddressOperands(AM, Base, Scale, Index, Disp, Segment);
> + getAddressOperands(AM, SDLoc(N), Base, Scale, Index, Disp, Segment);
> return true;
> }
>
> @@ -1413,7 +1414,7 @@ bool X86DAGToDAGISel::SelectMOV64Imm32(S
> if ((uint32_t)ImmVal != (uint64_t)ImmVal)
> return false;
>
> - Imm = CurDAG->getTargetConstant(ImmVal, MVT::i64);
> + Imm = CurDAG->getTargetConstant(ImmVal, SDLoc(N), MVT::i64);
> return true;
> }
>
> @@ -1449,9 +1450,9 @@ bool X86DAGToDAGISel::SelectLEA64_32Addr
> // Base could already be %rip, particularly in the x32 ABI.
> Base = SDValue(CurDAG->getMachineNode(
> TargetOpcode::SUBREG_TO_REG, DL, MVT::i64,
> - CurDAG->getTargetConstant(0, MVT::i64),
> + CurDAG->getTargetConstant(0, DL, MVT::i64),
> Base,
> - CurDAG->getTargetConstant(X86::sub_32bit,
> MVT::i32)),
> + CurDAG->getTargetConstant(X86::sub_32bit, DL,
> MVT::i32)),
> 0);
> }
>
> @@ -1463,9 +1464,10 @@ bool X86DAGToDAGISel::SelectLEA64_32Addr
> "Expect to be extending 32-bit registers for use in LEA");
> Index = SDValue(CurDAG->getMachineNode(
> TargetOpcode::SUBREG_TO_REG, DL, MVT::i64,
> - CurDAG->getTargetConstant(0, MVT::i64),
> + CurDAG->getTargetConstant(0, DL, MVT::i64),
> Index,
> - CurDAG->getTargetConstant(X86::sub_32bit,
> MVT::i32)),
> + CurDAG->getTargetConstant(X86::sub_32bit, DL,
> + MVT::i32)),
> 0);
> }
>
> @@ -1531,7 +1533,7 @@ bool X86DAGToDAGISel::SelectLEAAddr(SDVa
> if (Complexity <= 2)
> return false;
>
> - getAddressOperands(AM, Base, Scale, Index, Disp, Segment);
> + getAddressOperands(AM, SDLoc(N), Base, Scale, Index, Disp, Segment);
> return true;
> }
>
> @@ -1555,7 +1557,7 @@ bool X86DAGToDAGISel::SelectTLSADDRAddr(
> AM.IndexReg = CurDAG->getRegister(0, MVT::i64);
> }
>
> - getAddressOperands(AM, Base, Scale, Index, Disp, Segment);
> + getAddressOperands(AM, SDLoc(N), Base, Scale, Index, Disp, Segment);
> return true;
> }
>
> @@ -1725,7 +1727,7 @@ static SDValue getAtomicLoadArithTargetC
> // an immediate operand to sub. However, it still fits in 32 bits for
> the
> // add (since it is not negated) so we can return target-constant.
> if (CNVal == INT32_MIN)
> - return CurDAG->getTargetConstant(CNVal, NVT);
> + return CurDAG->getTargetConstant(CNVal, dl, NVT);
> // For atomic-load-add, we could do some optimizations.
> if (Op == ADD) {
> // Translate to INC/DEC if ADD by 1 or -1.
> @@ -1740,7 +1742,7 @@ static SDValue getAtomicLoadArithTargetC
> CNVal = -CNVal;
> }
> }
> - return CurDAG->getTargetConstant(CNVal, NVT);
> + return CurDAG->getTargetConstant(CNVal, dl, NVT);
> }
>
> // If the value operand is single-used, try to optimize it.
> @@ -2053,12 +2055,14 @@ SDNode *X86DAGToDAGISel::SelectGather(SD
> SDVTList VTs = CurDAG->getVTList(VSrc.getValueType(),
> VSrc.getValueType(),
> MVT::Other);
>
> + SDLoc DL(Node);
> +
> // Memory Operands: Base, Scale, Index, Disp, Segment
> - SDValue Disp = CurDAG->getTargetConstant(0, MVT::i32);
> + SDValue Disp = CurDAG->getTargetConstant(0, DL, MVT::i32);
> SDValue Segment = CurDAG->getRegister(0, MVT::i32);
> - const SDValue Ops[] = { VSrc, Base, getI8Imm(Scale->getSExtValue()),
> VIdx,
> + const SDValue Ops[] = { VSrc, Base, getI8Imm(Scale->getSExtValue(),
> DL), VIdx,
> Disp, Segment, VMask, Chain};
> - SDNode *ResNode = CurDAG->getMachineNode(Opc, SDLoc(Node), VTs, Ops);
> + SDNode *ResNode = CurDAG->getMachineNode(Opc, DL, VTs, Ops);
> // Node has 2 outputs: VDst and MVT::Other.
> // ResNode has 3 outputs: VDst, VMask_wb, and MVT::Other.
> // We replace VDst of Node with VDst of ResNode, and Other of Node with
> Other
> @@ -2232,13 +2236,13 @@ SDNode *X86DAGToDAGISel::Select(SDNode *
> }
>
> // Emit the smaller op and the shift.
> - SDValue NewCst = CurDAG->getTargetConstant(Val >> ShlVal, CstVT);
> + SDValue NewCst = CurDAG->getTargetConstant(Val >> ShlVal, dl, CstVT);
> SDNode *New = CurDAG->getMachineNode(Op, dl, NVT,
> N0->getOperand(0),NewCst);
> if (ShlVal == 1)
> return CurDAG->SelectNodeTo(Node, AddOp, NVT, SDValue(New, 0),
> SDValue(New, 0));
> return CurDAG->SelectNodeTo(Node, ShlOp, NVT, SDValue(New, 0),
> - getI8Imm(ShlVal));
> + getI8Imm(ShlVal, dl));
> }
> case X86ISD::UMUL8:
> case X86ISD::SMUL8: {
> @@ -2402,7 +2406,8 @@ SDNode *X86DAGToDAGISel::Select(SDNode *
> // Shift AX down 8 bits.
> Result = SDValue(CurDAG->getMachineNode(X86::SHR16ri, dl, MVT::i16,
> Result,
> - CurDAG->getTargetConstant(8,
> MVT::i8)), 0);
> + CurDAG->getTargetConstant(8, dl,
> MVT::i8)),
> + 0);
> // Then truncate it down to i8.
> ReplaceUses(SDValue(Node, 1),
> CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, MVT::i8,
> Result));
> @@ -2522,7 +2527,8 @@ SDNode *X86DAGToDAGISel::Select(SDNode *
> ClrNode =
> SDValue(CurDAG->getMachineNode(
> TargetOpcode::EXTRACT_SUBREG, dl, MVT::i16,
> ClrNode,
> - CurDAG->getTargetConstant(X86::sub_16bit,
> MVT::i32)),
> + CurDAG->getTargetConstant(X86::sub_16bit, dl,
> + MVT::i32)),
> 0);
> break;
> case MVT::i32:
> @@ -2531,8 +2537,9 @@ SDNode *X86DAGToDAGISel::Select(SDNode *
> ClrNode =
> SDValue(CurDAG->getMachineNode(
> TargetOpcode::SUBREG_TO_REG, dl, MVT::i64,
> - CurDAG->getTargetConstant(0, MVT::i64), ClrNode,
> - CurDAG->getTargetConstant(X86::sub_32bit,
> MVT::i32)),
> + CurDAG->getTargetConstant(0, dl, MVT::i64),
> ClrNode,
> + CurDAG->getTargetConstant(X86::sub_32bit, dl,
> + MVT::i32)),
> 0);
> break;
> default:
> @@ -2584,8 +2591,9 @@ SDNode *X86DAGToDAGISel::Select(SDNode *
> Result =
> SDValue(CurDAG->getMachineNode(
> TargetOpcode::SUBREG_TO_REG, dl, MVT::i64,
> - CurDAG->getTargetConstant(0, MVT::i64), Result,
> - CurDAG->getTargetConstant(X86::sub_32bit,
> MVT::i32)),
> + CurDAG->getTargetConstant(0, dl, MVT::i64),
> Result,
> + CurDAG->getTargetConstant(X86::sub_32bit, dl,
> + MVT::i32)),
> 0);
> }
> } else {
> @@ -2642,7 +2650,7 @@ SDNode *X86DAGToDAGISel::Select(SDNode *
> if ((C->getZExtValue() & ~UINT64_C(0xff)) == 0 &&
> (!(C->getZExtValue() & 0x80) ||
> HasNoSignedComparisonUses(Node))) {
> - SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(),
> MVT::i8);
> + SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(), dl,
> MVT::i8);
> SDValue Reg = N0.getNode()->getOperand(0);
>
> // On x86-32, only the ABCD registers have 8-bit subregisters.
> @@ -2653,7 +2661,7 @@ SDNode *X86DAGToDAGISel::Select(SDNode *
> case MVT::i16: TRC = &X86::GR16_ABCDRegClass; break;
> default: llvm_unreachable("Unsupported TEST operand type!");
> }
> - SDValue RC = CurDAG->getTargetConstant(TRC->getID(), MVT::i32);
> + SDValue RC = CurDAG->getTargetConstant(TRC->getID(), dl,
> MVT::i32);
> Reg = SDValue(CurDAG->getMachineNode(X86::COPY_TO_REGCLASS, dl,
> Reg.getValueType(), Reg,
> RC), 0);
> }
> @@ -2678,7 +2686,7 @@ SDNode *X86DAGToDAGISel::Select(SDNode *
> HasNoSignedComparisonUses(Node))) {
> // Shift the immediate right by 8 bits.
> SDValue ShiftedImm = CurDAG->getTargetConstant(C->getZExtValue()
> >> 8,
> - MVT::i8);
> + dl, MVT::i8);
> SDValue Reg = N0.getNode()->getOperand(0);
>
> // Put the value in an ABCD register.
> @@ -2689,7 +2697,7 @@ SDNode *X86DAGToDAGISel::Select(SDNode *
> case MVT::i16: TRC = &X86::GR16_ABCDRegClass; break;
> default: llvm_unreachable("Unsupported TEST operand type!");
> }
> - SDValue RC = CurDAG->getTargetConstant(TRC->getID(), MVT::i32);
> + SDValue RC = CurDAG->getTargetConstant(TRC->getID(), dl,
> MVT::i32);
> Reg = SDValue(CurDAG->getMachineNode(X86::COPY_TO_REGCLASS, dl,
> Reg.getValueType(), Reg,
> RC), 0);
>
> @@ -2714,7 +2722,8 @@ SDNode *X86DAGToDAGISel::Select(SDNode *
> N0.getValueType() != MVT::i16 &&
> (!(C->getZExtValue() & 0x8000) ||
> HasNoSignedComparisonUses(Node))) {
> - SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(),
> MVT::i16);
> + SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(), dl,
> + MVT::i16);
> SDValue Reg = N0.getNode()->getOperand(0);
>
> // Extract the 16-bit subregister.
> @@ -2736,7 +2745,8 @@ SDNode *X86DAGToDAGISel::Select(SDNode *
> N0.getValueType() == MVT::i64 &&
> (!(C->getZExtValue() & 0x80000000) ||
> HasNoSignedComparisonUses(Node))) {
> - SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(),
> MVT::i32);
> + SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(), dl,
> + MVT::i32);
> SDValue Reg = N0.getNode()->getOperand(0);
>
> // Extract the 32-bit subregister.
>
> Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=235977&r1=235976&r2=235977&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue Apr 28 06:56:37 2015
> @@ -1892,7 +1892,7 @@ X86TargetLowering::LowerReturn(SDValue C
> SmallVector<SDValue, 6> RetOps;
> RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
> // Operand #1 = Bytes To Pop
> -
> RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
> +
> RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
> dl,
> MVT::i16));
>
> // Copy the result values into the output registers.
> @@ -2095,7 +2095,7 @@ X86TargetLowering::LowerCallResult(SDVal
> if (CopyVT != VA.getValVT())
> Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
> // This truncation won't change the value.
> - DAG.getIntPtrConstant(1));
> + DAG.getIntPtrConstant(1, dl));
>
> InFlag = Chain.getValue(2);
> InVals.push_back(Val);
> @@ -2155,7 +2155,7 @@ static SDValue
> CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
> ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
> SDLoc dl) {
> - SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
> + SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32);
>
> return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode,
> Flags.getByValAlign(),
> /*isVolatile*/false, /*AlwaysInline=*/true,
> @@ -2503,7 +2503,7 @@ X86TargetLowering::LowerFormalArguments(
> unsigned Offset = FuncInfo->getVarArgsGPOffset();
> for (SDValue Val : LiveGPRs) {
> SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
> - DAG.getIntPtrConstant(Offset));
> + DAG.getIntPtrConstant(Offset, dl));
> SDValue Store =
> DAG.getStore(Val.getValue(1), dl, Val, FIN,
> MachinePointerInfo::getFixedStack(
> @@ -2519,9 +2519,9 @@ X86TargetLowering::LowerFormalArguments(
> SaveXMMOps.push_back(Chain);
> SaveXMMOps.push_back(ALVal);
> SaveXMMOps.push_back(DAG.getIntPtrConstant(
> - FuncInfo->getRegSaveFrameIndex()));
> + FuncInfo->getRegSaveFrameIndex(), dl));
> SaveXMMOps.push_back(DAG.getIntPtrConstant(
> - FuncInfo->getVarArgsFPOffset()));
> + FuncInfo->getVarArgsFPOffset(), dl));
> SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
> LiveXMMRegs.end());
> MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
> @@ -2621,7 +2621,7 @@ X86TargetLowering::LowerFormalArguments(
> int UnwindHelpFI = MFI->CreateStackObject(8, 8, /*isSS=*/false);
> SDValue StackSlot = DAG.getFrameIndex(UnwindHelpFI, MVT::i64);
> MMI.getWinEHFuncInfo(MF.getFunction()).UnwindHelpFrameIdx =
> UnwindHelpFI;
> - SDValue Neg2 = DAG.getConstant(-2, MVT::i64);
> + SDValue Neg2 = DAG.getConstant(-2, dl, MVT::i64);
> Chain = DAG.getStore(Chain, dl, Neg2, StackSlot,
> MachinePointerInfo::getFixedStack(UnwindHelpFI),
> /*isVolatile=*/true,
> @@ -2638,7 +2638,7 @@ X86TargetLowering::LowerMemOpCallTo(SDVa
> const CCValAssign &VA,
> ISD::ArgFlagsTy Flags) const {
> unsigned LocMemOffset = VA.getLocMemOffset();
> - SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
> + SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
> PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
> if (Flags.isByVal())
> return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
> @@ -2784,7 +2784,7 @@ X86TargetLowering::LowerCall(TargetLower
>
> if (!IsSibcall)
> Chain = DAG.getCALLSEQ_START(
> - Chain, DAG.getIntPtrConstant(NumBytesToPush, true), dl);
> + Chain, DAG.getIntPtrConstant(NumBytesToPush, dl, true), dl);
>
> SDValue RetAddrFrIdx;
> // Load return address for tail calls.
> @@ -2916,7 +2916,8 @@ X86TargetLowering::LowerCall(TargetLower
> && "SSE registers cannot be used when SSE is disabled");
>
> RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
> - DAG.getConstant(NumXMMRegs,
> MVT::i8)));
> + DAG.getConstant(NumXMMRegs, dl,
> + MVT::i8)));
> }
>
> if (isVarArg && IsMustTail) {
> @@ -2960,7 +2961,7 @@ X86TargetLowering::LowerCall(TargetLower
>
> if (Flags.isByVal()) {
> // Copy relative to framepointer.
> - SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
> + SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset(), dl);
> if (!StackPtr.getNode())
> StackPtr = DAG.getCopyFromReg(Chain, dl,
> RegInfo->getStackRegister(),
> @@ -3086,8 +3087,8 @@ X86TargetLowering::LowerCall(TargetLower
>
> if (!IsSibcall && isTailCall) {
> Chain = DAG.getCALLSEQ_END(Chain,
> - DAG.getIntPtrConstant(NumBytesToPop, true),
> - DAG.getIntPtrConstant(0, true), InFlag,
> dl);
> + DAG.getIntPtrConstant(NumBytesToPop, dl,
> true),
> + DAG.getIntPtrConstant(0, dl, true),
> InFlag, dl);
> InFlag = Chain.getValue(1);
> }
>
> @@ -3095,7 +3096,7 @@ X86TargetLowering::LowerCall(TargetLower
> Ops.push_back(Callee);
>
> if (isTailCall)
> - Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
> + Ops.push_back(DAG.getConstant(FPDiff, dl, MVT::i32));
>
> // Add argument registers to the end of the list so that they are known
> live
> // into the call.
> @@ -3144,8 +3145,8 @@ X86TargetLowering::LowerCall(TargetLower
> // Returns a flag for retval copy to use.
> if (!IsSibcall) {
> Chain = DAG.getCALLSEQ_END(Chain,
> - DAG.getIntPtrConstant(NumBytesToPop, true),
> -
> DAG.getIntPtrConstant(NumBytesForCalleeToPop,
> + DAG.getIntPtrConstant(NumBytesToPop, dl,
> true),
> +
> DAG.getIntPtrConstant(NumBytesForCalleeToPop, dl,
> true),
> InFlag, dl);
> InFlag = Chain.getValue(1);
> @@ -3532,7 +3533,8 @@ static SDValue getTargetShuffleNode(unsi
> case X86ISD::PSHUFLW:
> case X86ISD::VPERMILPI:
> case X86ISD::VPERMI:
> - return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask,
> MVT::i8));
> + return DAG.getNode(Opc, dl, VT, V1,
> + DAG.getConstant(TargetMask, dl, MVT::i8));
> }
> }
>
> @@ -3642,13 +3644,13 @@ static bool isX86CCUnsigned(unsigned X86
> /// TranslateX86CC - do a one to one translation of a ISD::CondCode to
> the X86
> /// specific condition code, returning the condition code and the LHS/RHS
> of the
> /// comparison to make.
> -static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
> +static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, SDLoc DL, bool
> isFP,
> SDValue &LHS, SDValue &RHS, SelectionDAG
> &DAG) {
> if (!isFP) {
> if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
> if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
> // X > -1 -> X == 0, jump !sign.
> - RHS = DAG.getConstant(0, RHS.getValueType());
> + RHS = DAG.getConstant(0, DL, RHS.getValueType());
> return X86::COND_NS;
> }
> if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
> @@ -3657,7 +3659,7 @@ static unsigned TranslateX86CC(ISD::Cond
> }
> if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
> // X < 1 -> X <= 0
> - RHS = DAG.getConstant(0, RHS.getValueType());
> + RHS = DAG.getConstant(0, DL, RHS.getValueType());
> return X86::COND_LE;
> }
> }
> @@ -3960,26 +3962,26 @@ static SDValue getZeroVector(EVT VT, con
> SDValue Vec;
> if (VT.is128BitVector()) { // SSE
> if (Subtarget->hasSSE2()) { // SSE2
> - SDValue Cst = DAG.getConstant(0, MVT::i32);
> + SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
> Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst,
> Cst);
> } else { // SSE1
> - SDValue Cst = DAG.getConstantFP(+0.0, MVT::f32);
> + SDValue Cst = DAG.getConstantFP(+0.0, dl, MVT::f32);
> Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst,
> Cst);
> }
> } else if (VT.is256BitVector()) { // AVX
> if (Subtarget->hasInt256()) { // AVX2
> - SDValue Cst = DAG.getConstant(0, MVT::i32);
> + SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
> SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
> Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
> } else {
> // 256-bit logic and arithmetic instructions in AVX are all
> // floating-point, no support for integer ops. Emit fp zeroed
> vectors.
> - SDValue Cst = DAG.getConstantFP(+0.0, MVT::f32);
> + SDValue Cst = DAG.getConstantFP(+0.0, dl, MVT::f32);
> SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
> Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
> }
> } else if (VT.is512BitVector()) { // AVX-512
> - SDValue Cst = DAG.getConstant(0, MVT::i32);
> + SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
> SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
> Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
> Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
> @@ -3989,7 +3991,7 @@ static SDValue getZeroVector(EVT VT, con
> && "Unexpected vector type");
> assert((Subtarget->hasVLX() || VT.getVectorNumElements() >= 8)
> && "Unexpected vector type");
> - SDValue Cst = DAG.getConstant(0, MVT::i1);
> + SDValue Cst = DAG.getConstant(0, dl, MVT::i1);
> SmallVector<SDValue, 64> Ops(VT.getVectorNumElements(), Cst);
> return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
> } else
> @@ -4027,7 +4029,7 @@ static SDValue ExtractSubVector(SDValue
> makeArrayRef(Vec->op_begin() + NormalizedIdxVal,
> ElemsPerChunk));
>
> - SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
> + SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal, dl);
> return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, VecIdx);
> }
>
> @@ -4071,7 +4073,7 @@ static SDValue InsertSubVector(SDValue R
> unsigned NormalizedIdxVal = (((IdxVal *
> ElVT.getSizeInBits())/vectorWidth)
> * ElemsPerChunk);
>
> - SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
> + SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal, dl);
> return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
> VecIdx);
> }
>
> @@ -4093,7 +4095,7 @@ static SDValue Insert128BitVector(SDValu
> if (IdxVal == 0 && Result.getValueType().is256BitVector() &&
> Result.getOpcode() != ISD::UNDEF) {
> EVT ResultVT = Result.getValueType();
> - SDValue ZeroIndex = DAG.getIntPtrConstant(0);
> + SDValue ZeroIndex = DAG.getIntPtrConstant(0, dl);
> SDValue Undef = DAG.getUNDEF(ResultVT);
> SDValue Vec256 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT,
> Undef,
> Vec, ZeroIndex);
> @@ -4105,7 +4107,7 @@ static SDValue Insert128BitVector(SDValu
> unsigned ScalarSize = ScalarType.getSizeInBits();
> assert((ScalarSize == 64 || ScalarSize == 32) && "Unknown float
> type");
> unsigned MaskVal = (ScalarSize == 64) ? 0x03 : 0x0f;
> - SDValue Mask = DAG.getConstant(MaskVal, MVT::i8);
> + SDValue Mask = DAG.getConstant(MaskVal, dl, MVT::i8);
> return DAG.getNode(X86ISD::BLENDI, dl, ResultVT, Result, Vec256,
> Mask);
> }
>
> @@ -4121,7 +4123,7 @@ static SDValue Insert128BitVector(SDValu
> // will be created by InsertSubVector().
> MVT CastVT = Subtarget.hasAVX2() ? MVT::v8i32 : MVT::v8f32;
>
> - SDValue Mask = DAG.getConstant(0x0f, MVT::i8);
> + SDValue Mask = DAG.getConstant(0x0f, dl, MVT::i8);
> Vec256 = DAG.getNode(ISD::BITCAST, dl, CastVT, Vec256);
> Vec256 = DAG.getNode(X86ISD::BLENDI, dl, CastVT, Result, Vec256,
> Mask);
> return DAG.getNode(ISD::BITCAST, dl, ResultVT, Vec256);
> @@ -4162,7 +4164,7 @@ static SDValue getOnesVector(MVT VT, boo
> SDLoc dl) {
> assert(VT.isVector() && "Expected a vector type");
>
> - SDValue Cst = DAG.getConstant(~0U, MVT::i32);
> + SDValue Cst = DAG.getConstant(~0U, dl, MVT::i32);
> SDValue Vec;
> if (VT.is256BitVector()) {
> if (HasInt256) { // AVX2
> @@ -4492,7 +4494,7 @@ static SDValue LowerBuildVectorv16i8(SDV
> }
> V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
> MVT::v16i8, V, Op.getOperand(i),
> - DAG.getIntPtrConstant(i));
> + DAG.getIntPtrConstant(i, dl));
> }
> }
>
> @@ -4520,7 +4522,7 @@ static SDValue LowerBuildVectorv16i8(SDV
> if (ThisIsNonZero) {
> ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16,
> Op.getOperand(i));
> ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
> - ThisElt, DAG.getConstant(8, MVT::i8));
> + ThisElt, DAG.getConstant(8, dl, MVT::i8));
> if (LastIsNonZero)
> ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
> } else
> @@ -4528,7 +4530,7 @@ static SDValue LowerBuildVectorv16i8(SDV
>
> if (ThisElt.getNode())
> V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V,
> ThisElt,
> - DAG.getIntPtrConstant(i/2));
> + DAG.getIntPtrConstant(i/2, dl));
> }
> }
>
> @@ -4560,7 +4562,7 @@ static SDValue LowerBuildVectorv8i16(SDV
> }
> V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
> MVT::v8i16, V, Op.getOperand(i),
> - DAG.getIntPtrConstant(i));
> + DAG.getIntPtrConstant(i, dl));
> }
> }
>
> @@ -4667,9 +4669,10 @@ static SDValue LowerBuildVectorv4x32(SDV
>
> unsigned InsertPSMask = EltMaskIdx << 6 | EltIdx << 4 | ZMask;
> assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
> - SDValue Result = DAG.getNode(X86ISD::INSERTPS, SDLoc(Op), MVT::v4f32,
> V1, V2,
> - DAG.getIntPtrConstant(InsertPSMask));
> - return DAG.getNode(ISD::BITCAST, SDLoc(Op), VT, Result);
> + SDLoc DL(Op);
> + SDValue Result = DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
> + DAG.getIntPtrConstant(InsertPSMask, DL));
> + return DAG.getNode(ISD::BITCAST, DL, VT, Result);
> }
>
> /// Return a vector logical shift node.
> @@ -4682,7 +4685,7 @@ static SDValue getVShift(bool isLeft, EV
> SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
> MVT ScalarShiftTy = TLI.getScalarShiftAmountTy(SrcOp.getValueType());
> assert(NumBits % 8 == 0 && "Only support byte sized shifts");
> - SDValue ShiftVal = DAG.getConstant(NumBits/8, ScalarShiftTy);
> + SDValue ShiftVal = DAG.getConstant(NumBits/8, dl, ScalarShiftTy);
> return DAG.getNode(ISD::BITCAST, dl, VT,
> DAG.getNode(Opc, dl, ShVT, SrcOp, ShiftVal));
> }
> @@ -4739,9 +4742,11 @@ LowerAsSplatVectorLoad(SDValue SrcOp, MV
> if ((Offset % RequiredAlign) & 3)
> return SDValue();
> int64_t StartOffset = Offset & ~(RequiredAlign-1);
> - if (StartOffset)
> - Ptr = DAG.getNode(ISD::ADD, SDLoc(Ptr), Ptr.getValueType(),
> - Ptr,DAG.getConstant(StartOffset,
> Ptr.getValueType()));
> + if (StartOffset) {
> + SDLoc DL(Ptr);
> + Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
> + DAG.getConstant(StartOffset, DL,
> Ptr.getValueType()));
> + }
>
> int EltNo = (Offset - StartOffset) >> 2;
> unsigned NumElems = VT.getVectorNumElements();
> @@ -5134,7 +5139,7 @@ static SDValue buildFromShuffleMostly(SD
> for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
> unsigned Idx = InsertIndices[i];
> NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV,
> Op.getOperand(Idx),
> - DAG.getIntPtrConstant(Idx));
> + DAG.getIntPtrConstant(Idx, DL));
> }
>
> return NV;
> @@ -5150,13 +5155,13 @@ X86TargetLowering::LowerBUILD_VECTORvXi1
>
> SDLoc dl(Op);
> if (ISD::isBuildVectorAllZeros(Op.getNode())) {
> - SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
> + SDValue Cst = DAG.getTargetConstant(0, dl, MVT::i1);
> SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
> return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
> }
>
> if (ISD::isBuildVectorAllOnes(Op.getNode())) {
> - SDValue Cst = DAG.getTargetConstant(1, MVT::i1);
> + SDValue Cst = DAG.getTargetConstant(1, dl, MVT::i1);
> SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
> return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
> }
> @@ -5186,15 +5191,15 @@ X86TargetLowering::LowerBUILD_VECTORvXi1
>
> if (AllContants) {
> SDValue FullMask = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1,
> - DAG.getConstant(Immediate, MVT::i16));
> + DAG.getConstant(Immediate, dl, MVT::i16));
> return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, FullMask,
> - DAG.getIntPtrConstant(0));
> + DAG.getIntPtrConstant(0, dl));
> }
>
> if (NumNonConsts == 1 && NonConstIdx != 0) {
> SDValue DstVec;
> if (NumConsts) {
> - SDValue VecAsImm = DAG.getConstant(Immediate,
> + SDValue VecAsImm = DAG.getConstant(Immediate, dl,
>
> MVT::getIntegerVT(VT.getSizeInBits()));
> DstVec = DAG.getNode(ISD::BITCAST, dl, VT, VecAsImm);
> }
> @@ -5202,7 +5207,7 @@ X86TargetLowering::LowerBUILD_VECTORvXi1
> DstVec = DAG.getUNDEF(VT);
> return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
> Op.getOperand(NonConstIdx),
> - DAG.getIntPtrConstant(NonConstIdx));
> + DAG.getIntPtrConstant(NonConstIdx, dl));
> }
> if (!IsSplat && (NonConstIdx != 0))
> llvm_unreachable("Unsupported BUILD_VECTOR operation");
> @@ -5210,12 +5215,12 @@ X86TargetLowering::LowerBUILD_VECTORvXi1
> SDValue Select;
> if (IsSplat)
> Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
> - DAG.getConstant(-1, SelectVT),
> - DAG.getConstant(0, SelectVT));
> + DAG.getConstant(-1, dl, SelectVT),
> + DAG.getConstant(0, dl, SelectVT));
> else
> Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
> - DAG.getConstant((Immediate | 1), SelectVT),
> - DAG.getConstant(Immediate, SelectVT));
> + DAG.getConstant((Immediate | 1), dl, SelectVT),
> + DAG.getConstant(Immediate, dl, SelectVT));
> return DAG.getNode(ISD::BITCAST, dl, VT, Select);
> }
>
> @@ -5733,7 +5738,7 @@ X86TargetLowering::LowerBUILD_VECTOR(SDV
> if (VT.is512BitVector()) {
> SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
> return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
> - Item, DAG.getIntPtrConstant(0));
> + Item, DAG.getIntPtrConstant(0, dl));
> }
> assert((VT.is128BitVector() || VT.is256BitVector()) &&
> "Expected an SSE value type!");
> @@ -5927,7 +5932,7 @@ X86TargetLowering::LowerBUILD_VECTOR(SDV
> for (unsigned i = 1; i < NumElems; ++i) {
> if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
> Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
> - Op.getOperand(i), DAG.getIntPtrConstant(i));
> + Op.getOperand(i), DAG.getIntPtrConstant(i,
> dl));
> }
> return Result;
> }
> @@ -6025,10 +6030,10 @@ static SDValue LowerCONCAT_VECTORSvXi1(S
> if (IsZeroV1 && IsZeroV2)
> return getZeroVector(ResVT, Subtarget, DAG, dl);
>
> - SDValue ZeroIdx = DAG.getIntPtrConstant(0);
> + SDValue ZeroIdx = DAG.getIntPtrConstant(0, dl);
> SDValue Undef = DAG.getUNDEF(ResVT);
> unsigned NumElems = ResVT.getVectorNumElements();
> - SDValue ShiftBits = DAG.getConstant(NumElems/2, MVT::i8);
> + SDValue ShiftBits = DAG.getConstant(NumElems/2, dl, MVT::i8);
>
> V2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V2, ZeroIdx);
> V2 = DAG.getNode(X86ISD::VSHLI, dl, ResVT, V2, ShiftBits);
> @@ -6196,7 +6201,7 @@ static bool isShuffleEquivalent(SDValue
> /// example.
> ///
> /// NB: We rely heavily on "undef" masks preserving the input lane.
> -static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask,
> +static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask, SDLoc DL,
> SelectionDAG &DAG) {
> assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
> assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
> @@ -6209,7 +6214,7 @@ static SDValue getV4X86ShuffleImm8ForMas
> Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
> Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
> Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
> - return DAG.getConstant(Imm, MVT::i8);
> + return DAG.getConstant(Imm, DL, MVT::i8);
> }
>
> /// \brief Try to emit a blend instruction for a shuffle using bit math.
> @@ -6223,8 +6228,9 @@ static SDValue lowerVectorShuffleAsBitBl
> assert(VT.isInteger() && "Only supports integer vector types!");
> MVT EltVT = VT.getScalarType();
> int NumEltBits = EltVT.getSizeInBits();
> - SDValue Zero = DAG.getConstant(0, EltVT);
> - SDValue AllOnes = DAG.getConstant(APInt::getAllOnesValue(NumEltBits),
> EltVT);
> + SDValue Zero = DAG.getConstant(0, DL, EltVT);
> + SDValue AllOnes = DAG.getConstant(APInt::getAllOnesValue(NumEltBits),
> DL,
> + EltVT);
> SmallVector<SDValue, 16> MaskOps;
> for (int i = 0, Size = Mask.size(); i < Size; ++i) {
> if (Mask[i] != -1 && Mask[i] != i && Mask[i] != i + Size)
> @@ -6270,7 +6276,7 @@ static SDValue lowerVectorShuffleAsBlend
> case MVT::v4f64:
> case MVT::v8f32:
> return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V2,
> - DAG.getConstant(BlendMask, MVT::i8));
> + DAG.getConstant(BlendMask, DL, MVT::i8));
>
> case MVT::v4i64:
> case MVT::v8i32:
> @@ -6294,7 +6300,7 @@ static SDValue lowerVectorShuffleAsBlend
> V2 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V2);
> return DAG.getNode(ISD::BITCAST, DL, VT,
> DAG.getNode(X86ISD::BLENDI, DL, BlendVT, V1, V2,
> - DAG.getConstant(BlendMask,
> MVT::i8)));
> + DAG.getConstant(BlendMask, DL,
> MVT::i8)));
> }
> // FALLTHROUGH
> case MVT::v8i16: {
> @@ -6311,7 +6317,7 @@ static SDValue lowerVectorShuffleAsBlend
> V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
> return DAG.getNode(ISD::BITCAST, DL, VT,
> DAG.getNode(X86ISD::BLENDI, DL, MVT::v8i16, V1, V2,
> - DAG.getConstant(BlendMask, MVT::i8)));
> + DAG.getConstant(BlendMask, DL,
> MVT::i8)));
> }
>
> case MVT::v16i16: {
> @@ -6325,7 +6331,7 @@ static SDValue lowerVectorShuffleAsBlend
> if (RepeatedMask[i] >= 16)
> BlendMask |= 1u << i;
> return DAG.getNode(X86ISD::BLENDI, DL, MVT::v16i16, V1, V2,
> - DAG.getConstant(BlendMask, MVT::i8));
> + DAG.getConstant(BlendMask, DL, MVT::i8));
> }
> }
> // FALLTHROUGH
> @@ -6357,7 +6363,8 @@ static SDValue lowerVectorShuffleAsBlend
> for (int j = 0; j < Scale; ++j)
> VSELECTMask.push_back(
> Mask[i] < 0 ? DAG.getUNDEF(MVT::i8)
> - : DAG.getConstant(Mask[i] < Size ? -1 : 0,
> MVT::i8));
> + : DAG.getConstant(Mask[i] < Size ? -1 : 0, DL,
> + MVT::i8));
>
> V1 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V1);
> V2 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V2);
> @@ -6551,7 +6558,8 @@ static SDValue lowerVectorShuffleAsByteR
>
> return DAG.getNode(ISD::BITCAST, DL, VT,
> DAG.getNode(X86ISD::PALIGNR, DL, AlignVT, Hi, Lo,
> - DAG.getConstant(Rotation * Scale,
> MVT::i8)));
> + DAG.getConstant(Rotation * Scale, DL,
> + MVT::i8)));
> }
>
> assert(VT.getSizeInBits() == 128 &&
> @@ -6568,9 +6576,9 @@ static SDValue lowerVectorShuffleAsByteR
> Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Hi);
>
> SDValue LoShift = DAG.getNode(X86ISD::VSHLDQ, DL, MVT::v2i64, Lo,
> - DAG.getConstant(LoByteShift, MVT::i8));
> + DAG.getConstant(LoByteShift, DL,
> MVT::i8));
> SDValue HiShift = DAG.getNode(X86ISD::VSRLDQ, DL, MVT::v2i64, Hi,
> - DAG.getConstant(HiByteShift, MVT::i8));
> + DAG.getConstant(HiByteShift, DL,
> MVT::i8));
> return DAG.getNode(ISD::BITCAST, DL, VT,
> DAG.getNode(ISD::OR, DL, MVT::v2i64, LoShift,
> HiShift));
> }
> @@ -6629,8 +6637,9 @@ static SDValue lowerVectorShuffleAsBitMa
> MVT EltVT = VT.getScalarType();
> int NumEltBits = EltVT.getSizeInBits();
> MVT IntEltVT = MVT::getIntegerVT(NumEltBits);
> - SDValue Zero = DAG.getConstant(0, IntEltVT);
> - SDValue AllOnes = DAG.getConstant(APInt::getAllOnesValue(NumEltBits),
> IntEltVT);
> + SDValue Zero = DAG.getConstant(0, DL, IntEltVT);
> + SDValue AllOnes = DAG.getConstant(APInt::getAllOnesValue(NumEltBits),
> DL,
> + IntEltVT);
> if (EltVT.isFloatingPoint()) {
> Zero = DAG.getNode(ISD::BITCAST, DL, EltVT, Zero);
> AllOnes = DAG.getNode(ISD::BITCAST, DL, EltVT, AllOnes);
> @@ -6727,7 +6736,8 @@ static SDValue lowerVectorShuffleAsShift
> "Illegal integer vector type");
> V = DAG.getNode(ISD::BITCAST, DL, ShiftVT, V);
>
> - V = DAG.getNode(OpCode, DL, ShiftVT, V, DAG.getConstant(ShiftAmt,
> MVT::i8));
> + V = DAG.getNode(OpCode, DL, ShiftVT, V,
> + DAG.getConstant(ShiftAmt, DL, MVT::i8));
> return DAG.getNode(ISD::BITCAST, DL, VT, V);
> };
>
> @@ -6781,19 +6791,19 @@ static SDValue lowerVectorShuffleAsSpeci
> ISD::BITCAST, DL, VT,
> DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
> DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
> - getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
> + getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
> }
> if (AnyExt && EltBits == 16 && Scale > 2) {
> int PSHUFDMask[4] = {0, -1, 0, -1};
> InputV = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
> DAG.getNode(ISD::BITCAST, DL, MVT::v4i32,
> InputV),
> - getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG));
> + getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG));
> int PSHUFHWMask[4] = {1, -1, -1, -1};
> return DAG.getNode(
> ISD::BITCAST, DL, VT,
> DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16,
> DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, InputV),
> - getV4X86ShuffleImm8ForMask(PSHUFHWMask, DAG)));
> + getV4X86ShuffleImm8ForMask(PSHUFHWMask, DL, DAG)));
> }
>
> // If this would require more than 2 unpack instructions to expand, use
> @@ -6804,7 +6814,7 @@ static SDValue lowerVectorShuffleAsSpeci
> SDValue PSHUFBMask[16];
> for (int i = 0; i < 16; ++i)
> PSHUFBMask[i] =
> - DAG.getConstant((i % Scale == 0) ? i / Scale : 0x80, MVT::i8);
> + DAG.getConstant((i % Scale == 0) ? i / Scale : 0x80, DL,
> MVT::i8);
> InputV = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, InputV);
> return DAG.getNode(ISD::BITCAST, DL, VT,
> DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, InputV,
> @@ -7062,7 +7072,7 @@ static SDValue lowerVectorShuffleAsEleme
> V2 = DAG.getNode(
> X86ISD::VSHLDQ, DL, MVT::v2i64, V2,
> DAG.getConstant(
> - V2Index * EltVT.getSizeInBits()/8,
> + V2Index * EltVT.getSizeInBits()/8, DL,
>
> DAG.getTargetLoweringInfo().getScalarShiftAmountTy(MVT::v2i64)));
> V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
> }
> @@ -7222,7 +7232,7 @@ static SDValue lowerVectorShuffleAsInser
> // Insert the V2 element into the desired position.
> SDLoc DL(Op);
> return DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
> - DAG.getConstant(InsertPSMask, MVT::i8));
> + DAG.getConstant(InsertPSMask, DL, MVT::i8));
> }
>
> /// \brief Try to lower a shuffle as a permute of the inputs followed by
> an
> @@ -7372,11 +7382,11 @@ static SDValue lowerV2F64VectorShuffle(S
> // If we have AVX, we can use VPERMILPS which will allow folding a
> load
> // into the shuffle.
> return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v2f64, V1,
> - DAG.getConstant(SHUFPDMask, MVT::i8));
> + DAG.getConstant(SHUFPDMask, DL, MVT::i8));
> }
>
> - return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V1,
> - DAG.getConstant(SHUFPDMask, MVT::i8));
> + return DAG.getNode(X86ISD::SHUFP, DL, MVT::v2f64, V1, V1,
> + DAG.getConstant(SHUFPDMask, DL, MVT::i8));
> }
> assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
> assert(Mask[1] >= 2 && "Non-canonicalized blend!");
> @@ -7419,8 +7429,8 @@ static SDValue lowerV2F64VectorShuffle(S
> return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2f64, V1, V2);
>
> unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
> - return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V2,
> - DAG.getConstant(SHUFPDMask, MVT::i8));
> + return DAG.getNode(X86ISD::SHUFP, DL, MVT::v2f64, V1, V2,
> + DAG.getConstant(SHUFPDMask, DL, MVT::i8));
> }
>
> /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
> @@ -7455,8 +7465,8 @@ static SDValue lowerV2I64VectorShuffle(S
> std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
> return DAG.getNode(
> ISD::BITCAST, DL, MVT::v2i64,
> - DAG.getNode(X86ISD::PSHUFD, SDLoc(Op), MVT::v4i32, V1,
> - getV4X86ShuffleImm8ForMask(WidenedMask, DAG)));
> + DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
> + getV4X86ShuffleImm8ForMask(WidenedMask, DL, DAG)));
> }
> assert(Mask[0] != -1 && "No undef lanes in multi-input v2 shuffles!");
> assert(Mask[1] != -1 && "No undef lanes in multi-input v2 shuffles!");
> @@ -7590,7 +7600,7 @@ static SDValue lowerVectorShuffleWithSHU
> int V1Index = V2AdjIndex;
> int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
> V2 = DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
> - getV4X86ShuffleImm8ForMask(BlendMask, DAG));
> + getV4X86ShuffleImm8ForMask(BlendMask, DL, DAG));
>
> // Now proceed to reconstruct the final blend as we have the
> necessary
> // high or low half formed.
> @@ -7629,7 +7639,7 @@ static SDValue lowerVectorShuffleWithSHU
> (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
> (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
> V1 = DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
> - getV4X86ShuffleImm8ForMask(BlendMask, DAG));
> + getV4X86ShuffleImm8ForMask(BlendMask, DL, DAG));
>
> // Now we do a normal shuffle of V1 by giving V1 as both operands to
> // a blend.
> @@ -7641,7 +7651,7 @@ static SDValue lowerVectorShuffleWithSHU
> }
> }
> return DAG.getNode(X86ISD::SHUFP, DL, VT, LowV, HighV,
> - getV4X86ShuffleImm8ForMask(NewMask, DAG));
> + getV4X86ShuffleImm8ForMask(NewMask, DL, DAG));
> }
>
> /// \brief Lower 4-lane 32-bit floating point shuffles.
> @@ -7681,13 +7691,13 @@ static SDValue lowerV4F32VectorShuffle(S
> // If we have AVX, we can use VPERMILPS which will allow folding a
> load
> // into the shuffle.
> return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f32, V1,
> - getV4X86ShuffleImm8ForMask(Mask, DAG));
> + getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
> }
>
> // Otherwise, use a straight shuffle of a single input vector. We
> pass the
> // input vector to both operands to simulate this with a SHUFPS.
> return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
> - getV4X86ShuffleImm8ForMask(Mask, DAG));
> + getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
> }
>
> // There are special ways we can lower some single-element blends.
> However, we
> @@ -7773,7 +7783,7 @@ static SDValue lowerV4I32VectorShuffle(S
> Mask = UnpackHiMask;
>
> return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
> - getV4X86ShuffleImm8ForMask(Mask, DAG));
> + getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
> }
>
> // Try to use shift instructions.
> @@ -7990,7 +8000,7 @@ static SDValue lowerV8I16GeneralSingleIn
> std::swap(PSHUFHalfMask[FixFreeIdx % 4], PSHUFHalfMask[FixIdx %
> 4]);
> V = DAG.getNode(FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW,
> DL,
> MVT::v8i16, V,
> - getV4X86ShuffleImm8ForMask(PSHUFHalfMask, DAG));
> + getV4X86ShuffleImm8ForMask(PSHUFHalfMask, DL,
> DAG));
>
> for (int &M : Mask)
> if (M != -1 && M == FixIdx)
> @@ -8017,7 +8027,8 @@ static SDValue lowerV8I16GeneralSingleIn
> V = DAG.getNode(ISD::BITCAST, DL, VT,
> DAG.getNode(X86ISD::PSHUFD, DL, PSHUFDVT,
> DAG.getNode(ISD::BITCAST, DL, PSHUFDVT,
> V),
> - getV4X86ShuffleImm8ForMask(PSHUFDMask,
> DAG)));
> + getV4X86ShuffleImm8ForMask(PSHUFDMask, DL,
> + DAG)));
>
> // Adjust the mask to match the new locations of A and B.
> for (int &M : Mask)
> @@ -8253,15 +8264,16 @@ static SDValue lowerV8I16GeneralSingleIn
> // target half.
> if (!isNoopShuffleMask(PSHUFLMask))
> V = DAG.getNode(X86ISD::PSHUFLW, DL, VT, V,
> - getV4X86ShuffleImm8ForMask(PSHUFLMask, DAG));
> + getV4X86ShuffleImm8ForMask(PSHUFLMask, DL, DAG));
> if (!isNoopShuffleMask(PSHUFHMask))
> V = DAG.getNode(X86ISD::PSHUFHW, DL, VT, V,
> - getV4X86ShuffleImm8ForMask(PSHUFHMask, DAG));
> + getV4X86ShuffleImm8ForMask(PSHUFHMask, DL, DAG));
> if (!isNoopShuffleMask(PSHUFDMask))
> V = DAG.getNode(ISD::BITCAST, DL, VT,
> DAG.getNode(X86ISD::PSHUFD, DL, PSHUFDVT,
> DAG.getNode(ISD::BITCAST, DL, PSHUFDVT,
> V),
> - getV4X86ShuffleImm8ForMask(PSHUFDMask,
> DAG)));
> + getV4X86ShuffleImm8ForMask(PSHUFDMask, DL,
> + DAG)));
>
> // At this point, each half should contain all its inputs, and we can
> then
> // just shuffle them into their final position.
> @@ -8275,7 +8287,7 @@ static SDValue lowerV8I16GeneralSingleIn
> // Do a half shuffle for the low mask.
> if (!isNoopShuffleMask(LoMask))
> V = DAG.getNode(X86ISD::PSHUFLW, DL, VT, V,
> - getV4X86ShuffleImm8ForMask(LoMask, DAG));
> + getV4X86ShuffleImm8ForMask(LoMask, DL, DAG));
>
> // Do a half shuffle with the high mask after shifting its values down.
> for (int &M : HiMask)
> @@ -8283,7 +8295,7 @@ static SDValue lowerV8I16GeneralSingleIn
> M -= 4;
> if (!isNoopShuffleMask(HiMask))
> V = DAG.getNode(X86ISD::PSHUFHW, DL, VT, V,
> - getV4X86ShuffleImm8ForMask(HiMask, DAG));
> + getV4X86ShuffleImm8ForMask(HiMask, DL, DAG));
>
> return V;
> }
> @@ -8313,8 +8325,8 @@ static SDValue lowerVectorShuffleAsPSHUF
> : (Mask[i / Scale] - Size) * Scale + i % Scale;
> if (Zeroable[i / Scale])
> V1Idx = V2Idx = ZeroMask;
> - V1Mask[i] = DAG.getConstant(V1Idx, MVT::i8);
> - V2Mask[i] = DAG.getConstant(V2Idx, MVT::i8);
> + V1Mask[i] = DAG.getConstant(V1Idx, DL, MVT::i8);
> + V2Mask[i] = DAG.getConstant(V2Idx, DL, MVT::i8);
> V1InUse |= (ZeroMask != V1Idx);
> V2InUse |= (ZeroMask != V2Idx);
> }
> @@ -8757,7 +8769,7 @@ static SDValue lowerV16I8VectorShuffle(S
> MVT MaskVTs[] = { MVT::v8i16, MVT::v4i32, MVT::v2i64 };
> SDValue ByteClearMask =
> DAG.getNode(ISD::BITCAST, DL, MVT::v16i8,
> - DAG.getConstant(0xFF, MaskVTs[NumEvenDrops - 1]));
> + DAG.getConstant(0xFF, DL, MaskVTs[NumEvenDrops - 1]));
> V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);
> if (!IsSingleInput)
> V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
> @@ -8803,7 +8815,7 @@ static SDValue lowerV16I8VectorShuffle(S
> // Use a mask to drop the high bytes.
> VLoHalf = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
> VLoHalf = DAG.getNode(ISD::AND, DL, MVT::v8i16, VLoHalf,
> - DAG.getConstant(0x00FF, MVT::v8i16));
> + DAG.getConstant(0x00FF, DL, MVT::v8i16));
>
> // This will be a single vector shuffle instead of a blend so nuke
> VHiHalf.
> VHiHalf = DAG.getUNDEF(MVT::v8i16);
> @@ -8949,9 +8961,9 @@ static SDValue splitAndLowerVectorShuffl
> auto *BV = dyn_cast<BuildVectorSDNode>(V);
> if (!BV) {
> LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigSplitVT, V,
> - DAG.getIntPtrConstant(0));
> + DAG.getIntPtrConstant(0, DL));
> HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigSplitVT, V,
> - DAG.getIntPtrConstant(OrigSplitNumElements));
> + DAG.getIntPtrConstant(OrigSplitNumElements, DL));
> } else {
>
> SmallVector<SDValue, 16> LoOps, HiOps;
> @@ -9140,7 +9152,7 @@ static SDValue lowerVectorShuffleAsLaneP
> // allow folding it into a memory operand.
> unsigned PERMMask = 3 | 2 << 4;
> SDValue Flipped = DAG.getNode(X86ISD::VPERM2X128, DL, VT,
> DAG.getUNDEF(VT),
> - V1, DAG.getConstant(PERMMask, MVT::i8));
> + V1, DAG.getConstant(PERMMask, DL,
> MVT::i8));
> return DAG.getVectorShuffle(VT, DL, V1, Flipped, FlippedBlendMask);
> }
>
> @@ -9177,9 +9189,10 @@ static SDValue lowerV2X128VectorShuffle(
> MVT SubVT = MVT::getVectorVT(VT.getVectorElementType(),
> VT.getVectorNumElements() / 2);
> SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
> - DAG.getIntPtrConstant(0));
> + DAG.getIntPtrConstant(0, DL));
> SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT,
> - OnlyUsesV1 ? V1 : V2,
> DAG.getIntPtrConstant(0));
> + OnlyUsesV1 ? V1 : V2,
> + DAG.getIntPtrConstant(0, DL));
> return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
> }
> }
> @@ -9228,7 +9241,7 @@ static SDValue lowerV2X128VectorShuffle(
> }
>
> return DAG.getNode(X86ISD::VPERM2X128, DL, VT, V1, V2,
> - DAG.getConstant(PermMask, MVT::i8));
> + DAG.getConstant(PermMask, DL, MVT::i8));
> }
>
> /// \brief Lower a vector shuffle by first fixing the 128-bit lanes and
> then
> @@ -9364,13 +9377,13 @@ static SDValue lowerV4F64VectorShuffle(S
> unsigned VPERMILPMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1) |
> ((Mask[2] == 3) << 2) | ((Mask[3] == 3) <<
> 3);
> return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f64, V1,
> - DAG.getConstant(VPERMILPMask, MVT::i8));
> + DAG.getConstant(VPERMILPMask, DL, MVT::i8));
> }
>
> // With AVX2 we have direct support for this permutation.
> if (Subtarget->hasAVX2())
> return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4f64, V1,
> - getV4X86ShuffleImm8ForMask(Mask, DAG));
> + getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
>
> // Otherwise, fall back.
> return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v4f64, V1,
> V2, Mask,
> @@ -9400,7 +9413,7 @@ static SDValue lowerV4F64VectorShuffle(S
> unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 5) << 1) |
> ((Mask[2] == 3) << 2) | ((Mask[3] == 7) << 3);
> return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V1, V2,
> - DAG.getConstant(SHUFPDMask, MVT::i8));
> + DAG.getConstant(SHUFPDMask, DL, MVT::i8));
> }
> if ((Mask[0] == -1 || (Mask[0] >= 4 && Mask[0] < 6)) &&
> (Mask[1] == -1 || Mask[1] < 2) &&
> @@ -9409,7 +9422,7 @@ static SDValue lowerV4F64VectorShuffle(S
> unsigned SHUFPDMask = (Mask[0] == 5) | ((Mask[1] == 1) << 1) |
> ((Mask[2] == 7) << 2) | ((Mask[3] == 3) << 3);
> return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V2, V1,
> - DAG.getConstant(SHUFPDMask, MVT::i8));
> + DAG.getConstant(SHUFPDMask, DL, MVT::i8));
> }
>
> // Try to simplify this by merging 128-bit lanes to enable a lane-based
> @@ -9476,7 +9489,7 @@ static SDValue lowerV4I64VectorShuffle(S
> ISD::BITCAST, DL, MVT::v4i64,
> DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32,
> DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, V1),
> - getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
> + getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
> }
> }
>
> @@ -9484,7 +9497,7 @@ static SDValue lowerV4I64VectorShuffle(S
> // lanes.
> if (isSingleInputShuffleMask(Mask))
> return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4i64, V1,
> - getV4X86ShuffleImm8ForMask(Mask, DAG));
> + getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
>
> // Try to use shift instructions.
> if (SDValue Shift =
> @@ -9554,7 +9567,7 @@ static SDValue lowerV8F32VectorShuffle(S
>
> if (isSingleInputShuffleMask(Mask))
> return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v8f32, V1,
> - getV4X86ShuffleImm8ForMask(RepeatedMask, DAG));
> + getV4X86ShuffleImm8ForMask(RepeatedMask, DL,
> DAG));
>
> // Use dedicated unpack instructions for masks that match their
> pattern.
> if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 1, 9, 4, 12, 5, 13}))
> @@ -9581,7 +9594,7 @@ static SDValue lowerV8F32VectorShuffle(S
> SDValue VPermMask[8];
> for (int i = 0; i < 8; ++i)
> VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
> - : DAG.getConstant(Mask[i], MVT::i32);
> + : DAG.getConstant(Mask[i], DL, MVT::i32);
> if (!is128BitLaneCrossingShuffleMask(MVT::v8f32, Mask))
> return DAG.getNode(
> X86ISD::VPERMILPV, DL, MVT::v8f32, V1,
> @@ -9654,7 +9667,7 @@ static SDValue lowerV8I32VectorShuffle(S
> assert(RepeatedMask.size() == 4 && "Unexpected repeated mask size!");
> if (isSingleInputShuffleMask(Mask))
> return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32, V1,
> - getV4X86ShuffleImm8ForMask(RepeatedMask, DAG));
> + getV4X86ShuffleImm8ForMask(RepeatedMask, DL,
> DAG));
>
> // Use dedicated unpack instructions for masks that match their
> pattern.
> if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 1, 9, 4, 12, 5, 13}))
> @@ -9682,7 +9695,7 @@ static SDValue lowerV8I32VectorShuffle(S
> SDValue VPermMask[8];
> for (int i = 0; i < 8; ++i)
> VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
> - : DAG.getConstant(Mask[i], MVT::i32);
> + : DAG.getConstant(Mask[i], DL, MVT::i32);
> return DAG.getNode(
> X86ISD::VPERMV, DL, MVT::v8i32,
> DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask), V1);
> @@ -9779,8 +9792,8 @@ static SDValue lowerV16I16VectorShuffle(
>
> int M = i < 8 ? Mask[i] : Mask[i] - 8;
> assert(M >= 0 && M < 8 && "Invalid single-input mask!");
> - PSHUFBMask[2 * i] = DAG.getConstant(2 * M, MVT::i8);
> - PSHUFBMask[2 * i + 1] = DAG.getConstant(2 * M + 1, MVT::i8);
> + PSHUFBMask[2 * i] = DAG.getConstant(2 * M, DL, MVT::i8);
> + PSHUFBMask[2 * i + 1] = DAG.getConstant(2 * M + 1, DL, MVT::i8);
> }
> return DAG.getNode(
> ISD::BITCAST, DL, MVT::v16i16,
> @@ -9871,7 +9884,8 @@ static SDValue lowerV32I8VectorShuffle(S
> PSHUFBMask[i] =
> Mask[i] < 0
> ? DAG.getUNDEF(MVT::i8)
> - : DAG.getConstant(Mask[i] < 16 ? Mask[i] : Mask[i] - 16,
> MVT::i8);
> + : DAG.getConstant(Mask[i] < 16 ? Mask[i] : Mask[i] - 16, DL,
> + MVT::i8);
>
> return DAG.getNode(
> X86ISD::PSHUFB, DL, MVT::v32i8, V1,
> @@ -10469,11 +10483,11 @@ X86TargetLowering::ExtractBitFromMaskVec
> rc = getRegClassFor(MVT::v16i1);
> unsigned MaxSift = rc->getSize()*8 - 1;
> Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
> - DAG.getConstant(MaxSift - IdxVal, MVT::i8));
> + DAG.getConstant(MaxSift - IdxVal, dl, MVT::i8));
> Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
> - DAG.getConstant(MaxSift, MVT::i8));
> + DAG.getConstant(MaxSift, dl, MVT::i8));
> return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
> - DAG.getIntPtrConstant(0));
> + DAG.getIntPtrConstant(0, dl));
> }
>
> SDValue
> @@ -10500,10 +10514,10 @@ X86TargetLowering::LowerEXTRACT_VECTOR_E
> Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
> SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
> getZeroVector(MaskVT, Subtarget, DAG, dl),
> - Idx, DAG.getConstant(0, getPointerTy()));
> + Idx, DAG.getConstant(0, dl,
> getPointerTy()));
> SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
> return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(),
> - Perm, DAG.getConstant(0, getPointerTy()));
> + Perm, DAG.getConstant(0, dl, getPointerTy()));
> }
> return SDValue();
> }
> @@ -10523,7 +10537,7 @@ X86TargetLowering::LowerEXTRACT_VECTOR_E
> // IdxVal -= NumElems/2;
> IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
> return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(),
> Vec,
> - DAG.getConstant(IdxVal, MVT::i32));
> + DAG.getConstant(IdxVal, dl, MVT::i32));
> }
>
> assert(VecVT.is128BitVector() && "Unexpected vector length");
> @@ -10565,7 +10579,7 @@ X86TargetLowering::LowerEXTRACT_VECTOR_E
> SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
> DAG.getUNDEF(VVT), Mask);
> return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
> - DAG.getIntPtrConstant(0));
> + DAG.getIntPtrConstant(0, dl));
> }
>
> if (VT.getSizeInBits() == 64) {
> @@ -10584,7 +10598,7 @@ X86TargetLowering::LowerEXTRACT_VECTOR_E
> SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
> DAG.getUNDEF(VVT), Mask);
> return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
> - DAG.getIntPtrConstant(0));
> + DAG.getIntPtrConstant(0, dl));
> }
>
> return SDValue();
> @@ -10615,13 +10629,13 @@ X86TargetLowering::InsertBitToMaskVector
> SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
> if (Vec.getOpcode() == ISD::UNDEF)
> return DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
> - DAG.getConstant(IdxVal, MVT::i8));
> + DAG.getConstant(IdxVal, dl, MVT::i8));
> const TargetRegisterClass* rc = getRegClassFor(VecVT);
> unsigned MaxSift = rc->getSize()*8 - 1;
> EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
> - DAG.getConstant(MaxSift, MVT::i8));
> + DAG.getConstant(MaxSift, dl, MVT::i8));
> EltInVec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, EltInVec,
> - DAG.getConstant(MaxSift - IdxVal, MVT::i8));
> + DAG.getConstant(MaxSift - IdxVal, dl, MVT::i8));
> return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
> }
>
> @@ -10654,7 +10668,7 @@ SDValue X86TargetLowering::LowerINSERT_V
> if ((Subtarget->hasAVX() && (EltVT == MVT::f64 || EltVT ==
> MVT::f32)) ||
> (Subtarget->hasAVX2() && EltVT == MVT::i32)) {
> SDValue N1Vec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, N1);
> - N2 = DAG.getIntPtrConstant(1);
> + N2 = DAG.getIntPtrConstant(1, dl);
> return DAG.getNode(X86ISD::BLENDI, dl, VT, N0, N1Vec, N2);
> }
> }
> @@ -10667,7 +10681,7 @@ SDValue X86TargetLowering::LowerINSERT_V
> unsigned IdxIn128 = IdxVal - (IdxVal / NumEltsIn128) * NumEltsIn128;
>
> V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
> - DAG.getConstant(IdxIn128, MVT::i32));
> + DAG.getConstant(IdxIn128, dl, MVT::i32));
>
> // Insert the changed part back into the bigger vector
> return Insert128BitVector(N0, V, IdxVal, DAG, dl);
> @@ -10689,7 +10703,7 @@ SDValue X86TargetLowering::LowerINSERT_V
> if (N1.getValueType() != MVT::i32)
> N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
> if (N2.getValueType() != MVT::i32)
> - N2 = DAG.getIntPtrConstant(IdxVal);
> + N2 = DAG.getIntPtrConstant(IdxVal, dl);
> return DAG.getNode(Opc, dl, VT, N0, N1, N2);
> }
>
> @@ -10713,11 +10727,11 @@ SDValue X86TargetLowering::LowerINSERT_V
> // But if optimizing for size and there's a load folding
> opportunity,
> // generate insertps because blendps does not have a 32-bit memory
> // operand form.
> - N2 = DAG.getIntPtrConstant(1);
> + N2 = DAG.getIntPtrConstant(1, dl);
> N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
> return DAG.getNode(X86ISD::BLENDI, dl, VT, N0, N1, N2);
> }
> - N2 = DAG.getIntPtrConstant(IdxVal << 4);
> + N2 = DAG.getIntPtrConstant(IdxVal << 4, dl);
> // Create this as a scalar to vector..
> N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
> return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
> @@ -10738,7 +10752,7 @@ SDValue X86TargetLowering::LowerINSERT_V
> if (N1.getValueType() != MVT::i32)
> N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
> if (N2.getValueType() != MVT::i32)
> - N2 = DAG.getIntPtrConstant(IdxVal);
> + N2 = DAG.getIntPtrConstant(IdxVal, dl);
> return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
> }
> return SDValue();
> @@ -10847,10 +10861,10 @@ static SDValue LowerINSERT_SUBVECTOR(SDV
> if (OpVT.getVectorElementType() == MVT::i1) {
> if (IdxVal == 0 && Vec.getOpcode() == ISD::UNDEF) // the operation
> is legal
> return Op;
> - SDValue ZeroIdx = DAG.getIntPtrConstant(0);
> + SDValue ZeroIdx = DAG.getIntPtrConstant(0, dl);
> SDValue Undef = DAG.getUNDEF(OpVT);
> unsigned NumElems = OpVT.getVectorNumElements();
> - SDValue ShiftBits = DAG.getConstant(NumElems/2, MVT::i8);
> + SDValue ShiftBits = DAG.getConstant(NumElems/2, dl, MVT::i8);
>
> if (IdxVal == OpVT.getVectorNumElements() / 2) {
> // Zero upper bits of the Vec
> @@ -11065,7 +11079,7 @@ X86TargetLowering::LowerGlobalAddress(co
> // addition for it.
> if (Offset != 0)
> Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
> - DAG.getConstant(Offset, getPointerTy()));
> + DAG.getConstant(Offset, dl, getPointerTy()));
>
> return Result;
> }
> @@ -11180,7 +11194,7 @@ static SDValue LowerToTLSExecModel(Globa
> is64Bit ? 257 :
> 256));
>
> SDValue ThreadPointer =
> - DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0),
> + DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0,
> dl),
> MachinePointerInfo(Ptr), false, false, false, 0);
>
> unsigned char OperandFlags = 0;
> @@ -11322,9 +11336,9 @@ X86TargetLowering::LowerGlobalTLSAddress
>
> SDValue TlsArray =
> Subtarget->is64Bit()
> - ? DAG.getIntPtrConstant(0x58)
> + ? DAG.getIntPtrConstant(0x58, dl)
> : (Subtarget->isTargetWindowsGNU()
> - ? DAG.getIntPtrConstant(0x2C)
> + ? DAG.getIntPtrConstant(0x2C, dl)
> : DAG.getExternalSymbol("_tls_array", getPointerTy()));
>
> SDValue ThreadPointer =
> @@ -11341,7 +11355,7 @@ X86TargetLowering::LowerGlobalTLSAddress
> IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX,
> MachinePointerInfo(),
> false, false, false, 0);
>
> - SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
> + SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
> dl,
> getPointerTy());
> IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
>
> @@ -11378,10 +11392,10 @@ static SDValue LowerShiftParts(SDValue O
> // generic ISD nodes haven't. Insert an AND to be safe, it's optimized
> away
> // during isel.
> SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
> - DAG.getConstant(VTBits - 1, MVT::i8));
> + DAG.getConstant(VTBits - 1, dl,
> MVT::i8));
> SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
> - DAG.getConstant(VTBits - 1, MVT::i8))
> - : DAG.getConstant(0, VT);
> + DAG.getConstant(VTBits - 1, dl,
> MVT::i8))
> + : DAG.getConstant(0, dl, VT);
>
> SDValue Tmp2, Tmp3;
> if (Op.getOpcode() == ISD::SHL_PARTS) {
> @@ -11396,12 +11410,12 @@ static SDValue LowerShiftParts(SDValue O
> // rely on the results of shld/shrd. Insert a test and select the
> appropriate
> // values for large shift amounts.
> SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
> - DAG.getConstant(VTBits, MVT::i8));
> + DAG.getConstant(VTBits, dl, MVT::i8));
> SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
> - AndNode, DAG.getConstant(0, MVT::i8));
> + AndNode, DAG.getConstant(0, dl, MVT::i8));
>
> SDValue Hi, Lo;
> - SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
> + SDValue CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
> SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
> SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
>
> @@ -11580,7 +11594,7 @@ SDValue X86TargetLowering::LowerUINT_TO_
> }
>
> return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
> - DAG.getIntPtrConstant(0));
> + DAG.getIntPtrConstant(0, dl));
> }
>
> // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
> @@ -11588,7 +11602,7 @@ SDValue X86TargetLowering::LowerUINT_TO_
> SelectionDAG &DAG) const {
> SDLoc dl(Op);
> // FP constant to bias correct the final result.
> - SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
> + SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
> dl,
> MVT::f64);
>
> // Load the 32-bit value into an XMM register.
> @@ -11600,7 +11614,7 @@ SDValue X86TargetLowering::LowerUINT_TO_
>
> Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
> DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
> - DAG.getIntPtrConstant(0));
> + DAG.getIntPtrConstant(0, dl));
>
> // Or the load with the bias.
> SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
> @@ -11612,7 +11626,7 @@ SDValue X86TargetLowering::LowerUINT_TO_
> MVT::v2f64, Bias)));
> Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
> DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
> - DAG.getIntPtrConstant(0));
> + DAG.getIntPtrConstant(0, dl));
>
> // Subtract the bias.
> SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
> @@ -11622,7 +11636,7 @@ SDValue X86TargetLowering::LowerUINT_TO_
>
> if (DestVT.bitsLT(MVT::f64))
> return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
> - DAG.getIntPtrConstant(0));
> + DAG.getIntPtrConstant(0, dl));
> if (DestVT.bitsGT(MVT::f64))
> return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
>
> @@ -11667,20 +11681,20 @@ static SDValue lowerUINT_TO_FP_vXi32(SDV
> // -- v >> 16
>
> // Create the splat vector for 0x4b000000.
> - SDValue CstLow = DAG.getConstant(0x4b000000, MVT::i32);
> + SDValue CstLow = DAG.getConstant(0x4b000000, DL, MVT::i32);
> SDValue CstLowArray[] = {CstLow, CstLow, CstLow, CstLow,
> CstLow, CstLow, CstLow, CstLow};
> SDValue VecCstLow = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
> makeArrayRef(&CstLowArray[0], NumElts));
> // Create the splat vector for 0x53000000.
> - SDValue CstHigh = DAG.getConstant(0x53000000, MVT::i32);
> + SDValue CstHigh = DAG.getConstant(0x53000000, DL, MVT::i32);
> SDValue CstHighArray[] = {CstHigh, CstHigh, CstHigh, CstHigh,
> CstHigh, CstHigh, CstHigh, CstHigh};
> SDValue VecCstHigh = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
> makeArrayRef(&CstHighArray[0],
> NumElts));
>
> // Create the right shift.
> - SDValue CstShift = DAG.getConstant(16, MVT::i32);
> + SDValue CstShift = DAG.getConstant(16, DL, MVT::i32);
> SDValue CstShiftArray[] = {CstShift, CstShift, CstShift, CstShift,
> CstShift, CstShift, CstShift, CstShift};
> SDValue VecCstShift = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
> @@ -11697,7 +11711,7 @@ static SDValue lowerUINT_TO_FP_vXi32(SDV
> // Low will be bitcasted right away, so do not bother bitcasting back
> to its
> // original type.
> Low = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecBitcast,
> - VecCstLowBitcast, DAG.getConstant(0xaa, MVT::i32));
> + VecCstLowBitcast, DAG.getConstant(0xaa, DL,
> MVT::i32));
> // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
> // (uint4) 0x53000000, 0xaa);
> SDValue VecCstHighBitcast =
> @@ -11707,9 +11721,9 @@ static SDValue lowerUINT_TO_FP_vXi32(SDV
> // High will be bitcasted right away, so do not bother bitcasting
> back to
> // its original type.
> High = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecShiftBitcast,
> - VecCstHighBitcast, DAG.getConstant(0xaa,
> MVT::i32));
> + VecCstHighBitcast, DAG.getConstant(0xaa, DL,
> MVT::i32));
> } else {
> - SDValue CstMask = DAG.getConstant(0xffff, MVT::i32);
> + SDValue CstMask = DAG.getConstant(0xffff, DL, MVT::i32);
> SDValue VecCstMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
> CstMask,
> CstMask, CstMask, CstMask);
> // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
> @@ -11722,7 +11736,7 @@ static SDValue lowerUINT_TO_FP_vXi32(SDV
>
> // Create the vector constant for -(0x1.0p39f + 0x1.0p23f).
> SDValue CstFAdd = DAG.getConstantFP(
> - APFloat(APFloat::IEEEsingle, APInt(32, 0xD3000080)), MVT::f32);
> + APFloat(APFloat::IEEEsingle, APInt(32, 0xD3000080)), DL, MVT::f32);
> SDValue CstFAddArray[] = {CstFAdd, CstFAdd, CstFAdd, CstFAdd,
> CstFAdd, CstFAdd, CstFAdd, CstFAdd};
> SDValue VecCstFAdd = DAG.getNode(ISD::BUILD_VECTOR, DL, VecFloatVT,
> @@ -11787,13 +11801,13 @@ SDValue X86TargetLowering::LowerUINT_TO_
> // Make a 64-bit buffer, and use it to build an FILD.
> SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
> if (SrcVT == MVT::i32) {
> - SDValue WordOff = DAG.getConstant(4, getPointerTy());
> + SDValue WordOff = DAG.getConstant(4, dl, getPointerTy());
> SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
> getPointerTy(), StackSlot, WordOff);
> SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl,
> Op.getOperand(0),
> StackSlot, MachinePointerInfo(),
> false, false, 0);
> - SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0,
> MVT::i32),
> + SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, dl,
> MVT::i32),
> OffsetSlot, MachinePointerInfo(),
> false, false, 0);
> SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
> @@ -11825,8 +11839,8 @@ SDValue X86TargetLowering::LowerUINT_TO_
> // Check whether the sign bit is set.
> SDValue SignSet = DAG.getSetCC(dl,
> getSetCCResultType(*DAG.getContext(),
> MVT::i64),
> - Op.getOperand(0), DAG.getConstant(0,
> MVT::i64),
> - ISD::SETLT);
> + Op.getOperand(0),
> + DAG.getConstant(0, dl, MVT::i64),
> ISD::SETLT);
>
> // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo
> bits.
> SDValue FudgePtr = DAG.getConstantPool(
> @@ -11834,8 +11848,8 @@ SDValue X86TargetLowering::LowerUINT_TO_
> getPointerTy());
>
> // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
> - SDValue Zero = DAG.getIntPtrConstant(0);
> - SDValue Four = DAG.getIntPtrConstant(4);
> + SDValue Zero = DAG.getIntPtrConstant(0, dl);
> + SDValue Four = DAG.getIntPtrConstant(4, dl);
> SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(),
> SignSet,
> Zero, Four);
> FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
> @@ -11847,7 +11861,8 @@ SDValue X86TargetLowering::LowerUINT_TO_
> MVT::f32, false, false, false, 4);
> // Extend everything to 80 bits to force it to be done on x87.
> SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
> - return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add,
> DAG.getIntPtrConstant(0));
> + return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add,
> + DAG.getIntPtrConstant(0, dl));
> }
>
> std::pair<SDValue,SDValue>
> @@ -12003,7 +12018,7 @@ static SDValue LowerZERO_EXTEND_AVX512(
> const TargetLowering &TLI = DAG.getTargetLoweringInfo();
> // Now we have only mask extension
> assert(InVT.getVectorElementType() == MVT::i1);
> - SDValue Cst = DAG.getTargetConstant(1, ExtVT.getScalarType());
> + SDValue Cst = DAG.getTargetConstant(1, DL, ExtVT.getScalarType());
> const Constant *C = cast<ConstantSDNode>(Cst)->getConstantIntValue();
> SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
> unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
> @@ -12096,7 +12111,7 @@ SDValue X86TargetLowering::LowerTRUNCATE
> InVT = ExtVT;
> }
>
> - SDValue Cst = DAG.getTargetConstant(1, InVT.getVectorElementType());
> + SDValue Cst = DAG.getTargetConstant(1, DL,
> InVT.getVectorElementType());
> const Constant *C = cast<ConstantSDNode>(Cst)->getConstantIntValue();
> SDValue CP = DAG.getConstantPool(C, getPointerTy());
> unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
> @@ -12116,13 +12131,13 @@ SDValue X86TargetLowering::LowerTRUNCATE
> In = DAG.getVectorShuffle(MVT::v8i32, DL, In,
> DAG.getUNDEF(MVT::v8i32),
> ShufMask);
> return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
> - DAG.getIntPtrConstant(0));
> + DAG.getIntPtrConstant(0, DL));
> }
>
> SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
> - DAG.getIntPtrConstant(0));
> + DAG.getIntPtrConstant(0, DL));
> SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
> - DAG.getIntPtrConstant(2));
> + DAG.getIntPtrConstant(2, DL));
> OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
> OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
> static const int ShufMask[] = {0, 2, 4, 6};
> @@ -12136,16 +12151,16 @@ SDValue X86TargetLowering::LowerTRUNCATE
>
> SmallVector<SDValue,32> pshufbMask;
> for (unsigned i = 0; i < 2; ++i) {
> - pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
> - pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
> - pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
> - pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
> - pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
> - pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
> - pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
> - pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
> + pshufbMask.push_back(DAG.getConstant(0x0, DL, MVT::i8));
> + pshufbMask.push_back(DAG.getConstant(0x1, DL, MVT::i8));
> + pshufbMask.push_back(DAG.getConstant(0x4, DL, MVT::i8));
> + pshufbMask.push_back(DAG.getConstant(0x5, DL, MVT::i8));
> + pshufbMask.push_back(DAG.getConstant(0x8, DL, MVT::i8));
> + pshufbMask.push_back(DAG.getConstant(0x9, DL, MVT::i8));
> + pshufbMask.push_back(DAG.getConstant(0xc, DL, MVT::i8));
> + pshufbMask.push_back(DAG.getConstant(0xd, DL, MVT::i8));
> for (unsigned j = 0; j < 8; ++j)
> - pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
> + pshufbMask.push_back(DAG.getConstant(0x80, DL, MVT::i8));
> }
> SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8,
> pshufbMask);
> In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
> @@ -12155,15 +12170,15 @@ SDValue X86TargetLowering::LowerTRUNCATE
> In = DAG.getVectorShuffle(MVT::v4i64, DL, In,
> DAG.getUNDEF(MVT::v4i64),
> &ShufMask[0]);
> In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
> - DAG.getIntPtrConstant(0));
> + DAG.getIntPtrConstant(0, DL));
> return DAG.getNode(ISD::BITCAST, DL, VT, In);
> }
>
> SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
> - DAG.getIntPtrConstant(0));
> + DAG.getIntPtrConstant(0, DL));
>
> SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
> - DAG.getIntPtrConstant(4));
> + DAG.getIntPtrConstant(4, DL));
>
> OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo);
> OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi);
> @@ -12202,7 +12217,7 @@ SDValue X86TargetLowering::LowerTRUNCATE
> DAG.getNode(ISD::BITCAST, DL, NVT, In),
> DAG.getUNDEF(NVT), &MaskVec[0]);
> return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
> - DAG.getIntPtrConstant(0));
> + DAG.getIntPtrConstant(0, DL));
> }
>
> SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
> @@ -12339,7 +12354,7 @@ static SDValue LowerFCOPYSIGN(SDValue Op
> }
> // And if it is bigger, shrink it first.
> if (SrcVT.bitsGT(VT)) {
> - Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1,
> DAG.getIntPtrConstant(1));
> + Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1,
> DAG.getIntPtrConstant(1, dl));
> SrcVT = VT;
> }
>
> @@ -12398,8 +12413,8 @@ static SDValue LowerFGETSIGN(SDValue Op,
>
> // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
> SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
> - DAG.getConstant(1, VT));
> - return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
> + DAG.getConstant(1, dl, VT));
> + return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, dl,
> VT));
> }
>
> // Check whether an OR'd tree is PTEST-able.
> @@ -12520,7 +12535,7 @@ SDValue X86TargetLowering::EmitTest(SDVa
> if (Op.getValueType() == MVT::i1) {
> SDValue ExtOp = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i8, Op);
> return DAG.getNode(X86ISD::CMP, dl, MVT::i32, ExtOp,
> - DAG.getConstant(0, MVT::i8));
> + DAG.getConstant(0, dl, MVT::i8));
> }
> // CF and OF aren't always set the way we want. Determine which
> // of these we need.
> @@ -12564,7 +12579,7 @@ SDValue X86TargetLowering::EmitTest(SDVa
> // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
> // DAG.getConstant(0, MVT::i1));
> return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
> - DAG.getConstant(0, Op.getValueType()));
> + DAG.getConstant(0, dl, Op.getValueType()));
> }
> unsigned Opcode = 0;
> unsigned NumOperands = 0;
> @@ -12652,7 +12667,7 @@ SDValue X86TargetLowering::EmitTest(SDVa
> if (!Mask.isSignedIntN(32)) // Avoid large immediates.
> break;
> SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
> - DAG.getConstant(Mask, VT));
> + DAG.getConstant(Mask, dl, VT));
> DAG.ReplaceAllUsesWith(Op, New);
> Op = New;
> }
> @@ -12738,7 +12753,7 @@ SDValue X86TargetLowering::EmitTest(SDVa
> if (Opcode == 0)
> // Emit a CMP with 0, which is the TEST pattern.
> return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
> - DAG.getConstant(0, Op.getValueType()));
> + DAG.getConstant(0, dl, Op.getValueType()));
>
> SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
> SmallVector<SDValue, 4> Ops(Op->op_begin(), Op->op_begin() +
> NumOperands);
> @@ -12803,7 +12818,7 @@ SDValue X86TargetLowering::ConvertCmpIfN
> SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
> SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16,
> TruncFPSW);
> SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
> - DAG.getConstant(8, MVT::i8));
> + DAG.getConstant(8, dl, MVT::i8));
> SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
> return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
> }
> @@ -12926,7 +12941,7 @@ SDValue X86TargetLowering::LowerToBT(SDV
> // Use BT if the immediate can't be encoded in a TEST instruction.
> if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
> LHS = AndLHS;
> - RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
> + RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), dl,
> LHS.getValueType());
> }
> }
>
> @@ -12948,7 +12963,7 @@ SDValue X86TargetLowering::LowerToBT(SDV
> SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
> X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
> return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
> - DAG.getConstant(Cond, MVT::i8), BT);
> + DAG.getConstant(Cond, dl, MVT::i8), BT);
> }
>
> return SDValue();
> @@ -13040,16 +13055,16 @@ static SDValue LowerBoolVSETCC_AVX512(SD
> "Unexpected type for boolean compare operation");
> ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
> SDValue NotOp0 = DAG.getNode(ISD::XOR, dl, VT, Op0,
> - DAG.getConstant(-1, VT));
> + DAG.getConstant(-1, dl, VT));
> SDValue NotOp1 = DAG.getNode(ISD::XOR, dl, VT, Op1,
> - DAG.getConstant(-1, VT));
> + DAG.getConstant(-1, dl, VT));
> switch (SetCCOpcode) {
> default: llvm_unreachable("Unexpected SETCC condition");
> case ISD::SETNE:
> // (x != y) -> ~(x ^ y)
> return DAG.getNode(ISD::XOR, dl, VT,
> DAG.getNode(ISD::XOR, dl, VT, Op0, Op1),
> - DAG.getConstant(-1, VT));
> + DAG.getConstant(-1, dl, VT));
> case ISD::SETEQ:
> // (x == y) -> (x ^ y)
> return DAG.getNode(ISD::XOR, dl, VT, Op0, Op1);
> @@ -13109,7 +13124,7 @@ static SDValue LowerIntVSETCC_AVX512(SDV
> return DAG.getNode(Opc, dl, VT, Op0, Op1);
> Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
> return DAG.getNode(Opc, dl, VT, Op0, Op1,
> - DAG.getConstant(SSECC, MVT::i8));
> + DAG.getConstant(SSECC, dl, MVT::i8));
> }
>
> /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
> @@ -13136,7 +13151,7 @@ static SDValue ChangeVSETULTtoVSETULE(SD
> if (Val == 0)
> return SDValue();
>
> - ULTOp1.push_back(DAG.getConstant(Val - 1, EVT));
> + ULTOp1.push_back(DAG.getConstant(Val - 1, dl, EVT));
> }
>
> return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
> @@ -13176,14 +13191,14 @@ static SDValue LowerVSETCC(SDValue Op, c
> }
>
> SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
> - DAG.getConstant(CC0, MVT::i8));
> + DAG.getConstant(CC0, dl, MVT::i8));
> SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
> - DAG.getConstant(CC1, MVT::i8));
> + DAG.getConstant(CC1, dl, MVT::i8));
> return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
> }
> // Handle all other FP comparisons here.
> return DAG.getNode(Opc, dl, VT, Op0, Op1,
> - DAG.getConstant(SSECC, MVT::i8));
> + DAG.getConstant(SSECC, dl, MVT::i8));
> }
>
> // Break 256-bit integer vector compare into smaller ones.
> @@ -13304,10 +13319,10 @@ static SDValue LowerVSETCC(SDValue Op, c
> // compare is always unsigned.
> SDValue SB;
> if (FlipSigns) {
> - SB = DAG.getConstant(0x80000000U, MVT::v4i32);
> + SB = DAG.getConstant(0x80000000U, dl, MVT::v4i32);
> } else {
> - SDValue Sign = DAG.getConstant(0x80000000U, MVT::i32);
> - SDValue Zero = DAG.getConstant(0x00000000U, MVT::i32);
> + SDValue Sign = DAG.getConstant(0x80000000U, dl, MVT::i32);
> + SDValue Zero = DAG.getConstant(0x00000000U, dl, MVT::i32);
> SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
> Sign, Zero, Sign, Zero);
> }
> @@ -13362,7 +13377,8 @@ static SDValue LowerVSETCC(SDValue Op, c
> // bits of the inputs before performing those operations.
> if (FlipSigns) {
> EVT EltVT = VT.getVectorElementType();
> - SDValue SB =
> DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), VT);
> + SDValue SB =
> DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), dl,
> + VT);
> Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
> Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
> }
> @@ -13430,7 +13446,7 @@ SDValue X86TargetLowering::LowerSETCC(SD
>
> CCode = X86::GetOppositeBranchCondition(CCode);
> SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
> - DAG.getConstant(CCode, MVT::i8),
> + DAG.getConstant(CCode, dl, MVT::i8),
> Op0.getOperand(1));
> if (VT == MVT::i1)
> return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
> @@ -13442,18 +13458,18 @@ SDValue X86TargetLowering::LowerSETCC(SD
> (CC == ISD::SETEQ || CC == ISD::SETNE)) {
>
> ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
> - return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, MVT::i1), NewCC);
> + return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, dl, MVT::i1),
> NewCC);
> }
>
> bool isFP = Op1.getSimpleValueType().isFloatingPoint();
> - unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
> + unsigned X86CC = TranslateX86CC(CC, dl, isFP, Op0, Op1, DAG);
> if (X86CC == X86::COND_INVALID)
> return SDValue();
>
> SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
> EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
> SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
> - DAG.getConstant(X86CC, MVT::i8), EFLAGS);
> + DAG.getConstant(X86CC, dl, MVT::i8),
> EFLAGS);
> if (VT == MVT::i1)
> return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
> return SetCC;
> @@ -13518,12 +13534,12 @@ SDValue X86TargetLowering::LowerSELECT(S
> if (SSECC != 8) {
> if (Subtarget->hasAVX512()) {
> SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0,
> CondOp1,
> - DAG.getConstant(SSECC, MVT::i8));
> + DAG.getConstant(SSECC, DL, MVT::i8));
> return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
> }
>
> SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
> - DAG.getConstant(SSECC, MVT::i8));
> + DAG.getConstant(SSECC, DL, MVT::i8));
>
> // If we have AVX, we can use a variable vector select (VBLENDV)
> instead
> // of 3 logic instructions for size savings and potentially speed.
> @@ -13555,7 +13571,7 @@ SDValue X86TargetLowering::LowerSELECT(S
> SDValue VSel = DAG.getNode(ISD::VSELECT, DL, VecVT, VCmp, VOp1,
> VOp2);
>
> return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT,
> - VSel, DAG.getIntPtrConstant(0));
> + VSel, DAG.getIntPtrConstant(0, DL));
> }
> SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
> SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
> @@ -13593,21 +13609,22 @@ SDValue X86TargetLowering::LowerSELECT(S
> (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
> SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
> SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
> - DAG.getConstant(0,
> CmpOp0.getValueType()),
> + DAG.getConstant(0, DL,
> +
> CmpOp0.getValueType()),
> CmpOp0);
> SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL,
> Op.getValueType(),
> - DAG.getConstant(X86::COND_B, MVT::i8),
> + DAG.getConstant(X86::COND_B, DL,
> MVT::i8),
> SDValue(Neg.getNode(), 1));
> return Res;
> }
>
> Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
> - CmpOp0, DAG.getConstant(1,
> CmpOp0.getValueType()));
> + CmpOp0, DAG.getConstant(1, DL,
> CmpOp0.getValueType()));
> Cmp = ConvertCmpIfNecessary(Cmp, DAG);
>
> SDValue Res = // Res = 0 or -1.
> DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
> - DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
> + DAG.getConstant(X86::COND_B, DL, MVT::i8), Cmp);
>
> if (isAllOnes(Op1) != (CondCode == X86::COND_E))
> Res = DAG.getNOT(DL, Res, Res.getValueType());
> @@ -13679,7 +13696,7 @@ SDValue X86TargetLowering::LowerSELECT(S
> else
> Cond = X86Op.getValue(1);
>
> - CC = DAG.getConstant(X86Cond, MVT::i8);
> + CC = DAG.getConstant(X86Cond, DL, MVT::i8);
> addTest = false;
> }
>
> @@ -13701,7 +13718,7 @@ SDValue X86TargetLowering::LowerSELECT(S
> }
>
> if (addTest) {
> - CC = DAG.getConstant(X86::COND_NE, MVT::i8);
> + CC = DAG.getConstant(X86::COND_NE, DL, MVT::i8);
> Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
> }
>
> @@ -13716,7 +13733,8 @@ SDValue X86TargetLowering::LowerSELECT(S
> if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
> (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) ||
> isZero(Op2))) {
> SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL,
> Op.getValueType(),
> - DAG.getConstant(X86::COND_B, MVT::i8),
> Cond);
> + DAG.getConstant(X86::COND_B, DL, MVT::i8),
> + Cond);
> if (isAllOnes(Op1) != (CondCode == X86::COND_B))
> return DAG.getNOT(DL, Res, Res.getValueType());
> return Res;
> @@ -13976,7 +13994,7 @@ static SDValue LowerExtendedLoad(SDValue
> SmallVector<SDValue, 8> Chains;
> SDValue Ptr = Ld->getBasePtr();
> SDValue Increment =
> - DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, TLI.getPointerTy());
> + DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, dl,
> TLI.getPointerTy());
> SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
>
> for (unsigned i = 0; i < NumLoads; ++i) {
> @@ -13992,7 +14010,7 @@ static SDValue LowerExtendedLoad(SDValue
> Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT,
> ScalarLoad);
> else
> Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
> - ScalarLoad, DAG.getIntPtrConstant(i));
> + ScalarLoad, DAG.getIntPtrConstant(i, dl));
>
> Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
> }
> @@ -14032,7 +14050,8 @@ static SDValue LowerExtendedLoad(SDValue
> unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
> MemVT.getVectorElementType().getSizeInBits();
> Shuff =
> - DAG.getNode(ISD::SRA, dl, RegVT, Shuff, DAG.getConstant(Amt,
> RegVT));
> + DAG.getNode(ISD::SRA, dl, RegVT, Shuff,
> + DAG.getConstant(Amt, dl, RegVT));
>
> DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
> return Shuff;
> @@ -14199,7 +14218,7 @@ SDValue X86TargetLowering::LowerBRCOND(S
> else
> Cond = X86Op.getValue(1);
>
> - CC = DAG.getConstant(X86Cond, MVT::i8);
> + CC = DAG.getConstant(X86Cond, dl, MVT::i8);
> addTest = false;
> } else {
> unsigned CondOpc;
> @@ -14230,7 +14249,7 @@ SDValue X86TargetLowering::LowerBRCOND(S
> X86::CondCode CCode =
> (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
> CCode = X86::GetOppositeBranchCondition(CCode);
> - CC = DAG.getConstant(CCode, MVT::i8);
> + CC = DAG.getConstant(CCode, dl, MVT::i8);
> SDNode *User = *Op.getNode()->use_begin();
> // Look for an unconditional branch following this conditional
> branch.
> // We need this because we need to reverse the successors in
> order
> @@ -14248,7 +14267,7 @@ SDValue X86TargetLowering::LowerBRCOND(S
> X86::CondCode CCode =
> (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
> CCode = X86::GetOppositeBranchCondition(CCode);
> - CC = DAG.getConstant(CCode, MVT::i8);
> + CC = DAG.getConstant(CCode, dl, MVT::i8);
> Cond = Cmp;
> addTest = false;
> }
> @@ -14261,7 +14280,7 @@ SDValue X86TargetLowering::LowerBRCOND(S
> X86::CondCode CCode =
> (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
> CCode = X86::GetOppositeBranchCondition(CCode);
> - CC = DAG.getConstant(CCode, MVT::i8);
> + CC = DAG.getConstant(CCode, dl, MVT::i8);
> Cond = Cond.getOperand(0).getOperand(1);
> addTest = false;
> } else if (Cond.getOpcode() == ISD::SETCC &&
> @@ -14287,10 +14306,10 @@ SDValue X86TargetLowering::LowerBRCOND(S
> SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
> Cond.getOperand(0),
> Cond.getOperand(1));
> Cmp = ConvertCmpIfNecessary(Cmp, DAG);
> - CC = DAG.getConstant(X86::COND_NE, MVT::i8);
> + CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
> Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
> Chain, Dest, CC, Cmp);
> - CC = DAG.getConstant(X86::COND_P, MVT::i8);
> + CC = DAG.getConstant(X86::COND_P, dl, MVT::i8);
> Cond = Cmp;
> addTest = false;
> }
> @@ -14317,10 +14336,10 @@ SDValue X86TargetLowering::LowerBRCOND(S
> SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
> Cond.getOperand(0),
> Cond.getOperand(1));
> Cmp = ConvertCmpIfNecessary(Cmp, DAG);
> - CC = DAG.getConstant(X86::COND_NE, MVT::i8);
> + CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
> Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
> Chain, Dest, CC, Cmp);
> - CC = DAG.getConstant(X86::COND_NP, MVT::i8);
> + CC = DAG.getConstant(X86::COND_NP, dl, MVT::i8);
> Cond = Cmp;
> addTest = false;
> Dest = FalseBB;
> @@ -14348,7 +14367,7 @@ SDValue X86TargetLowering::LowerBRCOND(S
>
> if (addTest) {
> X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
> - CC = DAG.getConstant(X86Cond, MVT::i8);
> + CC = DAG.getConstant(X86Cond, dl, MVT::i8);
> Cond = EmitTest(Cond, X86Cond, dl, DAG);
> }
> Cond = ConvertCmpIfNecessary(Cond, DAG);
> @@ -14385,7 +14404,7 @@ X86TargetLowering::LowerDYNAMIC_STACKALL
>
> // Chain the dynamic stack allocation so that it doesn't modify the
> stack
> // pointer when other instructions are using the stack.
> - Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true),
> + Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, dl,
> true),
> SDLoc(Node));
>
> SDValue Size = Tmp2.getOperand(1);
> @@ -14397,11 +14416,11 @@ X86TargetLowering::LowerDYNAMIC_STACKALL
> Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
> if (Align > StackAlign)
> Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
> - DAG.getConstant(-(uint64_t)Align, VT));
> + DAG.getConstant(-(uint64_t)Align, dl, VT));
> Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
>
> - Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
> - DAG.getIntPtrConstant(0, true), SDValue(),
> + Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, dl, true),
> + DAG.getIntPtrConstant(0, dl, true), SDValue(),
> SDLoc(Node));
>
> SDValue Ops[2] = { Tmp1, Tmp2 };
> @@ -14457,7 +14476,7 @@ X86TargetLowering::LowerDYNAMIC_STACKALL
>
> if (Align) {
> SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
> - DAG.getConstant(-(uint64_t)Align, VT));
> + DAG.getConstant(-(uint64_t)Align, dl, VT));
> Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
> }
>
> @@ -14492,22 +14511,22 @@ SDValue X86TargetLowering::LowerVASTART(
> // Store gp_offset
> SDValue Store = DAG.getStore(Op.getOperand(0), DL,
>
> DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
> - MVT::i32),
> + DL, MVT::i32),
> FIN, MachinePointerInfo(SV), false, false,
> 0);
> MemOps.push_back(Store);
>
> // Store fp_offset
> FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
> - FIN, DAG.getIntPtrConstant(4));
> + FIN, DAG.getIntPtrConstant(4, DL));
> Store = DAG.getStore(Op.getOperand(0), DL,
> - DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
> + DAG.getConstant(FuncInfo->getVarArgsFPOffset(), DL,
> MVT::i32),
> FIN, MachinePointerInfo(SV, 4), false, false, 0);
> MemOps.push_back(Store);
>
> // Store ptr to overflow_arg_area
> FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
> - FIN, DAG.getIntPtrConstant(4));
> + FIN, DAG.getIntPtrConstant(4, DL));
> SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
> getPointerTy());
> Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
> @@ -14517,7 +14536,7 @@ SDValue X86TargetLowering::LowerVASTART(
>
> // Store ptr to reg_save_area.
> FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
> - FIN, DAG.getIntPtrConstant(8));
> + FIN, DAG.getIntPtrConstant(8, DL));
> SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
> getPointerTy());
> Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
> @@ -14567,9 +14586,9 @@ SDValue X86TargetLowering::LowerVAARG(SD
>
> // Insert VAARG_64 node into the DAG
> // VAARG_64 returns two values: Variable Argument Address, Chain
> - SDValue InstOps[] = {Chain, SrcPtr, DAG.getConstant(ArgSize, MVT::i32),
> - DAG.getConstant(ArgMode, MVT::i8),
> - DAG.getConstant(Align, MVT::i32)};
> + SDValue InstOps[] = {Chain, SrcPtr, DAG.getConstant(ArgSize, dl,
> MVT::i32),
> + DAG.getConstant(ArgMode, dl, MVT::i8),
> + DAG.getConstant(Align, dl, MVT::i32)};
> SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
> SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
> VTs, InstOps, MVT::i64,
> @@ -14600,7 +14619,7 @@ static SDValue LowerVACOPY(SDValue Op, c
> SDLoc DL(Op);
>
> return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
> - DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
> + DAG.getIntPtrConstant(24, DL), 8,
> /*isVolatile*/false,
> false, false,
> MachinePointerInfo(DstSV),
> MachinePointerInfo(SrcSV));
> }
> @@ -14621,7 +14640,7 @@ static SDValue getTargetVShiftByConstNod
> if (Opc == X86ISD::VSRAI)
> ShiftAmt = ElementType.getSizeInBits() - 1;
> else
> - return DAG.getConstant(0, VT);
> + return DAG.getConstant(0, dl, VT);
> }
>
> assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc ==
> X86ISD::VSRAI)
> @@ -14646,7 +14665,7 @@ static SDValue getTargetVShiftByConstNod
> }
> ND = cast<ConstantSDNode>(CurrentOp);
> const APInt &C = ND->getAPIntValue();
> - Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), ElementType));
> + Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), dl, ElementType));
> }
> break;
> case X86ISD::VSRLI:
> @@ -14658,7 +14677,7 @@ static SDValue getTargetVShiftByConstNod
> }
> ND = cast<ConstantSDNode>(CurrentOp);
> const APInt &C = ND->getAPIntValue();
> - Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), ElementType));
> + Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), dl,
> ElementType));
> }
> break;
> case X86ISD::VSRAI:
> @@ -14670,7 +14689,7 @@ static SDValue getTargetVShiftByConstNod
> }
> ND = cast<ConstantSDNode>(CurrentOp);
> const APInt &C = ND->getAPIntValue();
> - Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), ElementType));
> + Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), dl,
> ElementType));
> }
> break;
> }
> @@ -14678,7 +14697,8 @@ static SDValue getTargetVShiftByConstNod
> return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
> }
>
> - return DAG.getNode(Opc, dl, VT, SrcOp, DAG.getConstant(ShiftAmt,
> MVT::i8));
> + return DAG.getNode(Opc, dl, VT, SrcOp,
> + DAG.getConstant(ShiftAmt, dl, MVT::i8));
> }
>
> // getTargetVShiftNode - Handle vector element shifts where the shift
> amount
> @@ -14716,7 +14736,7 @@ static SDValue getTargetVShiftNode(unsig
> SmallVector<SDValue, 4> ShOps;
> ShOps.push_back(ShAmt);
> if (SVT == MVT::i32) {
> - ShOps.push_back(DAG.getConstant(0, SVT));
> + ShOps.push_back(DAG.getConstant(0, dl, SVT));
> ShOps.push_back(DAG.getUNDEF(SVT));
> }
> ShOps.push_back(DAG.getUNDEF(SVT));
> @@ -14757,7 +14777,7 @@ static SDValue getVectorMaskingNode(SDVa
> // are extracted by EXTRACT_SUBVECTOR.
> SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
> DAG.getNode(ISD::BITCAST, dl, BitcastVT,
> Mask),
> - DAG.getIntPtrConstant(0));
> + DAG.getIntPtrConstant(0, dl));
>
> switch (Op.getOpcode()) {
> default: break;
> @@ -14915,22 +14935,23 @@ static SDValue LowerINTRINSIC_WO_CHAIN(S
> Op.getOperand(2));
> }
> SDValue CmpMask = getVectorMaskingNode(Cmp, Mask,
> - DAG.getTargetConstant(0,
> MaskVT),
> + DAG.getTargetConstant(0, dl,
> +
> MaskVT),
> Subtarget, DAG);
> SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
> DAG.getUNDEF(BitcastVT), CmpMask,
> - DAG.getIntPtrConstant(0));
> + DAG.getIntPtrConstant(0, dl));
> return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
> }
> case COMI: { // Comparison intrinsics
> ISD::CondCode CC = (ISD::CondCode)IntrData->Opc1;
> SDValue LHS = Op.getOperand(1);
> SDValue RHS = Op.getOperand(2);
> - unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
> + unsigned X86CC = TranslateX86CC(CC, dl, true, LHS, RHS, DAG);
> assert(X86CC != X86::COND_INVALID && "Unexpected illegal
> condition!");
> SDValue Cond = DAG.getNode(IntrData->Opc0, dl, MVT::i32, LHS, RHS);
> SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
> - DAG.getConstant(X86CC, MVT::i8), Cond);
> + DAG.getConstant(X86CC, dl, MVT::i8),
> Cond);
> return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
> }
> case VSHIFT:
> @@ -14957,7 +14978,7 @@ static SDValue LowerINTRINSIC_WO_CHAIN(S
> SDLoc dl(Op);
> SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
> DAG.getNode(ISD::BITCAST, dl,
> BitcastVT, Mask),
> - DAG.getIntPtrConstant(0));
> + DAG.getIntPtrConstant(0, dl));
>
> return DAG.getNode(IntrData->Opc0, dl, VT, VMask, DataToCompress,
> PassThru);
> @@ -14972,7 +14993,7 @@ static SDValue LowerINTRINSIC_WO_CHAIN(S
> SDLoc dl(Op);
> SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
> DAG.getNode(ISD::BITCAST, dl,
> BitcastVT, Mask),
> - DAG.getIntPtrConstant(0));
> + DAG.getIntPtrConstant(0, dl));
> return DAG.getNode(IntrData->Opc0, dl, VT, VMask, Op.getOperand(1),
> Op.getOperand(2));
> }
> @@ -15062,7 +15083,7 @@ static SDValue LowerINTRINSIC_WO_CHAIN(S
> SDValue RHS = Op.getOperand(2);
> unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
> SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
> - SDValue CC = DAG.getConstant(X86CC, MVT::i8);
> + SDValue CC = DAG.getConstant(X86CC, dl, MVT::i8);
> SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
> return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
> }
> @@ -15071,7 +15092,7 @@ static SDValue LowerINTRINSIC_WO_CHAIN(S
> unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)?
> X86::COND_E: X86::COND_B;
> SDValue LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1,
> Op.getOperand(1));
> SDValue RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1,
> Op.getOperand(2));
> - SDValue CC = DAG.getConstant(X86CC, MVT::i8);
> + SDValue CC = DAG.getConstant(X86CC, dl, MVT::i8);
> SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
> SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
> return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
> @@ -15136,7 +15157,7 @@ static SDValue LowerINTRINSIC_WO_CHAIN(S
> SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
> SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
> SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
> - DAG.getConstant(X86CC, MVT::i8),
> + DAG.getConstant(X86CC, dl, MVT::i8),
> SDValue(PCMP.getNode(), 1));
> return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
> }
> @@ -15163,17 +15184,17 @@ static SDValue getGatherNode(unsigned Op
> SDLoc dl(Op);
> ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
> assert(C && "Invalid scale type");
> - SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
> + SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
> EVT MaskVT = MVT::getVectorVT(MVT::i1,
>
> Index.getSimpleValueType().getVectorNumElements());
> SDValue MaskInReg;
> ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
> if (MaskC)
> - MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
> + MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
> else
> MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
> SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
> - SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
> + SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
> SDValue Segment = DAG.getRegister(0, MVT::i32);
> if (Src.getOpcode() == ISD::UNDEF)
> Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
> @@ -15189,15 +15210,15 @@ static SDValue getScatterNode(unsigned O
> SDLoc dl(Op);
> ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
> assert(C && "Invalid scale type");
> - SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
> - SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
> + SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
> + SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
> SDValue Segment = DAG.getRegister(0, MVT::i32);
> EVT MaskVT = MVT::getVectorVT(MVT::i1,
>
> Index.getSimpleValueType().getVectorNumElements());
> SDValue MaskInReg;
> ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
> if (MaskC)
> - MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
> + MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
> else
> MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
> SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
> @@ -15212,15 +15233,15 @@ static SDValue getPrefetchNode(unsigned
> SDLoc dl(Op);
> ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
> assert(C && "Invalid scale type");
> - SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
> - SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
> + SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
> + SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
> SDValue Segment = DAG.getRegister(0, MVT::i32);
> EVT MaskVT =
> MVT::getVectorVT(MVT::i1,
> Index.getSimpleValueType().getVectorNumElements());
> SDValue MaskInReg;
> ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
> if (MaskC)
> - MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
> + MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
> else
> MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
> //SDVTList VTs = DAG.getVTList(MVT::Other);
> @@ -15261,7 +15282,7 @@ static void getReadPerformanceCounter(SD
> // The EAX register is loaded with the low-order 32 bits. The EDX
> register
> // is loaded with the supported high-order bits of the counter.
> SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
> - DAG.getConstant(32, MVT::i8));
> + DAG.getConstant(32, DL, MVT::i8));
> Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
> Results.push_back(Chain);
> return;
> @@ -15315,7 +15336,7 @@ static void getReadTimeStampCounter(SDNo
> // The EDX register is loaded with the high-order 32 bits of the MSR,
> and
> // the EAX register is loaded with the low-order 32 bits.
> SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
> - DAG.getConstant(32, MVT::i8));
> + DAG.getConstant(32, DL, MVT::i8));
> Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
> Results.push_back(Chain);
> return;
> @@ -15360,8 +15381,8 @@ static SDValue LowerINTRINSIC_W_CHAIN(SD
> // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
> // Otherwise return the value from Rand, which is always 0, casted to
> i32.
> SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
> - DAG.getConstant(1, Op->getValueType(1)),
> - DAG.getConstant(X86::COND_B, MVT::i32),
> + DAG.getConstant(1, dl, Op->getValueType(1)),
> + DAG.getConstant(X86::COND_B, dl, MVT::i32),
> SDValue(Result.getNode(), 1) };
> SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
> DAG.getVTList(Op->getValueType(1),
> MVT::Glue),
> @@ -15421,7 +15442,7 @@ static SDValue LowerINTRINSIC_W_CHAIN(SD
> SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
> SDValue InTrans = DAG.getNode(IntrData->Opc0, dl, VTs,
> Op.getOperand(0));
> SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
> - DAG.getConstant(X86::COND_NE, MVT::i8),
> + DAG.getConstant(X86::COND_NE, dl,
> MVT::i8),
> InTrans);
> SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0),
> SetCC);
> return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
> @@ -15433,14 +15454,14 @@ static SDValue LowerINTRINSIC_W_CHAIN(SD
> SDVTList CFVTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
> SDVTList VTs = DAG.getVTList(Op.getOperand(3)->getValueType(0),
> MVT::Other);
> SDValue GenCF = DAG.getNode(X86ISD::ADD, dl, CFVTs, Op.getOperand(2),
> - DAG.getConstant(-1, MVT::i8));
> + DAG.getConstant(-1, dl, MVT::i8));
> SDValue Res = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(3),
> Op.getOperand(4), GenCF.getValue(1));
> SDValue Store = DAG.getStore(Op.getOperand(0), dl, Res.getValue(0),
> Op.getOperand(5), MachinePointerInfo(),
> false, false, 0);
> SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
> - DAG.getConstant(X86::COND_B, MVT::i8),
> + DAG.getConstant(X86::COND_B, dl, MVT::i8),
> Res.getValue(1));
> Results.push_back(SetCC);
> Results.push_back(Store);
> @@ -15464,7 +15485,7 @@ static SDValue LowerINTRINSIC_W_CHAIN(SD
> Mask.getValueType().getSizeInBits());
> SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
> DAG.getNode(ISD::BITCAST, dl, BitcastVT,
> Mask),
> - DAG.getIntPtrConstant(0));
> + DAG.getIntPtrConstant(0, dl));
>
> SDValue Compressed = DAG.getNode(IntrData->Opc0, dl, VT, VMask,
> DataToCompress, DAG.getUNDEF(VT));
> @@ -15488,7 +15509,7 @@ static SDValue LowerINTRINSIC_W_CHAIN(SD
> Mask.getValueType().getSizeInBits());
> SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
> DAG.getNode(ISD::BITCAST, dl, BitcastVT,
> Mask),
> - DAG.getIntPtrConstant(0));
> + DAG.getIntPtrConstant(0, dl));
>
> SDValue DataToExpand = DAG.getLoad(VT, dl, Chain, Addr,
> MachinePointerInfo(),
> false, false, false, 0);
> @@ -15516,7 +15537,7 @@ SDValue X86TargetLowering::LowerRETURNAD
> if (Depth > 0) {
> SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
> const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
> - SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), PtrVT);
> + SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), dl, PtrVT);
> return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
> DAG.getNode(ISD::ADD, dl, PtrVT,
> FrameAddr, Offset),
> @@ -15584,7 +15605,7 @@ unsigned X86TargetLowering::getRegisterB
> SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
> SelectionDAG &DAG)
> const {
> const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
> - return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize());
> + return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize(), SDLoc(Op));
> }
>
> SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG)
> const {
> @@ -15603,7 +15624,8 @@ SDValue X86TargetLowering::LowerEH_RETUR
> unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
>
> SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
> -
> DAG.getIntPtrConstant(RegInfo->getSlotSize()));
> +
> DAG.getIntPtrConstant(RegInfo->getSlotSize(),
> + dl));
> StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
> Chain = DAG.getStore(Chain, dl, Handler, StoreAddr,
> MachinePointerInfo(),
> false, false, 0);
> @@ -15658,12 +15680,12 @@ SDValue X86TargetLowering::LowerINIT_TRA
> // Load the pointer to the nested function into R11.
> unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
> SDValue Addr = Trmp;
> - OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode,
> MVT::i16),
> + OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl,
> MVT::i16),
> Addr, MachinePointerInfo(TrmpAddr),
> false, false, 0);
>
> Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
> - DAG.getConstant(2, MVT::i64));
> + DAG.getConstant(2, dl, MVT::i64));
> OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
> MachinePointerInfo(TrmpAddr, 2),
> false, false, 2);
> @@ -15672,13 +15694,13 @@ SDValue X86TargetLowering::LowerINIT_TRA
> // R10 is specified in X86CallingConv.td
> OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
> Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
> - DAG.getConstant(10, MVT::i64));
> - OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode,
> MVT::i16),
> + DAG.getConstant(10, dl, MVT::i64));
> + OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl,
> MVT::i16),
> Addr, MachinePointerInfo(TrmpAddr, 10),
> false, false, 0);
>
> Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
> - DAG.getConstant(12, MVT::i64));
> + DAG.getConstant(12, dl, MVT::i64));
> OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
> MachinePointerInfo(TrmpAddr, 12),
> false, false, 2);
> @@ -15686,16 +15708,16 @@ SDValue X86TargetLowering::LowerINIT_TRA
> // Jump to the nested function.
> OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
> Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
> - DAG.getConstant(20, MVT::i64));
> - OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode,
> MVT::i16),
> + DAG.getConstant(20, dl, MVT::i64));
> + OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl,
> MVT::i16),
> Addr, MachinePointerInfo(TrmpAddr, 20),
> false, false, 0);
>
> unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
> Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
> - DAG.getConstant(22, MVT::i64));
> - OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM,
> MVT::i8), Addr,
> - MachinePointerInfo(TrmpAddr, 22),
> + DAG.getConstant(22, dl, MVT::i64));
> + OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, dl,
> MVT::i8),
> + Addr, MachinePointerInfo(TrmpAddr, 22),
> false, false, 0);
>
> return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
> @@ -15748,32 +15770,32 @@ SDValue X86TargetLowering::LowerINIT_TRA
> SDValue Addr, Disp;
>
> Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
> - DAG.getConstant(10, MVT::i32));
> + DAG.getConstant(10, dl, MVT::i32));
> Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
>
> // This is storing the opcode for MOV32ri.
> const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
> const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
> OutChains[0] = DAG.getStore(Root, dl,
> - DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
> + DAG.getConstant(MOV32ri|N86Reg, dl,
> MVT::i8),
> Trmp, MachinePointerInfo(TrmpAddr),
> false, false, 0);
>
> Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
> - DAG.getConstant(1, MVT::i32));
> + DAG.getConstant(1, dl, MVT::i32));
> OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
> MachinePointerInfo(TrmpAddr, 1),
> false, false, 1);
>
> const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
> Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
> - DAG.getConstant(5, MVT::i32));
> - OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8),
> Addr,
> - MachinePointerInfo(TrmpAddr, 5),
> + DAG.getConstant(5, dl, MVT::i32));
> + OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, dl,
> MVT::i8),
> + Addr, MachinePointerInfo(TrmpAddr, 5),
> false, false, 1);
>
> Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
> - DAG.getConstant(6, MVT::i32));
> + DAG.getConstant(6, dl, MVT::i32));
> OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
> MachinePointerInfo(TrmpAddr, 6),
> false, false, 1);
> @@ -15830,20 +15852,20 @@ SDValue X86TargetLowering::LowerFLT_ROUN
> SDValue CWD1 =
> DAG.getNode(ISD::SRL, DL, MVT::i16,
> DAG.getNode(ISD::AND, DL, MVT::i16,
> - CWD, DAG.getConstant(0x800, MVT::i16)),
> - DAG.getConstant(11, MVT::i8));
> + CWD, DAG.getConstant(0x800, DL, MVT::i16)),
> + DAG.getConstant(11, DL, MVT::i8));
> SDValue CWD2 =
> DAG.getNode(ISD::SRL, DL, MVT::i16,
> DAG.getNode(ISD::AND, DL, MVT::i16,
> - CWD, DAG.getConstant(0x400, MVT::i16)),
> - DAG.getConstant(9, MVT::i8));
> + CWD, DAG.getConstant(0x400, DL, MVT::i16)),
> + DAG.getConstant(9, DL, MVT::i8));
>
> SDValue RetVal =
> DAG.getNode(ISD::AND, DL, MVT::i16,
> DAG.getNode(ISD::ADD, DL, MVT::i16,
> DAG.getNode(ISD::OR, DL, MVT::i16, CWD1,
> CWD2),
> - DAG.getConstant(1, MVT::i16)),
> - DAG.getConstant(3, MVT::i16));
> + DAG.getConstant(1, DL, MVT::i16)),
> + DAG.getConstant(3, DL, MVT::i16));
>
> return DAG.getNode((VT.getSizeInBits() < 16 ?
> ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
> @@ -15869,14 +15891,15 @@ static SDValue LowerCTLZ(SDValue Op, Sel
> // If src is zero (i.e. bsr sets ZF), returns NumBits.
> SDValue Ops[] = {
> Op,
> - DAG.getConstant(NumBits+NumBits-1, OpVT),
> - DAG.getConstant(X86::COND_E, MVT::i8),
> + DAG.getConstant(NumBits + NumBits - 1, dl, OpVT),
> + DAG.getConstant(X86::COND_E, dl, MVT::i8),
> Op.getValue(1)
> };
> Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
>
> // Finally xor with NumBits-1.
> - Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1,
> OpVT));
> + Op = DAG.getNode(ISD::XOR, dl, OpVT, Op,
> + DAG.getConstant(NumBits - 1, dl, OpVT));
>
> if (VT == MVT::i8)
> Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
> @@ -15901,7 +15924,8 @@ static SDValue LowerCTLZ_ZERO_UNDEF(SDVa
> Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
>
> // And xor with NumBits-1.
> - Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1,
> OpVT));
> + Op = DAG.getNode(ISD::XOR, dl, OpVT, Op,
> + DAG.getConstant(NumBits - 1, dl, OpVT));
>
> if (VT == MVT::i8)
> Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
> @@ -15921,8 +15945,8 @@ static SDValue LowerCTTZ(SDValue Op, Sel
> // If src is zero (i.e. bsf sets ZF), returns NumBits.
> SDValue Ops[] = {
> Op,
> - DAG.getConstant(NumBits, VT),
> - DAG.getConstant(X86::COND_E, MVT::i8),
> + DAG.getConstant(NumBits, dl, VT),
> + DAG.getConstant(X86::COND_E, dl, MVT::i8),
> Op.getValue(1)
> };
> return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
> @@ -15989,8 +16013,8 @@ static SDValue LowerMUL(SDValue Op, cons
> if (Subtarget->hasInt256()) {
> if (VT == MVT::v32i8) {
> MVT SubVT = MVT::getVectorVT(MVT::i8, VT.getVectorNumElements() /
> 2);
> - SDValue Lo = DAG.getIntPtrConstant(0);
> - SDValue Hi = DAG.getIntPtrConstant(VT.getVectorNumElements() / 2);
> + SDValue Lo = DAG.getIntPtrConstant(0, dl);
> + SDValue Hi = DAG.getIntPtrConstant(VT.getVectorNumElements() / 2,
> dl);
> SDValue ALo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, A,
> Lo);
> SDValue BLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, B,
> Lo);
> SDValue AHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, A,
> Hi);
> @@ -16024,8 +16048,8 @@ static SDValue LowerMUL(SDValue Op, cons
> BLo = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
> ALo = DAG.getNode(ISD::BITCAST, dl, ExVT, ALo);
> BLo = DAG.getNode(ISD::BITCAST, dl, ExVT, BLo);
> - ALo = DAG.getNode(ISD::SRA, dl, ExVT, ALo, DAG.getConstant(8,
> ExVT));
> - BLo = DAG.getNode(ISD::SRA, dl, ExVT, BLo, DAG.getConstant(8,
> ExVT));
> + ALo = DAG.getNode(ISD::SRA, dl, ExVT, ALo, DAG.getConstant(8, dl,
> ExVT));
> + BLo = DAG.getNode(ISD::SRA, dl, ExVT, BLo, DAG.getConstant(8, dl,
> ExVT));
> }
>
> // Extract the hi parts and sign extend to i16
> @@ -16044,15 +16068,15 @@ static SDValue LowerMUL(SDValue Op, cons
> BHi = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
> AHi = DAG.getNode(ISD::BITCAST, dl, ExVT, AHi);
> BHi = DAG.getNode(ISD::BITCAST, dl, ExVT, BHi);
> - AHi = DAG.getNode(ISD::SRA, dl, ExVT, AHi, DAG.getConstant(8,
> ExVT));
> - BHi = DAG.getNode(ISD::SRA, dl, ExVT, BHi, DAG.getConstant(8,
> ExVT));
> + AHi = DAG.getNode(ISD::SRA, dl, ExVT, AHi, DAG.getConstant(8, dl,
> ExVT));
> + BHi = DAG.getNode(ISD::SRA, dl, ExVT, BHi, DAG.getConstant(8, dl,
> ExVT));
> }
>
> // Multiply, mask the lower 8bits of the lo/hi results and pack
> SDValue RLo = DAG.getNode(ISD::MUL, dl, ExVT, ALo, BLo);
> SDValue RHi = DAG.getNode(ISD::MUL, dl, ExVT, AHi, BHi);
> - RLo = DAG.getNode(ISD::AND, dl, ExVT, RLo, DAG.getConstant(255,
> ExVT));
> - RHi = DAG.getNode(ISD::AND, dl, ExVT, RHi, DAG.getConstant(255,
> ExVT));
> + RLo = DAG.getNode(ISD::AND, dl, ExVT, RLo, DAG.getConstant(255, dl,
> ExVT));
> + RHi = DAG.getNode(ISD::AND, dl, ExVT, RHi, DAG.getConstant(255, dl,
> ExVT));
> return DAG.getNode(X86ISD::PACKUS, dl, VT, RLo, RHi);
> }
>
> @@ -16228,7 +16252,8 @@ static SDValue LowerMUL_LOHI(SDValue Op,
> // unsigned multiply.
> if (IsSigned && !Subtarget->hasSSE41()) {
> SDValue ShAmt =
> - DAG.getConstant(31,
> DAG.getTargetLoweringInfo().getShiftAmountTy(VT));
> + DAG.getConstant(31, dl,
> + DAG.getTargetLoweringInfo().getShiftAmountTy(VT));
> SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
> DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt),
> Op1);
> SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
> @@ -16283,7 +16308,7 @@ static SDValue LowerScalarImmediateShift
> SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
> // Zero out the rightmost bits.
> SmallVector<SDValue, 32> V(
> - NumElts, DAG.getConstant(uint8_t(-1U << ShiftAmt),
> MVT::i8));
> + NumElts, DAG.getConstant(uint8_t(-1U << ShiftAmt), dl,
> MVT::i8));
> return DAG.getNode(ISD::AND, dl, VT, SHL,
> DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
> }
> @@ -16294,7 +16319,7 @@ static SDValue LowerScalarImmediateShift
> SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
> // Zero out the leftmost bits.
> SmallVector<SDValue, 32> V(
> - NumElts, DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
> MVT::i8));
> + NumElts, DAG.getConstant(uint8_t(-1U) >> ShiftAmt, dl,
> MVT::i8));
> return DAG.getNode(ISD::AND, dl, VT, SRL,
> DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
> }
> @@ -16308,7 +16333,8 @@ static SDValue LowerScalarImmediateShift
> // R s>> a === ((R u>> a) ^ m) - m
> SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
> SmallVector<SDValue, 32> V(NumElts,
> - DAG.getConstant(128 >> ShiftAmt,
> MVT::i8));
> + DAG.getConstant(128 >> ShiftAmt, dl,
> + MVT::i8));
> SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
> Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
> Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
> @@ -16413,7 +16439,7 @@ static SDValue LowerScalarVariableShift(
> if (!BaseShAmt)
> // Avoid introducing an extract element from a shuffle.
> BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
> InVec,
> - DAG.getIntPtrConstant(SplatIdx));
> + DAG.getIntPtrConstant(SplatIdx, dl));
> }
> }
>
> @@ -16571,7 +16597,7 @@ static SDValue LowerShift(SDValue Op, co
> Elts.push_back(DAG.getUNDEF(SVT));
> continue;
> }
> - Elts.push_back(DAG.getConstant(One.shl(ShAmt), SVT));
> + Elts.push_back(DAG.getConstant(One.shl(ShAmt), dl, SVT));
> }
> SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
> return DAG.getNode(ISD::MUL, dl, VT, R, BV);
> @@ -16579,9 +16605,10 @@ static SDValue LowerShift(SDValue Op, co
>
> // Lower SHL with variable shift amount.
> if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
> - Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, VT));
> + Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, dl, VT));
>
> - Op = DAG.getNode(ISD::ADD, dl, VT, Op, DAG.getConstant(0x3f800000U,
> VT));
> + Op = DAG.getNode(ISD::ADD, dl, VT, Op,
> + DAG.getConstant(0x3f800000U, dl, VT));
> Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
> Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
> return DAG.getNode(ISD::MUL, dl, VT, Op, R);
> @@ -16645,10 +16672,10 @@ static SDValue LowerShift(SDValue Op, co
> // Replace this node with two shifts followed by a MOVSS/MOVSD.
> EVT CastVT = MVT::v4i32;
> SDValue Splat1 =
> - DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), VT);
> + DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), dl,
> VT);
> SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
> SDValue Splat2 =
> - DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), VT);
> + DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), dl,
> VT);
> SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
> if (TargetOpcode == X86ISD::MOVSD)
> CastVT = MVT::v2i64;
> @@ -16664,16 +16691,16 @@ static SDValue LowerShift(SDValue Op, co
> assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
>
> // a = a << 5;
> - Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(5, VT));
> + Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(5, dl, VT));
> Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
>
> // Turn 'a' into a mask suitable for VSELECT
> - SDValue VSelM = DAG.getConstant(0x80, VT);
> + SDValue VSelM = DAG.getConstant(0x80, dl, VT);
> SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
> OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
>
> - SDValue CM1 = DAG.getConstant(0x0f, VT);
> - SDValue CM2 = DAG.getConstant(0x3f, VT);
> + SDValue CM1 = DAG.getConstant(0x0f, dl, VT);
> + SDValue CM2 = DAG.getConstant(0x3f, dl, VT);
>
> // r = VSELECT(r, psllw(r & (char16)15, 4), a);
> SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
> @@ -16814,7 +16841,7 @@ static SDValue LowerXALUO(SDValue Op, Se
>
> SDValue SetCC =
> DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
> - DAG.getConstant(X86::COND_O, MVT::i32),
> + DAG.getConstant(X86::COND_O, DL, MVT::i32),
> SDValue(Sum.getNode(), 2));
>
> return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
> @@ -16827,7 +16854,7 @@ static SDValue LowerXALUO(SDValue Op, Se
>
> SDValue SetCC =
> DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
> - DAG.getConstant(Cond, MVT::i32),
> + DAG.getConstant(Cond, DL, MVT::i32),
> SDValue(Sum.getNode(), 1));
>
> return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
> @@ -16979,13 +17006,13 @@ static SDValue LowerATOMIC_FENCE(SDValue
> return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other,
> Op.getOperand(0));
>
> SDValue Chain = Op.getOperand(0);
> - SDValue Zero = DAG.getConstant(0, MVT::i32);
> + SDValue Zero = DAG.getConstant(0, dl, MVT::i32);
> SDValue Ops[] = {
> - DAG.getRegister(X86::ESP, MVT::i32), // Base
> - DAG.getTargetConstant(1, MVT::i8), // Scale
> - DAG.getRegister(0, MVT::i32), // Index
> - DAG.getTargetConstant(0, MVT::i32), // Disp
> - DAG.getRegister(0, MVT::i32), // Segment.
> + DAG.getRegister(X86::ESP, MVT::i32), // Base
> + DAG.getTargetConstant(1, dl, MVT::i8), // Scale
> + DAG.getRegister(0, MVT::i32), // Index
> + DAG.getTargetConstant(0, dl, MVT::i32), // Disp
> + DAG.getRegister(0, MVT::i32), // Segment.
> Zero,
> Chain
> };
> @@ -17018,7 +17045,7 @@ static SDValue LowerCMP_SWAP(SDValue Op,
> SDValue Ops[] = { cpIn.getValue(0),
> Op.getOperand(1),
> Op.getOperand(3),
> - DAG.getTargetConstant(size, MVT::i8),
> + DAG.getTargetConstant(size, DL, MVT::i8),
> cpIn.getValue(1) };
> SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
> MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
> @@ -17030,7 +17057,8 @@ static SDValue LowerCMP_SWAP(SDValue Op,
> SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
> MVT::i32, cpOut.getValue(2));
> SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
> - DAG.getConstant(X86::COND_E, MVT::i8),
> EFLAGS);
> + DAG.getConstant(X86::COND_E, DL, MVT::i8),
> + EFLAGS);
>
> DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
> DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
> @@ -17059,7 +17087,7 @@ static SDValue LowerBITCAST(SDValue Op,
> SmallVector<SDValue, 16> Elts;
> for (unsigned i = 0, e = NumElts; i != e; ++i)
> Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
> - DAG.getIntPtrConstant(i)));
> + DAG.getIntPtrConstant(i, dl)));
>
> // Explicitly mark the extra elements as Undef.
> Elts.append(NumElts, DAG.getUNDEF(SVT));
> @@ -17068,7 +17096,7 @@ static SDValue LowerBITCAST(SDValue Op,
> SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
> SDValue ToV2F64 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, BV);
> return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
> - DAG.getIntPtrConstant(0));
> + DAG.getIntPtrConstant(0, dl));
> }
>
> assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
> @@ -17123,12 +17151,15 @@ static SDValue LowerCTPOP(SDValue Op, co
> bool NeedsBitcast = EltVT == MVT::i32;
> MVT BitcastVT = VT.is256BitVector() ? MVT::v4i64 : MVT::v2i64;
>
> - SDValue Cst55 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x55)),
> EltVT);
> - SDValue Cst33 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x33)),
> EltVT);
> - SDValue Cst0F = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x0F)),
> EltVT);
> + SDValue Cst55 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x55)),
> dl,
> + EltVT);
> + SDValue Cst33 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x33)),
> dl,
> + EltVT);
> + SDValue Cst0F = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x0F)),
> dl,
> + EltVT);
>
> // v = v - ((v >> 1) & 0x55555555...)
> - SmallVector<SDValue, 8> Ones(NumElts, DAG.getConstant(1, EltVT));
> + SmallVector<SDValue, 8> Ones(NumElts, DAG.getConstant(1, dl, EltVT));
> SDValue OnesV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ones);
> SDValue Srl = DAG.getNode(ISD::SRL, dl, VT, Op, OnesV);
> if (NeedsBitcast)
> @@ -17147,7 +17178,7 @@ static SDValue LowerCTPOP(SDValue Op, co
> // v = (v & 0x33333333...) + ((v >> 2) & 0x33333333...)
> SmallVector<SDValue, 8> Mask33(NumElts, Cst33);
> SDValue M33 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Mask33);
> - SmallVector<SDValue, 8> Twos(NumElts, DAG.getConstant(2, EltVT));
> + SmallVector<SDValue, 8> Twos(NumElts, DAG.getConstant(2, dl, EltVT));
> SDValue TwosV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Twos);
>
> Srl = DAG.getNode(ISD::SRL, dl, VT, Sub, TwosV);
> @@ -17166,7 +17197,7 @@ static SDValue LowerCTPOP(SDValue Op, co
> SDValue Add = DAG.getNode(ISD::ADD, dl, VT, AndLHS, AndRHS);
>
> // v = (v + (v >> 4)) & 0x0F0F0F0F...
> - SmallVector<SDValue, 8> Fours(NumElts, DAG.getConstant(4, EltVT));
> + SmallVector<SDValue, 8> Fours(NumElts, DAG.getConstant(4, dl, EltVT));
> SDValue FoursV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Fours);
> Srl = DAG.getNode(ISD::SRL, dl, VT, Add, FoursV);
> Add = DAG.getNode(ISD::ADD, dl, VT, Add, Srl);
> @@ -17199,7 +17230,7 @@ static SDValue LowerCTPOP(SDValue Op, co
> Add = And;
> SmallVector<SDValue, 8> Csts;
> for (unsigned i = 8; i <= Len/2; i *= 2) {
> - Csts.assign(NumElts, DAG.getConstant(i, EltVT));
> + Csts.assign(NumElts, DAG.getConstant(i, dl, EltVT));
> SDValue CstsV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Csts);
> Srl = DAG.getNode(ISD::SRL, dl, VT, Add, CstsV);
> Add = DAG.getNode(ISD::ADD, dl, VT, Add, Srl);
> @@ -17207,7 +17238,8 @@ static SDValue LowerCTPOP(SDValue Op, co
> }
>
> // The result is on the least significant 6-bits on i32 and 7-bits on
> i64.
> - SDValue Cst3F = DAG.getConstant(APInt(Len, Len == 32 ? 0x3F : 0x7F),
> EltVT);
> + SDValue Cst3F = DAG.getConstant(APInt(Len, Len == 32 ? 0x3F : 0x7F), dl,
> + EltVT);
> SmallVector<SDValue, 8> Cst3FV(NumElts, Cst3F);
> SDValue M3F = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Cst3FV);
> if (NeedsBitcast) {
> @@ -17226,7 +17258,7 @@ static SDValue LowerLOAD_SUB(SDValue Op,
> SDLoc dl(Node);
> EVT T = Node->getValueType(0);
> SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
> - DAG.getConstant(0, T), Node->getOperand(2));
> + DAG.getConstant(0, dl, T),
> Node->getOperand(2));
> return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
> cast<AtomicSDNode>(Node)->getMemoryVT(),
> Node->getOperand(0),
> @@ -17332,9 +17364,9 @@ static SDValue LowerFSINCOS(SDValue Op,
>
> // Returned in bits 0:31 and 32:64 xmm0.
> SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
> - CallResult.first,
> DAG.getIntPtrConstant(0));
> + CallResult.first, DAG.getIntPtrConstant(0,
> dl));
> SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
> - CallResult.first,
> DAG.getIntPtrConstant(1));
> + CallResult.first, DAG.getIntPtrConstant(1,
> dl));
> SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
> return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
> }
> @@ -17501,7 +17533,7 @@ void X86TargetLowering::ReplaceNodeResul
> return;
> SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
> N->getOperand(0));
> - SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
> + SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
> dl,
> MVT::f64);
> SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias,
> Bias);
> SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
> @@ -17544,9 +17576,9 @@ void X86TargetLowering::ReplaceNodeResul
> EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
> SDValue cpInL, cpInH;
> cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
> - DAG.getConstant(0, HalfT));
> + DAG.getConstant(0, dl, HalfT));
> cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
> - DAG.getConstant(1, HalfT));
> + DAG.getConstant(1, dl, HalfT));
> cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
> Regs64bit ? X86::RAX : X86::EAX,
> cpInL, SDValue());
> @@ -17555,9 +17587,9 @@ void X86TargetLowering::ReplaceNodeResul
> cpInH, cpInL.getValue(1));
> SDValue swapInL, swapInH;
> swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT,
> N->getOperand(3),
> - DAG.getConstant(0, HalfT));
> + DAG.getConstant(0, dl, HalfT));
> swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT,
> N->getOperand(3),
> - DAG.getConstant(1, HalfT));
> + DAG.getConstant(1, dl, HalfT));
> swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
> Regs64bit ? X86::RBX : X86::EBX,
> swapInL, cpInH.getValue(1));
> @@ -17584,7 +17616,7 @@ void X86TargetLowering::ReplaceNodeResul
> MVT::i32, cpOutH.getValue(2));
> SDValue Success =
> DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
> - DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
> + DAG.getConstant(X86::COND_E, dl, MVT::i8), EFLAGS);
> Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
>
> Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
> @@ -17634,7 +17666,7 @@ void X86TargetLowering::ReplaceNodeResul
> SmallVector<SDValue, 8> Elts;
> for (unsigned i = 0, e = NumElts; i != e; ++i)
> Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
> - ToVecInt, DAG.getIntPtrConstant(i)));
> + ToVecInt, DAG.getIntPtrConstant(i,
> dl)));
>
> Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
> }
> @@ -19845,7 +19877,7 @@ static bool combineX86ShuffleChain(SDVal
> int M = Mask[i / Ratio] != SM_SentinelZero
> ? Ratio * Mask[i / Ratio] + i % Ratio
> : 255;
> - PSHUFBMask.push_back(DAG.getConstant(M, MVT::i8));
> + PSHUFBMask.push_back(DAG.getConstant(M, DL, MVT::i8));
> }
> MVT ByteVT = MVT::getVectorVT(MVT::i8, NumBytes);
> Op = DAG.getNode(ISD::BITCAST, DL, ByteVT, Input);
> @@ -20151,7 +20183,7 @@ combineRedundantDWordShuffle(SDValue N,
> for (int &M : Mask)
> M = VMask[M];
> V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
> - getV4X86ShuffleImm8ForMask(Mask, DAG));
> + getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
>
> // Rebuild the chain around this new shuffle.
> while (!Chain.empty()) {
> @@ -20238,7 +20270,7 @@ static bool combineRedundantHalfShuffle(
> for (int &M : Mask)
> M = VMask[M];
> V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
> - getV4X86ShuffleImm8ForMask(Mask, DAG));
> + getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
>
> // Check that the shuffles didn't cancel each other out. If not, we
> need to
> // combine to the new one.
> @@ -20297,7 +20329,7 @@ static SDValue PerformTargetShuffleCombi
> V = DAG.getNode(ISD::BITCAST, DL, DVT, V);
> DCI.AddToWorklist(V.getNode());
> V = DAG.getNode(X86ISD::PSHUFD, DL, DVT, V,
> - getV4X86ShuffleImm8ForMask(DMask, DAG));
> + getV4X86ShuffleImm8ForMask(DMask, DL, DAG));
> DCI.AddToWorklist(V.getNode());
> return DAG.getNode(ISD::BITCAST, DL, VT, V);
> }
> @@ -20727,11 +20759,11 @@ static SDValue PerformEXTRACT_VECTOR_ELT
> SDValue Cst = DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, InputVector);
> EVT VecIdxTy = DAG.getTargetLoweringInfo().getVectorIdxTy();
> SDValue BottomHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
> MVT::i64, Cst,
> - DAG.getConstant(0, VecIdxTy));
> + DAG.getConstant(0, dl, VecIdxTy));
> SDValue TopHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64,
> Cst,
> - DAG.getConstant(1, VecIdxTy));
> + DAG.getConstant(1, dl, VecIdxTy));
>
> - SDValue ShAmt = DAG.getConstant(32,
> + SDValue ShAmt = DAG.getConstant(32, dl,
> DAG.getTargetLoweringInfo().getShiftAmountTy(MVT::i64));
> Vals[0] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BottomHalf);
> Vals[1] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
> @@ -20751,7 +20783,7 @@ static SDValue PerformEXTRACT_VECTOR_ELT
> // Replace each use (extract) with a load of the appropriate element.
> for (unsigned i = 0; i < 4; ++i) {
> uint64_t Offset = EltSize * i;
> - SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
> + SDValue OffsetVal = DAG.getConstant(Offset, dl, TLI.getPointerTy());
>
> SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
> StackPtr, OffsetVal);
> @@ -21112,21 +21144,21 @@ static SDValue PerformSELECTCombine(SDNo
> TrueC->getAPIntValue().isPowerOf2()) {
> if (NeedsCondInvert) // Invert the condition if needed.
> Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
> - DAG.getConstant(1, Cond.getValueType()));
> + DAG.getConstant(1, DL,
> Cond.getValueType()));
>
> // Zero extend the condition if needed.
> Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(),
> Cond);
>
> unsigned ShAmt = TrueC->getAPIntValue().logBase2();
> return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
> - DAG.getConstant(ShAmt, MVT::i8));
> + DAG.getConstant(ShAmt, DL, MVT::i8));
> }
>
> // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
> if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
> if (NeedsCondInvert) // Invert the condition if needed.
> Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
> - DAG.getConstant(1, Cond.getValueType()));
> + DAG.getConstant(1, DL,
> Cond.getValueType()));
>
> // Zero extend the condition if needed.
> Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
> @@ -21161,7 +21193,7 @@ static SDValue PerformSELECTCombine(SDNo
> APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
> if (NeedsCondInvert) // Invert the condition if needed.
> Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
> - DAG.getConstant(1, Cond.getValueType()));
> + DAG.getConstant(1, DL,
> Cond.getValueType()));
>
> // Zero extend the condition if needed.
> Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
> FalseC->getValueType(0),
> @@ -21169,7 +21201,8 @@ static SDValue PerformSELECTCombine(SDNo
> // Scale the condition by the difference.
> if (Diff != 1)
> Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
> - DAG.getConstant(Diff,
> Cond.getValueType()));
> + DAG.getConstant(Diff, DL,
> + Cond.getValueType()));
>
> // Add the base if non-zero.
> if (FalseC->getAPIntValue() != 0)
> @@ -21257,7 +21290,7 @@ static SDValue PerformSELECTCombine(SDNo
> (-OpRHSConst->getAPIntValue() - 1))
> return DAG.getNode(
> X86ISD::SUBUS, DL, VT, OpLHS,
> - DAG.getConstant(-OpRHSConst->getAPIntValue(), VT));
> + DAG.getConstant(-OpRHSConst->getAPIntValue(), DL,
> VT));
>
> // Another special case: If C was a sign bit, the sub has been
> // canonicalized into a xor.
> @@ -21271,7 +21304,7 @@ static SDValue PerformSELECTCombine(SDNo
> // don't rely on particular values of undef lanes.
> return DAG.getNode(
> X86ISD::SUBUS, DL, VT, OpLHS,
> - DAG.getConstant(OpRHSConst->getAPIntValue(), VT));
> + DAG.getConstant(OpRHSConst->getAPIntValue(), DL, VT));
> }
> }
> }
> @@ -21665,7 +21698,7 @@ static SDValue PerformCMOVCombine(SDNode
> // Extra check as FCMOV only supports a subset of X86 cond.
> (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
> SDValue Ops[] = { FalseOp, TrueOp,
> - DAG.getConstant(CC, MVT::i8), Flags };
> + DAG.getConstant(CC, DL, MVT::i8), Flags };
> return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
> }
>
> @@ -21687,14 +21720,14 @@ static SDValue PerformCMOVCombine(SDNode
> // shift amount.
> if (FalseC->getAPIntValue() == 0 &&
> TrueC->getAPIntValue().isPowerOf2()) {
> Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
> - DAG.getConstant(CC, MVT::i8), Cond);
> + DAG.getConstant(CC, DL, MVT::i8), Cond);
>
> // Zero extend the condition if needed.
> Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0),
> Cond);
>
> unsigned ShAmt = TrueC->getAPIntValue().logBase2();
> Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
> - DAG.getConstant(ShAmt, MVT::i8));
> + DAG.getConstant(ShAmt, DL, MVT::i8));
> if (N->getNumValues() == 2) // Dead flag value?
> return DCI.CombineTo(N, Cond, SDValue());
> return Cond;
> @@ -21704,7 +21737,7 @@ static SDValue PerformCMOVCombine(SDNode
> // for any integer data type, including i8/i16.
> if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
> Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
> - DAG.getConstant(CC, MVT::i8), Cond);
> + DAG.getConstant(CC, DL, MVT::i8), Cond);
>
> // Zero extend the condition if needed.
> Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
> @@ -21742,14 +21775,14 @@ static SDValue PerformCMOVCombine(SDNode
> if (isFastMultiplier) {
> APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
> Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
> - DAG.getConstant(CC, MVT::i8), Cond);
> + DAG.getConstant(CC, DL, MVT::i8), Cond);
> // Zero extend the condition if needed.
> Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
> FalseC->getValueType(0),
> Cond);
> // Scale the condition by the difference.
> if (Diff != 1)
> Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
> - DAG.getConstant(Diff,
> Cond.getValueType()));
> + DAG.getConstant(Diff, DL,
> Cond.getValueType()));
>
> // Add the base if non-zero.
> if (FalseC->getAPIntValue() != 0)
> @@ -21795,7 +21828,7 @@ static SDValue PerformCMOVCombine(SDNode
> if (CC == X86::COND_E &&
> CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
> SDValue Ops[] = { FalseOp, Cond.getOperand(0),
> - DAG.getConstant(CC, MVT::i8), Cond };
> + DAG.getConstant(CC, DL, MVT::i8), Cond };
> return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
> }
> }
> @@ -21829,10 +21862,10 @@ static SDValue PerformCMOVCombine(SDNode
> CC1 = X86::GetOppositeBranchCondition(CC1);
> }
>
> - SDValue LOps[] = {FalseOp, TrueOp, DAG.getConstant(CC0, MVT::i8),
> + SDValue LOps[] = {FalseOp, TrueOp, DAG.getConstant(CC0, DL,
> MVT::i8),
> Flags};
> SDValue LCMOV = DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), LOps);
> - SDValue Ops[] = {LCMOV, TrueOp, DAG.getConstant(CC1, MVT::i8),
> Flags};
> + SDValue Ops[] = {LCMOV, TrueOp, DAG.getConstant(CC1, DL, MVT::i8),
> Flags};
> SDValue CMOV = DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
> DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1),
> SDValue(CMOV.getNode(), 1));
> return CMOV;
> @@ -21930,8 +21963,9 @@ static SDValue PerformINTRINSIC_WO_CHAIN
>
> // Replace this packed shift intrinsic with a target independent
> // shift dag node.
> - SDValue Splat = DAG.getConstant(C, VT);
> - return DAG.getNode(ISD::SRA, SDLoc(N), VT, Op0, Splat);
> + SDLoc DL(N);
> + SDValue Splat = DAG.getConstant(C, DL, VT);
> + return DAG.getNode(ISD::SRA, DL, VT, Op0, Splat);
> }
> }
> }
> @@ -21981,17 +22015,17 @@ static SDValue PerformMulCombine(SDNode
> SDValue NewMul;
> if (isPowerOf2_64(MulAmt1))
> NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
> - DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
> + DAG.getConstant(Log2_64(MulAmt1), DL,
> MVT::i8));
> else
> NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
> - DAG.getConstant(MulAmt1, VT));
> + DAG.getConstant(MulAmt1, DL, VT));
>
> if (isPowerOf2_64(MulAmt2))
> NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
> - DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
> + DAG.getConstant(Log2_64(MulAmt2), DL,
> MVT::i8));
> else
> NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
> - DAG.getConstant(MulAmt2, VT));
> + DAG.getConstant(MulAmt2, DL, VT));
>
> // Do not add new nodes to DAG combiner worklist.
> DCI.CombineTo(N, NewMul, false);
> @@ -22018,9 +22052,11 @@ static SDValue PerformSHLCombine(SDNode
> APInt Mask =
> cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
> APInt ShAmt = N1C->getAPIntValue();
> Mask = Mask.shl(ShAmt);
> - if (Mask != 0)
> - return DAG.getNode(ISD::AND, SDLoc(N), VT,
> - N00, DAG.getConstant(Mask, VT));
> + if (Mask != 0) {
> + SDLoc DL(N);
> + return DAG.getNode(ISD::AND, DL, VT,
> + N00, DAG.getConstant(Mask, DL, VT));
> + }
> }
> }
>
> @@ -22150,7 +22186,8 @@ static SDValue CMPEQCombine(SDNode *N, S
> unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
> if (Subtarget->hasAVX512()) {
> SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1,
> CMP00,
> - CMP01, DAG.getConstant(x86cc,
> MVT::i8));
> + CMP01,
> + DAG.getConstant(x86cc, DL,
> MVT::i8));
> if (N->getValueType(0) != MVT::i1)
> return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
> FSetCC);
> @@ -22158,7 +22195,8 @@ static SDValue CMPEQCombine(SDNode *N, S
> }
> SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
> CMP00.getValueType(),
> CMP00, CMP01,
> - DAG.getConstant(x86cc,
> MVT::i8));
> + DAG.getConstant(x86cc, DL,
> + MVT::i8));
>
> bool is64BitFP = (CMP00.getValueType() == MVT::f64);
> MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
> @@ -22174,14 +22212,16 @@ static SDValue CMPEQCombine(SDNode *N, S
> SDValue Vector32 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f32,
> Vector64);
> OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
> MVT::f32,
> - Vector32,
> DAG.getIntPtrConstant(0));
> + Vector32,
> DAG.getIntPtrConstant(0, DL));
> IntVT = MVT::i32;
> }
>
> - SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, IntVT,
> OnesOrZeroesF);
> + SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, IntVT,
> + OnesOrZeroesF);
> SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
> - DAG.getConstant(1, IntVT));
> - SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8,
> ANDed);
> + DAG.getConstant(1, DL, IntVT));
> + SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8,
> + ANDed);
> return OneBitOfTruth;
> }
> }
> @@ -22293,7 +22333,7 @@ static SDValue WidenMaskArithmetic(SDNod
> APInt Mask = APInt::getAllOnesValue(InBits);
> Mask = Mask.zext(VT.getScalarType().getSizeInBits());
> return DAG.getNode(ISD::AND, DL, VT,
> - Op, DAG.getConstant(Mask, VT));
> + Op, DAG.getConstant(Mask, DL, VT));
> }
> case ISD::SIGN_EXTEND:
> return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
> @@ -22389,8 +22429,8 @@ static SDValue VectorZextCombine(SDNode
> Mask.push_back(i / ZextRatio);
>
> SDValue NewShuffle = DAG.getVectorShuffle(Shuffle->getValueType(0), DL,
> - Shuffle->getOperand(0), DAG.getConstant(0, SrcType), Mask);
> - return DAG.getNode(ISD::BITCAST, DL, N0.getValueType(), NewShuffle);
> + Shuffle->getOperand(0), DAG.getConstant(0, DL, SrcType), Mask);
> + return DAG.getNode(ISD::BITCAST, DL, N0.getValueType(), NewShuffle);
> }
>
> static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
> @@ -22425,7 +22465,8 @@ static SDValue PerformAndCombine(SDNode
> uint64_t MaskSize = countPopulation(Mask);
> if (Shift + MaskSize <= VT.getSizeInBits())
> return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
> - DAG.getConstant(Shift | (MaskSize << 8),
> VT));
> + DAG.getConstant(Shift | (MaskSize << 8),
> DL,
> + VT));
> }
> }
> } // BEXTR
> @@ -22640,10 +22681,10 @@ static SDValue performIntegerAbsCombine(
> if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
> // Generate SUB & CMOV.
> SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT,
> MVT::i32),
> - DAG.getConstant(0, VT),
> N0.getOperand(0));
> + DAG.getConstant(0, DL, VT),
> N0.getOperand(0));
>
> SDValue Ops[] = { N0.getOperand(0), Neg,
> - DAG.getConstant(X86::COND_GE, MVT::i8),
> + DAG.getConstant(X86::COND_GE, DL, MVT::i8),
> SDValue(Neg.getNode(), 1) };
> return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT,
> MVT::Glue), Ops);
> }
> @@ -22688,7 +22729,7 @@ static SDValue PerformLOADCombine(SDNode
> return SDValue();
>
> SDValue Ptr = Ld->getBasePtr();
> - SDValue Increment = DAG.getConstant(16, TLI.getPointerTy());
> + SDValue Increment = DAG.getConstant(16, dl, TLI.getPointerTy());
>
> EVT HalfVT = EVT::getVectorVT(*DAG.getContext(),
> MemVT.getScalarType(),
> NumElems/2);
> @@ -22767,7 +22808,7 @@ static SDValue PerformMLOADCombine(SDNod
> for (unsigned i = NumElems; i != NumElems*SizeRatio; ++i)
> ShuffleVec[i] = NumElems*SizeRatio;
> NewMask = DAG.getVectorShuffle(WideVecVT, dl, NewMask,
> - DAG.getConstant(0, WideVecVT),
> + DAG.getConstant(0, dl, WideVecVT),
> &ShuffleVec[0]);
> }
> else {
> @@ -22779,7 +22820,7 @@ static SDValue PerformMLOADCombine(SDNod
>
> unsigned NumConcat = WidenNumElts / MaskNumElts;
> SmallVector<SDValue, 16> Ops(NumConcat);
> - SDValue ZeroVal = DAG.getConstant(0, Mask.getValueType());
> + SDValue ZeroVal = DAG.getConstant(0, dl, Mask.getValueType());
> Ops[0] = Mask;
> for (unsigned i = 1; i != NumConcat; ++i)
> Ops[i] = ZeroVal;
> @@ -22851,7 +22892,7 @@ static SDValue PerformMSTORECombine(SDNo
> for (unsigned i = NumElems; i != NumElems*SizeRatio; ++i)
> ShuffleVec[i] = NumElems*SizeRatio;
> NewMask = DAG.getVectorShuffle(WideVecVT, dl, NewMask,
> - DAG.getConstant(0, WideVecVT),
> + DAG.getConstant(0, dl, WideVecVT),
> &ShuffleVec[0]);
> }
> else {
> @@ -22863,7 +22904,7 @@ static SDValue PerformMSTORECombine(SDNo
>
> unsigned NumConcat = WidenNumElts / MaskNumElts;
> SmallVector<SDValue, 16> Ops(NumConcat);
> - SDValue ZeroVal = DAG.getConstant(0, Mask.getValueType());
> + SDValue ZeroVal = DAG.getConstant(0, dl, Mask.getValueType());
> Ops[0] = Mask;
> for (unsigned i = 1; i != NumConcat; ++i)
> Ops[i] = ZeroVal;
> @@ -22897,7 +22938,7 @@ static SDValue PerformSTORECombine(SDNod
> SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
> SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
>
> - SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
> + SDValue Stride = DAG.getConstant(16, dl, TLI.getPointerTy());
> SDValue Ptr0 = St->getBasePtr();
> SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0,
> Stride);
>
> @@ -22970,7 +23011,7 @@ static SDValue PerformSTORECombine(SDNod
> assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
> SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
> SmallVector<SDValue, 8> Chains;
> - SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
> + SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8, dl,
> TLI.getPointerTy());
> SDValue Ptr = St->getBasePtr();
>
> @@ -22978,7 +23019,7 @@ static SDValue PerformSTORECombine(SDNod
> for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e;
> ++i) {
> SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
> StoreType, ShuffWide,
> - DAG.getIntPtrConstant(i));
> + DAG.getIntPtrConstant(i, dl));
> SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
> St->getPointerInfo(), St->isVolatile(),
> St->isNonTemporal(), St->getAlignment());
> @@ -23062,7 +23103,7 @@ static SDValue PerformSTORECombine(SDNod
> // Otherwise, lower to two pairs of 32-bit loads / stores.
> SDValue LoAddr = Ld->getBasePtr();
> SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
> - DAG.getConstant(4, MVT::i32));
> + DAG.getConstant(4, LdDL, MVT::i32));
>
> SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
> Ld->getPointerInfo(),
> @@ -23083,7 +23124,7 @@ static SDValue PerformSTORECombine(SDNod
>
> LoAddr = St->getBasePtr();
> HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
> - DAG.getConstant(4, MVT::i32));
> + DAG.getConstant(4, StDL, MVT::i32));
>
> SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
> St->getPointerInfo(),
> @@ -23507,7 +23548,7 @@ static SDValue PerformZExtCombine(SDNode
> return DAG.getNode(ISD::AND, dl, VT,
> DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
> N00.getOperand(0),
> N00.getOperand(1)),
> - DAG.getConstant(1, VT));
> + DAG.getConstant(1, dl, VT));
> }
> }
>
> @@ -23519,7 +23560,7 @@ static SDValue PerformZExtCombine(SDNode
> return DAG.getNode(ISD::AND, dl, VT,
> DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
> N00.getOperand(0),
> N00.getOperand(1)),
> - DAG.getConstant(1, VT));
> + DAG.getConstant(1, dl, VT));
> }
> }
> if (VT.is256BitVector()) {
> @@ -23558,18 +23599,18 @@ static SDValue PerformISDSETCCCombine(SD
> if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() ==
> ISD::SUB)
> if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
> if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
> - SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
> LHS.getValueType(), RHS,
> + SDValue addV = DAG.getNode(ISD::ADD, DL, LHS.getValueType(), RHS,
> LHS.getOperand(1));
> - return DAG.getSetCC(SDLoc(N), N->getValueType(0), addV,
> - DAG.getConstant(0, addV.getValueType()), CC);
> + return DAG.getSetCC(DL, N->getValueType(0), addV,
> + DAG.getConstant(0, DL, addV.getValueType()),
> CC);
> }
> if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() ==
> ISD::SUB)
> if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
> if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
> - SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
> RHS.getValueType(), LHS,
> + SDValue addV = DAG.getNode(ISD::ADD, DL, RHS.getValueType(), LHS,
> RHS.getOperand(1));
> - return DAG.getSetCC(SDLoc(N), N->getValueType(0), addV,
> - DAG.getConstant(0, addV.getValueType()), CC);
> + return DAG.getSetCC(DL, N->getValueType(0), addV,
> + DAG.getConstant(0, DL, addV.getValueType()),
> CC);
> }
>
> if (VT.getScalarType() == MVT::i1 &&
> @@ -23593,9 +23634,9 @@ static SDValue PerformISDSETCCCombine(SD
> assert(VT == LHS.getOperand(0).getValueType() &&
> "Uexpected operand type");
> if (CC == ISD::SETGT)
> - return DAG.getConstant(0, VT);
> + return DAG.getConstant(0, DL, VT);
> if (CC == ISD::SETLE)
> - return DAG.getConstant(1, VT);
> + return DAG.getConstant(1, DL, VT);
> if (CC == ISD::SETEQ || CC == ISD::SETGE)
> return DAG.getNOT(DL, LHS.getOperand(0), VT);
>
> @@ -23616,7 +23657,8 @@ static SDValue NarrowVectorLoadToElement
> SDValue Addr = Load->getOperand(1);
> SDValue NewAddr = DAG.getNode(
> ISD::ADD, dl, Addr.getSimpleValueType(), Addr,
> - DAG.getConstant(Index * EVT.getStoreSize(),
> Addr.getSimpleValueType()));
> + DAG.getConstant(Index * EVT.getStoreSize(), dl,
> + Addr.getSimpleValueType()));
>
> SDValue NewLoad =
> DAG.getLoad(EVT, dl, Load->getChain(), NewAddr,
> @@ -23672,7 +23714,7 @@ static SDValue PerformBLENDICombine(SDNo
> if (VT == MVT::v2f64)
> if (auto *Mask = dyn_cast<ConstantSDNode>(N->getOperand(2)))
> if (Mask->getZExtValue() == 2 && !isShuffleFoldableLoad(V0)) {
> - SDValue NewMask = DAG.getConstant(1, MVT::i8);
> + SDValue NewMask = DAG.getConstant(1, DL, MVT::i8);
> return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V0, NewMask);
> }
>
> @@ -23687,12 +23729,14 @@ static SDValue MaterializeSETB(SDLoc DL,
> if (VT == MVT::i8)
> return DAG.getNode(ISD::AND, DL, VT,
> DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
> - DAG.getConstant(X86::COND_B, MVT::i8),
> EFLAGS),
> - DAG.getConstant(1, VT));
> + DAG.getConstant(X86::COND_B, DL,
> MVT::i8),
> + EFLAGS),
> + DAG.getConstant(1, DL, VT));
> assert (VT == MVT::i1 && "Unexpected type for SECCC node");
> return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
> DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
> - DAG.getConstant(X86::COND_B, MVT::i8),
> EFLAGS));
> + DAG.getConstant(X86::COND_B, DL,
> MVT::i8),
> + EFLAGS));
> }
>
> // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
> @@ -23731,7 +23775,7 @@ static SDValue PerformSETCCCombine(SDNod
>
> Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
> if (Flags.getNode()) {
> - SDValue Cond = DAG.getConstant(CC, MVT::i8);
> + SDValue Cond = DAG.getConstant(CC, DL, MVT::i8);
> return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
> }
>
> @@ -23753,7 +23797,7 @@ static SDValue PerformBrCondCombine(SDNo
>
> Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
> if (Flags.getNode()) {
> - SDValue Cond = DAG.getConstant(CC, MVT::i8);
> + SDValue Cond = DAG.getConstant(CC, DL, MVT::i8);
> return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest,
> Cond,
> Flags);
> }
> @@ -23857,12 +23901,13 @@ static SDValue PerformADCCombine(SDNode
> SDValue(N, 1).use_empty()) {
> SDLoc DL(N);
> EVT VT = N->getValueType(0);
> - SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
> + SDValue CarryOut = DAG.getConstant(0, DL, N->getValueType(1));
> SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
> DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
> -
> DAG.getConstant(X86::COND_B,MVT::i8),
> + DAG.getConstant(X86::COND_B,
> DL,
> + MVT::i8),
> N->getOperand(2)),
> - DAG.getConstant(1, VT));
> + DAG.getConstant(1, DL, VT));
> return DCI.CombineTo(N, Res1, CarryOut);
> }
>
> @@ -23897,16 +23942,17 @@ static SDValue OptimizeConditionalInDecr
>
> SDValue CmpOp0 = Cmp.getOperand(0);
> SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
> - DAG.getConstant(1, CmpOp0.getValueType()));
> + DAG.getConstant(1, DL,
> CmpOp0.getValueType()));
>
> SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
> if (CC == X86::COND_NE)
> return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC :
> X86ISD::SBB,
> DL, OtherVal.getValueType(), OtherVal,
> - DAG.getConstant(-1ULL, OtherVal.getValueType()),
> NewCmp);
> + DAG.getConstant(-1ULL, DL,
> OtherVal.getValueType()),
> + NewCmp);
> return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB :
> X86ISD::ADC,
> DL, OtherVal.getValueType(), OtherVal,
> - DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
> + DAG.getConstant(0, DL, OtherVal.getValueType()),
> NewCmp);
> }
>
> /// PerformADDCombine - Do target-specific dag combines on integer adds.
> @@ -23942,9 +23988,9 @@ static SDValue PerformSubCombine(SDNode
> EVT VT = Op0.getValueType();
> SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
> Op1.getOperand(0),
> - DAG.getConstant(~XorC, VT));
> + DAG.getConstant(~XorC, SDLoc(Op1),
> VT));
> return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
> - DAG.getConstant(C->getAPIntValue()+1, VT));
> + DAG.getConstant(C->getAPIntValue() + 1,
> SDLoc(N), VT));
> }
> }
>
> @@ -24014,7 +24060,7 @@ static SDValue performVZEXTCombine(SDNod
> OrigVT = MVT::getVectorVT(OrigVT.getVectorElementType(),
> OrigVT.getVectorNumElements() /
> Ratio);
> OrigV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigVT, OrigV,
> - DAG.getIntPtrConstant(0));
> + DAG.getIntPtrConstant(0, DL));
> }
> Op = DAG.getNode(ISD::BITCAST, DL, OpVT, OrigV);
> return DAG.getNode(X86ISD::VZEXT, DL, VT, Op);
> @@ -24495,7 +24541,8 @@ void X86TargetLowering::LowerAsmOperandF
> case 'I':
> if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
> if (C->getZExtValue() <= 31) {
> - Result = DAG.getTargetConstant(C->getZExtValue(),
> Op.getValueType());
> + Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
> + Op.getValueType());
> break;
> }
> }
> @@ -24503,7 +24550,8 @@ void X86TargetLowering::LowerAsmOperandF
> case 'J':
> if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
> if (C->getZExtValue() <= 63) {
> - Result = DAG.getTargetConstant(C->getZExtValue(),
> Op.getValueType());
> + Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
> + Op.getValueType());
> break;
> }
> }
> @@ -24511,7 +24559,8 @@ void X86TargetLowering::LowerAsmOperandF
> case 'K':
> if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
> if (isInt<8>(C->getSExtValue())) {
> - Result = DAG.getTargetConstant(C->getZExtValue(),
> Op.getValueType());
> + Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
> + Op.getValueType());
> break;
> }
> }
> @@ -24520,7 +24569,8 @@ void X86TargetLowering::LowerAsmOperandF
> if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
> if (C->getZExtValue() == 0xff || C->getZExtValue() == 0xffff ||
> (Subtarget->is64Bit() && C->getZExtValue() == 0xffffffff)) {
> - Result = DAG.getTargetConstant(C->getSExtValue(),
> Op.getValueType());
> + Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op),
> + Op.getValueType());
> break;
> }
> }
> @@ -24528,7 +24578,8 @@ void X86TargetLowering::LowerAsmOperandF
> case 'M':
> if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
> if (C->getZExtValue() <= 3) {
> - Result = DAG.getTargetConstant(C->getZExtValue(),
> Op.getValueType());
> + Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
> + Op.getValueType());
> break;
> }
> }
> @@ -24536,7 +24587,8 @@ void X86TargetLowering::LowerAsmOperandF
> case 'N':
> if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
> if (C->getZExtValue() <= 255) {
> - Result = DAG.getTargetConstant(C->getZExtValue(),
> Op.getValueType());
> + Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
> + Op.getValueType());
> break;
> }
> }
> @@ -24544,7 +24596,8 @@ void X86TargetLowering::LowerAsmOperandF
> case 'O':
> if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
> if (C->getZExtValue() <= 127) {
> - Result = DAG.getTargetConstant(C->getZExtValue(),
> Op.getValueType());
> + Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
> + Op.getValueType());
> break;
> }
> }
> @@ -24555,7 +24608,7 @@ void X86TargetLowering::LowerAsmOperandF
> if
> (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
> C->getSExtValue())) {
> // Widen to 64 bits here to get it sign extended.
> - Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
> + Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op),
> MVT::i64);
> break;
> }
> // FIXME gcc accepts some relocatable values here too, but only in
> certain
> @@ -24568,7 +24621,8 @@ void X86TargetLowering::LowerAsmOperandF
> if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
> if
> (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
> C->getZExtValue())) {
> - Result = DAG.getTargetConstant(C->getZExtValue(),
> Op.getValueType());
> + Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
> + Op.getValueType());
> break;
> }
> }
> @@ -24580,7 +24634,7 @@ void X86TargetLowering::LowerAsmOperandF
> // Literal immediates are always ok.
> if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
> // Widen to 64 bits here to get it sign extended.
> - Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
> + Result = DAG.getTargetConstant(CST->getSExtValue(), SDLoc(Op),
> MVT::i64);
> break;
> }
>
>
> Modified: llvm/trunk/lib/Target/X86/X86InstrCompiler.td
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrCompiler.td?rev=235977&r1=235976&r2=235977&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86InstrCompiler.td (original)
> +++ llvm/trunk/lib/Target/X86/X86InstrCompiler.td Tue Apr 28 06:56:37 2015
> @@ -17,12 +17,12 @@
>
> def GetLo32XForm : SDNodeXForm<imm, [{
> // Transformation function: get the low 32 bits.
> - return getI32Imm((unsigned)N->getZExtValue());
> + return getI32Imm((unsigned)N->getZExtValue(), SDLoc(N));
> }]>;
>
> def GetLo8XForm : SDNodeXForm<imm, [{
> // Transformation function: get the low 8 bits.
> - return getI8Imm((uint8_t)N->getZExtValue());
> + return getI8Imm((uint8_t)N->getZExtValue(), SDLoc(N));
> }]>;
>
>
>
> Modified: llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td?rev=235977&r1=235976&r2=235977&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td (original)
> +++ llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td Tue Apr 28 06:56:37
> 2015
> @@ -566,7 +566,7 @@ def fp32imm0 : PatLeaf<(f32 fpimm), [{
>
> def I8Imm : SDNodeXForm<imm, [{
> // Transformation function: get the low 8 bits.
> - return getI8Imm((uint8_t)N->getZExtValue());
> + return getI8Imm((uint8_t)N->getZExtValue(), SDLoc(N));
> }]>;
>
> def FROUND_NO_EXC : ImmLeaf<i32, [{ return Imm == 8; }]>;
> @@ -577,31 +577,31 @@ def FROUND_CURRENT : ImmLeaf<i32, [{
> // BYTE_imm - Transform bit immediates into byte immediates.
> def BYTE_imm : SDNodeXForm<imm, [{
> // Transformation function: imm >> 3
> - return getI32Imm(N->getZExtValue() >> 3);
> + return getI32Imm(N->getZExtValue() >> 3, SDLoc(N));
> }]>;
>
> // EXTRACT_get_vextract128_imm xform function: convert extract_subvector
> index
> // to VEXTRACTF128/VEXTRACTI128 imm.
> def EXTRACT_get_vextract128_imm : SDNodeXForm<extract_subvector, [{
> - return getI8Imm(X86::getExtractVEXTRACT128Immediate(N));
> + return getI8Imm(X86::getExtractVEXTRACT128Immediate(N), SDLoc(N));
> }]>;
>
> // INSERT_get_vinsert128_imm xform function: convert insert_subvector
> index to
> // VINSERTF128/VINSERTI128 imm.
> def INSERT_get_vinsert128_imm : SDNodeXForm<insert_subvector, [{
> - return getI8Imm(X86::getInsertVINSERT128Immediate(N));
> + return getI8Imm(X86::getInsertVINSERT128Immediate(N), SDLoc(N));
> }]>;
>
> // EXTRACT_get_vextract256_imm xform function: convert extract_subvector
> index
> // to VEXTRACTF64x4 imm.
> def EXTRACT_get_vextract256_imm : SDNodeXForm<extract_subvector, [{
> - return getI8Imm(X86::getExtractVEXTRACT256Immediate(N));
> + return getI8Imm(X86::getExtractVEXTRACT256Immediate(N), SDLoc(N));
> }]>;
>
> // INSERT_get_vinsert256_imm xform function: convert insert_subvector
> index to
> // VINSERTF64x4 imm.
> def INSERT_get_vinsert256_imm : SDNodeXForm<insert_subvector, [{
> - return getI8Imm(X86::getInsertVINSERT256Immediate(N));
> + return getI8Imm(X86::getInsertVINSERT256Immediate(N), SDLoc(N));
> }]>;
>
> def vextract128_extract : PatFrag<(ops node:$bigvec, node:$index),
>
> Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=235977&r1=235976&r2=235977&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original)
> +++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Tue Apr 28 06:56:37 2015
> @@ -2223,7 +2223,7 @@ let Predicates = [HasBMI2], Defs = [EFLA
>
> def CountTrailingOnes : SDNodeXForm<imm, [{
> // Count the trailing ones in the immediate.
> - return getI8Imm(countTrailingOnes(N->getZExtValue()));
> + return getI8Imm(countTrailingOnes(N->getZExtValue()), SDLoc(N));
> }]>;
>
> def BZHIMask : ImmLeaf<i64, [{
>
> Modified: llvm/trunk/lib/Target/X86/X86InstrShiftRotate.td
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrShiftRotate.td?rev=235977&r1=235976&r2=235977&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86InstrShiftRotate.td (original)
> +++ llvm/trunk/lib/Target/X86/X86InstrShiftRotate.td Tue Apr 28 06:56:37
> 2015
> @@ -850,12 +850,12 @@ def SHRD64mri8 : RIi8<0xAC, MRMDestMem,
>
> def ROT32L2R_imm8 : SDNodeXForm<imm, [{
> // Convert a ROTL shamt to a ROTR shamt on 32-bit integer.
> - return getI8Imm(32 - N->getZExtValue());
> + return getI8Imm(32 - N->getZExtValue(), SDLoc(N));
> }]>;
>
> def ROT64L2R_imm8 : SDNodeXForm<imm, [{
> // Convert a ROTL shamt to a ROTR shamt on 64-bit integer.
> - return getI8Imm(64 - N->getZExtValue());
> + return getI8Imm(64 - N->getZExtValue(), SDLoc(N));
> }]>;
>
> multiclass bmi_rotate<string asm, RegisterClass RC, X86MemOperand
> x86memop> {
>
> Modified: llvm/trunk/lib/Target/X86/X86SelectionDAGInfo.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SelectionDAGInfo.cpp?rev=235977&r1=235976&r2=235977&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86SelectionDAGInfo.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86SelectionDAGInfo.cpp Tue Apr 28 06:56:37
> 2015
> @@ -138,22 +138,22 @@ X86SelectionDAGInfo::EmitTargetCodeForMe
> default: // Byte aligned
> AVT = MVT::i8;
> ValReg = X86::AL;
> - Count = DAG.getIntPtrConstant(SizeVal);
> + Count = DAG.getIntPtrConstant(SizeVal, dl);
> break;
> }
>
> if (AVT.bitsGT(MVT::i8)) {
> unsigned UBytes = AVT.getSizeInBits() / 8;
> - Count = DAG.getIntPtrConstant(SizeVal / UBytes);
> + Count = DAG.getIntPtrConstant(SizeVal / UBytes, dl);
> BytesLeft = SizeVal % UBytes;
> }
>
> - Chain = DAG.getCopyToReg(Chain, dl, ValReg, DAG.getConstant(Val,
> AVT),
> + Chain = DAG.getCopyToReg(Chain, dl, ValReg, DAG.getConstant(Val, dl,
> AVT),
> InFlag);
> InFlag = Chain.getValue(1);
> } else {
> AVT = MVT::i8;
> - Count = DAG.getIntPtrConstant(SizeVal);
> + Count = DAG.getIntPtrConstant(SizeVal, dl);
> Chain = DAG.getCopyToReg(Chain, dl, X86::AL, Src, InFlag);
> InFlag = Chain.getValue(1);
> }
> @@ -174,7 +174,8 @@ X86SelectionDAGInfo::EmitTargetCodeForMe
> Count = Size;
> EVT CVT = Count.getValueType();
> SDValue Left = DAG.getNode(ISD::AND, dl, CVT, Count,
> - DAG.getConstant((AVT == MVT::i64) ? 7 : 3,
> CVT));
> + DAG.getConstant((AVT == MVT::i64) ? 7 : 3,
> dl,
> + CVT));
> Chain = DAG.getCopyToReg(Chain, dl, (CVT == MVT::i64) ? X86::RCX :
> X86::ECX,
> Left, InFlag);
> @@ -190,9 +191,9 @@ X86SelectionDAGInfo::EmitTargetCodeForMe
>
> Chain = DAG.getMemset(Chain, dl,
> DAG.getNode(ISD::ADD, dl, AddrVT, Dst,
> - DAG.getConstant(Offset, AddrVT)),
> + DAG.getConstant(Offset, dl,
> AddrVT)),
> Src,
> - DAG.getConstant(BytesLeft, SizeVT),
> + DAG.getConstant(BytesLeft, dl, SizeVT),
> Align, isVolatile, false,
> DstPtrInfo.getWithOffset(Offset));
> }
> @@ -248,7 +249,7 @@ SDValue X86SelectionDAGInfo::EmitTargetC
>
> unsigned UBytes = AVT.getSizeInBits() / 8;
> unsigned CountVal = SizeVal / UBytes;
> - SDValue Count = DAG.getIntPtrConstant(CountVal);
> + SDValue Count = DAG.getIntPtrConstant(CountVal, dl);
> unsigned BytesLeft = SizeVal % UBytes;
>
> SDValue InFlag;
> @@ -279,10 +280,12 @@ SDValue X86SelectionDAGInfo::EmitTargetC
> EVT SizeVT = Size.getValueType();
> Results.push_back(DAG.getMemcpy(Chain, dl,
> DAG.getNode(ISD::ADD, dl, DstVT, Dst,
> - DAG.getConstant(Offset,
> DstVT)),
> + DAG.getConstant(Offset,
> dl,
> + DstVT)),
> DAG.getNode(ISD::ADD, dl, SrcVT, Src,
> - DAG.getConstant(Offset,
> SrcVT)),
> - DAG.getConstant(BytesLeft, SizeVT),
> + DAG.getConstant(Offset,
> dl,
> + SrcVT)),
> + DAG.getConstant(BytesLeft, dl,
> SizeVT),
> Align, isVolatile, AlwaysInline,
> false,
> DstPtrInfo.getWithOffset(Offset),
> SrcPtrInfo.getWithOffset(Offset)));
>
> Modified: llvm/trunk/lib/Target/XCore/XCoreISelDAGToDAG.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreISelDAGToDAG.cpp?rev=235977&r1=235976&r2=235977&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/XCore/XCoreISelDAGToDAG.cpp (original)
> +++ llvm/trunk/lib/Target/XCore/XCoreISelDAGToDAG.cpp Tue Apr 28 06:56:37
> 2015
> @@ -47,8 +47,8 @@ namespace {
>
> /// getI32Imm - Return a target constant with the specified value, of
> type
> /// i32.
> - inline SDValue getI32Imm(unsigned Imm) {
> - return CurDAG->getTargetConstant(Imm, MVT::i32);
> + inline SDValue getI32Imm(unsigned Imm, SDLoc dl) {
> + return CurDAG->getTargetConstant(Imm, dl, MVT::i32);
> }
>
> inline bool immMskBitp(SDNode *inN) const {
> @@ -90,7 +90,7 @@ bool XCoreDAGToDAGISel::SelectADDRspii(S
> FrameIndexSDNode *FIN = nullptr;
> if ((FIN = dyn_cast<FrameIndexSDNode>(Addr))) {
> Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
> - Offset = CurDAG->getTargetConstant(0, MVT::i32);
> + Offset = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i32);
> return true;
> }
> if (Addr.getOpcode() == ISD::ADD) {
> @@ -100,7 +100,8 @@ bool XCoreDAGToDAGISel::SelectADDRspii(S
> && (CN->getSExtValue() % 4 == 0 && CN->getSExtValue() >= 0)) {
> // Constant positive word offset from frame index
> Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
> - Offset = CurDAG->getTargetConstant(CN->getSExtValue(), MVT::i32);
> + Offset = CurDAG->getTargetConstant(CN->getSExtValue(), SDLoc(Addr),
> + MVT::i32);
> return true;
> }
> }
> @@ -138,7 +139,7 @@ SDNode *XCoreDAGToDAGISel::Select(SDNode
> if (immMskBitp(N)) {
> // Transformation function: get the size of a mask
> // Look for the first non-zero bit
> - SDValue MskSize = getI32Imm(32 - countLeadingZeros((uint32_t)Val));
> + SDValue MskSize = getI32Imm(32 - countLeadingZeros((uint32_t)Val),
> dl);
> return CurDAG->getMachineNode(XCore::MKMSK_rus, dl,
> MVT::i32, MskSize);
> }
> @@ -256,7 +257,7 @@ SDNode *XCoreDAGToDAGISel::SelectBRIND(S
> // after with clrsr 1. If any resources owned by the thread are ready
> an event
> // will be taken. If no resource is ready we branch to the address
> which was
> // the operand to the checkevent intrinsic.
> - SDValue constOne = getI32Imm(1);
> + SDValue constOne = getI32Imm(1, dl);
> SDValue Glue =
> SDValue(CurDAG->getMachineNode(XCore::SETSR_branch_u6, dl, MVT::Glue,
> constOne, Chain), 0);
>
> Modified: llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp?rev=235977&r1=235976&r2=235977&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp Tue Apr 28 06:56:37
> 2015
> @@ -298,7 +298,7 @@ LowerGlobalAddress(SDValue Op, Selection
> GA = getGlobalAddressWrapper(GA, GV, DAG);
> // Handle the rest of the offset.
> if (Offset != FoldedOffset) {
> - SDValue Remaining = DAG.getConstant(Offset - FoldedOffset,
> MVT::i32);
> + SDValue Remaining = DAG.getConstant(Offset - FoldedOffset, DL,
> MVT::i32);
> GA = DAG.getNode(ISD::ADD, DL, MVT::i32, GA, Remaining);
> }
> return GA;
> @@ -368,7 +368,7 @@ LowerBR_JT(SDValue Op, SelectionDAG &DAG
> }
> assert((NumEntries >> 31) == 0);
> SDValue ScaledIndex = DAG.getNode(ISD::SHL, dl, MVT::i32, Index,
> - DAG.getConstant(1, MVT::i32));
> + DAG.getConstant(1, dl, MVT::i32));
> return DAG.getNode(XCoreISD::BR_JT32, dl, MVT::Other, Chain, TargetJT,
> ScaledIndex);
> }
> @@ -393,12 +393,12 @@ lowerLoadWordFromAlignedBasePlusOffset(S
> HighOffset);
> } else {
> LowAddr = DAG.getNode(ISD::ADD, DL, MVT::i32, Base,
> - DAG.getConstant(LowOffset, MVT::i32));
> + DAG.getConstant(LowOffset, DL, MVT::i32));
> HighAddr = DAG.getNode(ISD::ADD, DL, MVT::i32, Base,
> - DAG.getConstant(HighOffset, MVT::i32));
> + DAG.getConstant(HighOffset, DL, MVT::i32));
> }
> - SDValue LowShift = DAG.getConstant((Offset - LowOffset) * 8, MVT::i32);
> - SDValue HighShift = DAG.getConstant((HighOffset - Offset) * 8,
> MVT::i32);
> + SDValue LowShift = DAG.getConstant((Offset - LowOffset) * 8, DL,
> MVT::i32);
> + SDValue HighShift = DAG.getConstant((HighOffset - Offset) * 8, DL,
> MVT::i32);
>
> SDValue Low = DAG.getLoad(getPointerTy(), DL, Chain,
> LowAddr, MachinePointerInfo(),
> @@ -469,14 +469,14 @@ LowerLOAD(SDValue Op, SelectionDAG &DAG)
> LD->isVolatile(), LD->isNonTemporal(),
> LD->isInvariant(), 2);
> SDValue HighAddr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr,
> - DAG.getConstant(2, MVT::i32));
> + DAG.getConstant(2, DL, MVT::i32));
> SDValue High = DAG.getExtLoad(ISD::EXTLOAD, DL, MVT::i32, Chain,
> HighAddr,
> LD->getPointerInfo().getWithOffset(2),
> MVT::i16, LD->isVolatile(),
> LD->isNonTemporal(), LD->isInvariant(),
> 2);
> SDValue HighShifted = DAG.getNode(ISD::SHL, DL, MVT::i32, High,
> - DAG.getConstant(16, MVT::i32));
> + DAG.getConstant(16, DL, MVT::i32));
> SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i32, Low, HighShifted);
> Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Low.getValue(1),
> High.getValue(1));
> @@ -529,13 +529,13 @@ LowerSTORE(SDValue Op, SelectionDAG &DAG
> if (ST->getAlignment() == 2) {
> SDValue Low = Value;
> SDValue High = DAG.getNode(ISD::SRL, dl, MVT::i32, Value,
> - DAG.getConstant(16, MVT::i32));
> + DAG.getConstant(16, dl, MVT::i32));
> SDValue StoreLow = DAG.getTruncStore(Chain, dl, Low, BasePtr,
> ST->getPointerInfo(), MVT::i16,
> ST->isVolatile(),
> ST->isNonTemporal(),
> 2);
> SDValue HighAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, BasePtr,
> - DAG.getConstant(2, MVT::i32));
> + DAG.getConstant(2, dl, MVT::i32));
> SDValue StoreHigh = DAG.getTruncStore(Chain, dl, High, HighAddr,
>
> ST->getPointerInfo().getWithOffset(2),
> MVT::i16, ST->isVolatile(),
> @@ -573,7 +573,7 @@ LowerSMUL_LOHI(SDValue Op, SelectionDAG
> SDLoc dl(Op);
> SDValue LHS = Op.getOperand(0);
> SDValue RHS = Op.getOperand(1);
> - SDValue Zero = DAG.getConstant(0, MVT::i32);
> + SDValue Zero = DAG.getConstant(0, dl, MVT::i32);
> SDValue Hi = DAG.getNode(XCoreISD::MACCS, dl,
> DAG.getVTList(MVT::i32, MVT::i32), Zero, Zero,
> LHS, RHS);
> @@ -590,7 +590,7 @@ LowerUMUL_LOHI(SDValue Op, SelectionDAG
> SDLoc dl(Op);
> SDValue LHS = Op.getOperand(0);
> SDValue RHS = Op.getOperand(1);
> - SDValue Zero = DAG.getConstant(0, MVT::i32);
> + SDValue Zero = DAG.getConstant(0, dl, MVT::i32);
> SDValue Hi = DAG.getNode(XCoreISD::LMUL, dl,
> DAG.getVTList(MVT::i32, MVT::i32), LHS, RHS,
> Zero, Zero);
> @@ -675,13 +675,13 @@ TryExpandADDWithMul(SDNode *N, Selection
> SDLoc dl(N);
> SDValue LL, RL, AddendL, AddendH;
> LL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
> - Mul.getOperand(0), DAG.getConstant(0, MVT::i32));
> + Mul.getOperand(0), DAG.getConstant(0, dl, MVT::i32));
> RL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
> - Mul.getOperand(1), DAG.getConstant(0, MVT::i32));
> + Mul.getOperand(1), DAG.getConstant(0, dl, MVT::i32));
> AddendL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
> - Other, DAG.getConstant(0, MVT::i32));
> + Other, DAG.getConstant(0, dl, MVT::i32));
> AddendH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
> - Other, DAG.getConstant(1, MVT::i32));
> + Other, DAG.getConstant(1, dl, MVT::i32));
> APInt HighMask = APInt::getHighBitsSet(64, 32);
> unsigned LHSSB = DAG.ComputeNumSignBits(Mul.getOperand(0));
> unsigned RHSSB = DAG.ComputeNumSignBits(Mul.getOperand(1));
> @@ -704,9 +704,9 @@ TryExpandADDWithMul(SDNode *N, Selection
> }
> SDValue LH, RH;
> LH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
> - Mul.getOperand(0), DAG.getConstant(1, MVT::i32));
> + Mul.getOperand(0), DAG.getConstant(1, dl, MVT::i32));
> RH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
> - Mul.getOperand(1), DAG.getConstant(1, MVT::i32));
> + Mul.getOperand(1), DAG.getConstant(1, dl, MVT::i32));
> SDValue Hi = DAG.getNode(XCoreISD::MACCU, dl,
> DAG.getVTList(MVT::i32, MVT::i32), AddendH,
> AddendL, LL, RL);
> @@ -735,18 +735,22 @@ ExpandADDSUB(SDNode *N, SelectionDAG &DA
>
> // Extract components
> SDValue LHSL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
> - N->getOperand(0), DAG.getConstant(0,
> MVT::i32));
> + N->getOperand(0),
> + DAG.getConstant(0, dl, MVT::i32));
> SDValue LHSH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
> - N->getOperand(0), DAG.getConstant(1,
> MVT::i32));
> + N->getOperand(0),
> + DAG.getConstant(1, dl, MVT::i32));
> SDValue RHSL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
> - N->getOperand(1), DAG.getConstant(0,
> MVT::i32));
> + N->getOperand(1),
> + DAG.getConstant(0, dl, MVT::i32));
> SDValue RHSH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
> - N->getOperand(1), DAG.getConstant(1,
> MVT::i32));
> + N->getOperand(1),
> + DAG.getConstant(1, dl, MVT::i32));
>
> // Expand
> unsigned Opcode = (N->getOpcode() == ISD::ADD) ? XCoreISD::LADD :
> XCoreISD::LSUB;
> - SDValue Zero = DAG.getConstant(0, MVT::i32);
> + SDValue Zero = DAG.getConstant(0, dl, MVT::i32);
> SDValue Lo = DAG.getNode(Opcode, dl, DAG.getVTList(MVT::i32, MVT::i32),
> LHSL, RHSL, Zero);
> SDValue Carry(Lo.getNode(), 1);
> @@ -775,7 +779,8 @@ LowerVAARG(SDValue Op, SelectionDAG &DAG
> false, false, false, 0);
> // Increment the pointer, VAList, to the next vararg
> SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAList,
> - DAG.getIntPtrConstant(VT.getSizeInBits()
> / 8));
> + DAG.getIntPtrConstant(VT.getSizeInBits()
> / 8,
> + dl));
> // Store the incremented VAList to the legalized pointer
> InChain = DAG.getStore(VAList.getValue(1), dl, nextPtr, VAListPtr,
> MachinePointerInfo(SV), false, false, 0);
> @@ -910,30 +915,30 @@ LowerINIT_TRAMPOLINE(SDValue Op, Selecti
> SDValue Addr = Trmp;
>
> SDLoc dl(Op);
> - OutChains[0] = DAG.getStore(Chain, dl, DAG.getConstant(0x0a3cd805,
> MVT::i32),
> - Addr, MachinePointerInfo(TrmpAddr), false,
> false,
> - 0);
> + OutChains[0] = DAG.getStore(Chain, dl,
> + DAG.getConstant(0x0a3cd805, dl, MVT::i32),
> Addr,
> + MachinePointerInfo(TrmpAddr), false, false,
> 0);
>
> Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
> - DAG.getConstant(4, MVT::i32));
> - OutChains[1] = DAG.getStore(Chain, dl, DAG.getConstant(0xd80456c0,
> MVT::i32),
> - Addr, MachinePointerInfo(TrmpAddr, 4),
> false,
> - false, 0);
> + DAG.getConstant(4, dl, MVT::i32));
> + OutChains[1] = DAG.getStore(Chain, dl,
> + DAG.getConstant(0xd80456c0, dl, MVT::i32),
> Addr,
> + MachinePointerInfo(TrmpAddr, 4), false,
> false, 0);
>
> Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
> - DAG.getConstant(8, MVT::i32));
> - OutChains[2] = DAG.getStore(Chain, dl, DAG.getConstant(0x27fb0a3c,
> MVT::i32),
> - Addr, MachinePointerInfo(TrmpAddr, 8),
> false,
> - false, 0);
> + DAG.getConstant(8, dl, MVT::i32));
> + OutChains[2] = DAG.getStore(Chain, dl,
> + DAG.getConstant(0x27fb0a3c, dl, MVT::i32),
> Addr,
> + MachinePointerInfo(TrmpAddr, 8), false,
> false, 0);
>
> Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
> - DAG.getConstant(12, MVT::i32));
> + DAG.getConstant(12, dl, MVT::i32));
> OutChains[3] = DAG.getStore(Chain, dl, Nest, Addr,
> MachinePointerInfo(TrmpAddr, 12), false,
> false,
> 0);
>
> Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
> - DAG.getConstant(16, MVT::i32));
> + DAG.getConstant(16, dl, MVT::i32));
> OutChains[4] = DAG.getStore(Chain, dl, FPtr, Addr,
> MachinePointerInfo(TrmpAddr, 16), false,
> false,
> 0);
> @@ -1096,7 +1101,7 @@ LowerCallResult(SDValue Chain, SDValue I
> int offset = ResultMemLocs[i].first;
> unsigned index = ResultMemLocs[i].second;
> SDVTList VTs = DAG.getVTList(MVT::i32, MVT::Other);
> - SDValue Ops[] = { Chain, DAG.getConstant(offset / 4, MVT::i32) };
> + SDValue Ops[] = { Chain, DAG.getConstant(offset / 4, dl, MVT::i32) };
> SDValue load = DAG.getNode(XCoreISD::LDWSP, dl, VTs, Ops);
> InVals[index] = load;
> MemOpChains.push_back(load.getValue(1));
> @@ -1145,7 +1150,7 @@ XCoreTargetLowering::LowerCCCCallTo(SDVa
> // Get a count of how many bytes are to be pushed on the stack.
> unsigned NumBytes = RetCCInfo.getNextStackOffset();
>
> - Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes,
> + Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes, dl,
> getPointerTy(), true), dl);
>
> SmallVector<std::pair<unsigned, SDValue>, 4> RegsToPass;
> @@ -1182,7 +1187,8 @@ XCoreTargetLowering::LowerCCCCallTo(SDVa
>
> MemOpChains.push_back(DAG.getNode(XCoreISD::STWSP, dl, MVT::Other,
> Chain, Arg,
> - DAG.getConstant(Offset/4,
> MVT::i32)));
> + DAG.getConstant(Offset/4, dl,
> + MVT::i32)));
> }
> }
>
> @@ -1233,8 +1239,9 @@ XCoreTargetLowering::LowerCCCCallTo(SDVa
>
> // Create the CALLSEQ_END node.
> Chain = DAG.getCALLSEQ_END(Chain,
> - DAG.getConstant(NumBytes, getPointerTy(),
> true),
> - DAG.getConstant(0, getPointerTy(), true),
> + DAG.getConstant(NumBytes, dl, getPointerTy(),
> + true),
> + DAG.getConstant(0, dl, getPointerTy(), true),
> InFlag, dl);
> InFlag = Chain.getValue(1);
>
> @@ -1422,7 +1429,7 @@ XCoreTargetLowering::LowerCCCArguments(S
> SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
> InVals.push_back(FIN);
> MemOps.push_back(DAG.getMemcpy(Chain, dl, FIN, ArgDI->SDV,
> - DAG.getConstant(Size, MVT::i32),
> + DAG.getConstant(Size, dl, MVT::i32),
> Align, false, false, false,
> MachinePointerInfo(),
> MachinePointerInfo()));
> @@ -1487,7 +1494,7 @@ XCoreTargetLowering::LowerReturn(SDValue
> SmallVector<SDValue, 4> RetOps(1, Chain);
>
> // Return on XCore is always a "retsp 0"
> - RetOps.push_back(DAG.getConstant(0, MVT::i32));
> + RetOps.push_back(DAG.getConstant(0, dl, MVT::i32));
>
> SmallVector<SDValue, 4> MemOpChains;
> // Handle return values that must be copied to memory.
> @@ -1671,9 +1678,9 @@ SDValue XCoreTargetLowering::PerformDAGC
>
> // fold (ladd 0, 0, x) -> 0, x & 1
> if (N0C && N0C->isNullValue() && N1C && N1C->isNullValue()) {
> - SDValue Carry = DAG.getConstant(0, VT);
> + SDValue Carry = DAG.getConstant(0, dl, VT);
> SDValue Result = DAG.getNode(ISD::AND, dl, VT, N2,
> - DAG.getConstant(1, VT));
> + DAG.getConstant(1, dl, VT));
> SDValue Ops[] = { Result, Carry };
> return DAG.getMergeValues(Ops, dl);
> }
> @@ -1686,7 +1693,7 @@ SDValue XCoreTargetLowering::PerformDAGC
> VT.getSizeInBits() - 1);
> DAG.computeKnownBits(N2, KnownZero, KnownOne);
> if ((KnownZero & Mask) == Mask) {
> - SDValue Carry = DAG.getConstant(0, VT);
> + SDValue Carry = DAG.getConstant(0, dl, VT);
> SDValue Result = DAG.getNode(ISD::ADD, dl, VT, N0, N2);
> SDValue Ops[] = { Result, Carry };
> return DAG.getMergeValues(Ops, dl);
> @@ -1711,7 +1718,7 @@ SDValue XCoreTargetLowering::PerformDAGC
> if ((KnownZero & Mask) == Mask) {
> SDValue Borrow = N2;
> SDValue Result = DAG.getNode(ISD::SUB, dl, VT,
> - DAG.getConstant(0, VT), N2);
> + DAG.getConstant(0, dl, VT), N2);
> SDValue Ops[] = { Result, Borrow };
> return DAG.getMergeValues(Ops, dl);
> }
> @@ -1725,7 +1732,7 @@ SDValue XCoreTargetLowering::PerformDAGC
> VT.getSizeInBits() - 1);
> DAG.computeKnownBits(N2, KnownZero, KnownOne);
> if ((KnownZero & Mask) == Mask) {
> - SDValue Borrow = DAG.getConstant(0, VT);
> + SDValue Borrow = DAG.getConstant(0, dl, VT);
> SDValue Result = DAG.getNode(ISD::SUB, dl, VT, N0, N2);
> SDValue Ops[] = { Result, Borrow };
> return DAG.getMergeValues(Ops, dl);
> @@ -1791,13 +1798,13 @@ SDValue XCoreTargetLowering::PerformDAGC
> DAG.MaskedValueIsZero(Addend0, HighMask) &&
> DAG.MaskedValueIsZero(Addend1, HighMask)) {
> SDValue Mul0L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
> - Mul0, DAG.getConstant(0, MVT::i32));
> + Mul0, DAG.getConstant(0, dl, MVT::i32));
> SDValue Mul1L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
> - Mul1, DAG.getConstant(0, MVT::i32));
> + Mul1, DAG.getConstant(0, dl, MVT::i32));
> SDValue Addend0L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
> - Addend0, DAG.getConstant(0,
> MVT::i32));
> + Addend0, DAG.getConstant(0, dl,
> MVT::i32));
> SDValue Addend1L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
> - Addend1, DAG.getConstant(0,
> MVT::i32));
> + Addend1, DAG.getConstant(0, dl,
> MVT::i32));
> SDValue Hi = DAG.getNode(XCoreISD::LMUL, dl,
> DAG.getVTList(MVT::i32, MVT::i32), Mul0L,
> Mul1L,
> Addend0L, Addend1L);
> @@ -1837,7 +1844,7 @@ SDValue XCoreTargetLowering::PerformDAGC
> bool isTail = isInTailCallPosition(DAG, ST, Chain);
> return DAG.getMemmove(Chain, dl, ST->getBasePtr(),
> LD->getBasePtr(),
> - DAG.getConstant(StoreBits/8, MVT::i32),
> + DAG.getConstant(StoreBits/8, dl, MVT::i32),
> Alignment, false, isTail,
> ST->getPointerInfo(),
> LD->getPointerInfo());
> }
>
> Modified: llvm/trunk/lib/Target/XCore/XCoreInstrInfo.td
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreInstrInfo.td?rev=235977&r1=235976&r2=235977&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/XCore/XCoreInstrInfo.td (original)
> +++ llvm/trunk/lib/Target/XCore/XCoreInstrInfo.td Tue Apr 28 06:56:37 2015
> @@ -94,33 +94,34 @@ def XCoreMemBarrier : SDNode<"XCoreISD::
> def div4_xform : SDNodeXForm<imm, [{
> // Transformation function: imm/4
> assert(N->getZExtValue() % 4 == 0);
> - return getI32Imm(N->getZExtValue()/4);
> + return getI32Imm(N->getZExtValue()/4, SDLoc(N));
> }]>;
>
> def msksize_xform : SDNodeXForm<imm, [{
> // Transformation function: get the size of a mask
> assert(isMask_32(N->getZExtValue()));
> // look for the first non-zero bit
> - return getI32Imm(32 - countLeadingZeros((uint32_t)N->getZExtValue()));
> + return getI32Imm(32 - countLeadingZeros((uint32_t)N->getZExtValue()),
> + SDLoc(N));
> }]>;
>
> def neg_xform : SDNodeXForm<imm, [{
> // Transformation function: -imm
> uint32_t value = N->getZExtValue();
> - return getI32Imm(-value);
> + return getI32Imm(-value, SDLoc(N));
> }]>;
>
> def bpwsub_xform : SDNodeXForm<imm, [{
> // Transformation function: 32-imm
> uint32_t value = N->getZExtValue();
> - return getI32Imm(32-value);
> + return getI32Imm(32 - value, SDLoc(N));
> }]>;
>
> def div4neg_xform : SDNodeXForm<imm, [{
> // Transformation function: -imm/4
> uint32_t value = N->getZExtValue();
> assert(-value % 4 == 0);
> - return getI32Imm(-value/4);
> + return getI32Imm(-value/4, SDLoc(N));
> }]>;
>
> def immUs4Neg : PatLeaf<(imm), [{
>
> Added: llvm/trunk/test/DebugInfo/AArch64/constant-dbgloc.ll
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/AArch64/constant-dbgloc.ll?rev=235977&view=auto
>
> ==============================================================================
> --- llvm/trunk/test/DebugInfo/AArch64/constant-dbgloc.ll (added)
> +++ llvm/trunk/test/DebugInfo/AArch64/constant-dbgloc.ll Tue Apr 28
> 06:56:37 2015
> @@ -0,0 +1,37 @@
> +; RUN: llc -filetype=asm %s -o - | FileCheck %s
> +
> +target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
> +target triple = "aarch64--linux-gnueabihf"
> +
> +; int
> +; main(void)
> +; {
> +; return -1;
> +; }
> +
> +; CHECK: test.c:4:5
> +; CHECK: movn
> +
> +; Function Attrs: nounwind
> +define i32 @main() {
> +entry:
> + %retval = alloca i32, align 4
> + store i32 0, i32* %retval
> + ret i32 -1, !dbg !11
> +}
> +
> +!llvm.dbg.cu = !{!0}
> +!llvm.module.flags = !{!8, !9}
> +
> +!0 = !MDCompileUnit(language: DW_LANG_C99, file: !1, producer: "",
> isOptimized: false, subprograms: !3)
> +!1 = !MDFile(filename: "test.c", directory: "/home/user/clang/build")
> +!2 = !{}
> +!3 = !{!4}
> +!4 = !MDSubprogram(name: "main", scope: !1, file: !1, line: 2, type: !5,
> isLocal: false, isDefinition: true, scopeLine: 3, flags: DIFlagPrototyped,
> isOptimized: false, function: i32 ()* @main, variables: !2)
> +!5 = !MDSubroutineType(types: !6)
> +!6 = !{!7}
> +!7 = !MDBasicType(name: "int", size: 32, align: 32, encoding:
> DW_ATE_signed)
> +!8 = !{i32 2, !"Dwarf Version", i32 4}
> +!9 = !{i32 2, !"Debug Info Version", i32 3}
> +!10 = !{i32 1, !"wchar_size", i32 4}
> +!11 = !MDLocation(line: 4, column: 5, scope: !4)
>
> Added: llvm/trunk/test/DebugInfo/ARM/constant-dbgloc.ll
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/ARM/constant-dbgloc.ll?rev=235977&view=auto
>
> ==============================================================================
> --- llvm/trunk/test/DebugInfo/ARM/constant-dbgloc.ll (added)
> +++ llvm/trunk/test/DebugInfo/ARM/constant-dbgloc.ll Tue Apr 28 06:56:37
> 2015
> @@ -0,0 +1,37 @@
> +; RUN: llc -filetype=asm %s -o - | FileCheck %s
> +
> +target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
> +target triple = "armv7--linux-gnueabihf"
> +
> +; int
> +; main(void)
> +; {
> +; return -1;
> +; }
> +
> +; CHECK: test.c:4:5
> +; CHECK: mvn
> +
> +; Function Attrs: nounwind
> +define i32 @main() {
> +entry:
> + %retval = alloca i32, align 4
> + store i32 0, i32* %retval
> + ret i32 -1, !dbg !11
> +}
> +
> +!llvm.dbg.cu = !{!0}
> +!llvm.module.flags = !{!8, !9}
> +
> +!0 = !MDCompileUnit(language: DW_LANG_C99, file: !1, producer: "",
> isOptimized: false, subprograms: !3)
> +!1 = !MDFile(filename: "test.c", directory: "/home/user/clang/build")
> +!2 = !{}
> +!3 = !{!4}
> +!4 = !MDSubprogram(name: "main", scope: !1, file: !1, line: 2, type: !5,
> isLocal: false, isDefinition: true, scopeLine: 3, flags: DIFlagPrototyped,
> isOptimized: false, function: i32 ()* @main, variables: !2)
> +!5 = !MDSubroutineType(types: !6)
> +!6 = !{!7}
> +!7 = !MDBasicType(name: "int", size: 32, align: 32, encoding:
> DW_ATE_signed)
> +!8 = !{i32 2, !"Dwarf Version", i32 4}
> +!9 = !{i32 2, !"Debug Info Version", i32 3}
> +!10 = !{i32 1, !"wchar_size", i32 4}
> +!11 = !MDLocation(line: 4, column: 5, scope: !4)
>
> Added: llvm/trunk/test/DebugInfo/constant-sdnodes-have-dbg-location.ll
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/constant-sdnodes-have-dbg-location.ll?rev=235977&view=auto
>
> ==============================================================================
> --- llvm/trunk/test/DebugInfo/constant-sdnodes-have-dbg-location.ll (added)
> +++ llvm/trunk/test/DebugInfo/constant-sdnodes-have-dbg-location.ll Tue
> Apr 28 06:56:37 2015
> @@ -0,0 +1,25 @@
> +; RUN: llc -debug < %s 2>&1 | FileCheck %s
> +
> +; CHECK: 0x{{[0-9,a-f]+}}: i32 = Constant<-1>test.c:4:5
> +
> +define i32 @main() {
> +entry:
> + %retval = alloca i32, align 4
> + store i32 0, i32* %retval
> + ret i32 -1, !dbg !10
> +}
> +
> +!llvm.dbg.cu = !{!0}
> +!llvm.module.flags = !{!8, !9}
> +
> +!0 = !MDCompileUnit(language: DW_LANG_C99, file: !1, producer: "",
> isOptimized: false, subprograms: !3)
> +!1 = !MDFile(filename: "test.c", directory: "/home/user/clang-llvm/build")
> +!2 = !{}
> +!3 = !{!4}
> +!4 = !MDSubprogram(name: "main", scope: !1, file: !1, line: 2, type: !5,
> isLocal: false, isDefinition: true, scopeLine: 3, flags: DIFlagPrototyped,
> isOptimized: false, function: i32 ()* @main, variables: !2)
> +!5 = !MDSubroutineType(types: !6)
> +!6 = !{!7}
> +!7 = !MDBasicType(name: "int", size: 32, align: 32, encoding:
> DW_ATE_signed)
> +!8 = !{i32 2, !"Dwarf Version", i32 4}
> +!9 = !{i32 2, !"Debug Info Version", i32 3}
> +!10 = !MDLocation(line: 4, column: 5, scope: !4)
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>
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