[PATCH] [AArch64] Add v8.1a atomic instructions

[Tim Northover]

Looks mostly reasonable. Just a few minor comments now.

Tim.


REPOSITORY
  rL LLVM

================
Comment at: lib/Target/AArch64/AArch64RegisterInfo.td:608-609
@@ +607,4 @@
+
+def WSeqPairsClass   : RegisterClass<"AArch64", [untyped], 32, (add WSeqPairs)> {let Size = 64;}
+def XSeqPairsClass   : RegisterClass<"AArch64", [untyped], 64, (add XSeqPairs)> {let Size = 128;}
+
----------------
These lines are longer than the column limit. Not sure about the surrounding ones.

================
Comment at: lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp:4322
@@ +4321,3 @@
+  }
+  printf ("FirstReg=%d\n",FirstReg);
+
----------------
Debugging code should be removed.

================
Comment at: lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp:4332
@@ +4331,3 @@
+  if (!isXReg && !isWReg) {
+    Error(S, "expected register");
+    return MatchOperand_ParseFail;
----------------
Since this only ever called for an instruction that *must* have a pair, we can be more helpful in the error messages produced. Always say that we need an even/odd register pair, for example.

http://reviews.llvm.org/D8501

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