[PATCH] [PPC64] Add vector quadword add/sub instructions for POWER8

[Kit Barton]

Hi hfinkel, wschmidt, seurer, nemanjai,

This patch adds support for the vector quadword add/sub instructions introduced in POWER8.

In addition to adding the instructions themselves, it makes the following changes:
  - Add support for the v1i128 type for intrinsics (Intrinsics.td, Function.cpp, and IntrinsicEmitter.cpp)
  - Add the v1i128 type to the VMX Register class
  - Add support for v1i128 to the PPC Calling conventions (also added v2i64 because it was missing)

http://reviews.llvm.org/D9081

Files:
  include/llvm/IR/Intrinsics.td
  include/llvm/IR/IntrinsicsPowerPC.td
  lib/IR/Function.cpp
  lib/Target/PowerPC/PPCCallingConv.td
  lib/Target/PowerPC/PPCISelLowering.cpp
  lib/Target/PowerPC/PPCInstrAltivec.td
  lib/Target/PowerPC/PPCInstrVSX.td
  lib/Target/PowerPC/PPCRegisterInfo.td
  test/CodeGen/PowerPC/vec_add_sub_quadword.ll
  test/MC/Disassembler/PowerPC/ppc64-encoding-vmx.txt
  test/MC/PowerPC/ppc64-encoding-vmx.s
  utils/TableGen/IntrinsicEmitter.cpp

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