[llvm] r235107 - [AArch64] Add v8.1a "Virtualization Host Extensions"
Vladimir Sukharev
vladimir.sukharev at arm.com
Thu Apr 16 08:38:58 PDT 2015
Author: vsukharev
Date: Thu Apr 16 10:38:58 2015
New Revision: 235107
URL: http://llvm.org/viewvc/llvm-project?rev=235107&view=rev
Log:
[AArch64] Add v8.1a "Virtualization Host Extensions"
Reviewers: t.p.northover
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D8500
Patch by: Tom Coxon
Added:
llvm/trunk/test/MC/AArch64/armv8.1a-vhe.s (with props)
llvm/trunk/test/MC/Disassembler/AArch64/armv8.1a-vhe.txt (with props)
Modified:
llvm/trunk/lib/Target/AArch64/Utils/AArch64BaseInfo.cpp
llvm/trunk/lib/Target/AArch64/Utils/AArch64BaseInfo.h
Modified: llvm/trunk/lib/Target/AArch64/Utils/AArch64BaseInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/Utils/AArch64BaseInfo.cpp?rev=235107&r1=235106&r2=235107&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/Utils/AArch64BaseInfo.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/Utils/AArch64BaseInfo.cpp Thu Apr 16 10:38:58 2015
@@ -771,7 +771,36 @@ const AArch64NamedImmMapper::Mapping AAr
{"lorea_el1", LOREA_EL1, AArch64::HasV8_1aOps},
{"lorn_el1", LORN_EL1, AArch64::HasV8_1aOps},
{"lorc_el1", LORC_EL1, AArch64::HasV8_1aOps},
- {"lorid_el1", LORID_EL1, AArch64::HasV8_1aOps},
+ {"lorid_el1", LORID_EL1, AArch64::HasV8_1aOps},
+
+ // v8.1a "Virtualization host extensions" system registers
+ {"ttbr1_el2", TTBR1_EL2, AArch64::HasV8_1aOps},
+ {"contextidr_el2", CONTEXTIDR_EL2, AArch64::HasV8_1aOps},
+ {"cnthv_tval_el2", CNTHV_TVAL_EL2, AArch64::HasV8_1aOps},
+ {"cnthv_cval_el2", CNTHV_CVAL_EL2, AArch64::HasV8_1aOps},
+ {"cnthv_ctl_el2", CNTHV_CTL_EL2, AArch64::HasV8_1aOps},
+ {"sctlr_el12", SCTLR_EL12, AArch64::HasV8_1aOps},
+ {"cpacr_el12", CPACR_EL12, AArch64::HasV8_1aOps},
+ {"ttbr0_el12", TTBR0_EL12, AArch64::HasV8_1aOps},
+ {"ttbr1_el12", TTBR1_EL12, AArch64::HasV8_1aOps},
+ {"tcr_el12", TCR_EL12, AArch64::HasV8_1aOps},
+ {"afsr0_el12", AFSR0_EL12, AArch64::HasV8_1aOps},
+ {"afsr1_el12", AFSR1_EL12, AArch64::HasV8_1aOps},
+ {"esr_el12", ESR_EL12, AArch64::HasV8_1aOps},
+ {"far_el12", FAR_EL12, AArch64::HasV8_1aOps},
+ {"mair_el12", MAIR_EL12, AArch64::HasV8_1aOps},
+ {"amair_el12", AMAIR_EL12, AArch64::HasV8_1aOps},
+ {"vbar_el12", VBAR_EL12, AArch64::HasV8_1aOps},
+ {"contextidr_el12", CONTEXTIDR_EL12, AArch64::HasV8_1aOps},
+ {"cntkctl_el12", CNTKCTL_EL12, AArch64::HasV8_1aOps},
+ {"cntp_tval_el02", CNTP_TVAL_EL02, AArch64::HasV8_1aOps},
+ {"cntp_ctl_el02", CNTP_CTL_EL02, AArch64::HasV8_1aOps},
+ {"cntp_cval_el02", CNTP_CVAL_EL02, AArch64::HasV8_1aOps},
+ {"cntv_tval_el02", CNTV_TVAL_EL02, AArch64::HasV8_1aOps},
+ {"cntv_ctl_el02", CNTV_CTL_EL02, AArch64::HasV8_1aOps},
+ {"cntv_cval_el02", CNTV_CVAL_EL02, AArch64::HasV8_1aOps},
+ {"spsr_el12", SPSR_EL12, AArch64::HasV8_1aOps},
+ {"elr_el12", ELR_EL12, AArch64::HasV8_1aOps},
};
uint32_t
Modified: llvm/trunk/lib/Target/AArch64/Utils/AArch64BaseInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/Utils/AArch64BaseInfo.h?rev=235107&r1=235106&r2=235107&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/Utils/AArch64BaseInfo.h (original)
+++ llvm/trunk/lib/Target/AArch64/Utils/AArch64BaseInfo.h Thu Apr 16 10:38:58 2015
@@ -1148,6 +1148,35 @@ namespace AArch64SysReg {
LORC_EL1 = 0xc523, // 11 000 1010 0100 011
LORID_EL1 = 0xc527, // 11 000 1010 0100 111
+ // v8.1a "Virtualization host extensions" system registers
+ TTBR1_EL2 = 0xe101, // 11 100 0010 0000 001
+ CONTEXTIDR_EL2 = 0xe681, // 11 100 1101 0000 001
+ CNTHV_TVAL_EL2 = 0xe718, // 11 100 1110 0011 000
+ CNTHV_CVAL_EL2 = 0xe71a, // 11 100 1110 0011 010
+ CNTHV_CTL_EL2 = 0xe719, // 11 100 1110 0011 001
+ SCTLR_EL12 = 0xe880, // 11 101 0001 0000 000
+ CPACR_EL12 = 0xe882, // 11 101 0001 0000 010
+ TTBR0_EL12 = 0xe900, // 11 101 0010 0000 000
+ TTBR1_EL12 = 0xe901, // 11 101 0010 0000 001
+ TCR_EL12 = 0xe902, // 11 101 0010 0000 010
+ AFSR0_EL12 = 0xea88, // 11 101 0101 0001 000
+ AFSR1_EL12 = 0xea89, // 11 101 0101 0001 001
+ ESR_EL12 = 0xea90, // 11 101 0101 0010 000
+ FAR_EL12 = 0xeb00, // 11 101 0110 0000 000
+ MAIR_EL12 = 0xed10, // 11 101 1010 0010 000
+ AMAIR_EL12 = 0xed18, // 11 101 1010 0011 000
+ VBAR_EL12 = 0xee00, // 11 101 1100 0000 000
+ CONTEXTIDR_EL12 = 0xee81, // 11 101 1101 0000 001
+ CNTKCTL_EL12 = 0xef08, // 11 101 1110 0001 000
+ CNTP_TVAL_EL02 = 0xef10, // 11 101 1110 0010 000
+ CNTP_CTL_EL02 = 0xef11, // 11 101 1110 0010 001
+ CNTP_CVAL_EL02 = 0xef12, // 11 101 1110 0010 010
+ CNTV_TVAL_EL02 = 0xef18, // 11 101 1110 0011 000
+ CNTV_CTL_EL02 = 0xef19, // 11 101 1110 0011 001
+ CNTV_CVAL_EL02 = 0xef1a, // 11 101 1110 0011 010
+ SPSR_EL12 = 0xea00, // 11 101 0100 0000 000
+ ELR_EL12 = 0xea01, // 11 101 0100 0000 001
+
// Cyclone specific system registers
CPM_IOACC_CTL_EL3 = 0xff90,
};
Added: llvm/trunk/test/MC/AArch64/armv8.1a-vhe.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/armv8.1a-vhe.s?rev=235107&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/armv8.1a-vhe.s (added)
+++ llvm/trunk/test/MC/AArch64/armv8.1a-vhe.s Thu Apr 16 10:38:58 2015
@@ -0,0 +1,61 @@
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.1a < %s | FileCheck %s
+
+
+//------------------------------------------------------------------------------
+// Virtualization Host Extensions
+//------------------------------------------------------------------------------
+ msr TTBR1_EL2, x0
+ msr CONTEXTIDR_EL2, x0
+ msr CNTHV_TVAL_EL2, x0
+ msr CNTHV_CVAL_EL2, x0
+ msr CNTHV_CTL_EL2, x0
+ msr SCTLR_EL12, x0
+ msr CPACR_EL12, x0
+ msr TTBR0_EL12, x0
+ msr TTBR1_EL12, x0
+ msr TCR_EL12, x0
+ msr AFSR0_EL12, x0
+ msr AFSR1_EL12, x0
+ msr ESR_EL12, x0
+ msr FAR_EL12, x0
+ msr MAIR_EL12, x0
+ msr AMAIR_EL12, x0
+ msr VBAR_EL12, x0
+ msr CONTEXTIDR_EL12, x0
+ msr CNTKCTL_EL12, x0
+ msr CNTP_TVAL_EL02, x0
+ msr CNTP_CTL_EL02, x0
+ msr CNTP_CVAL_EL02, x0
+ msr CNTV_TVAL_EL02, x0
+ msr CNTV_CTL_EL02, x0
+ msr CNTV_CVAL_EL02, x0
+ msr SPSR_EL12, x0
+ msr ELR_EL12, x0
+
+// CHECK: msr TTBR1_EL2, x0 // encoding: [0x20,0x20,0x1c,0xd5]
+// CHECK: msr CONTEXTIDR_EL2, x0 // encoding: [0x20,0xd0,0x1c,0xd5]
+// CHECK: msr CNTHV_TVAL_EL2, x0 // encoding: [0x00,0xe3,0x1c,0xd5]
+// CHECK: msr CNTHV_CVAL_EL2, x0 // encoding: [0x40,0xe3,0x1c,0xd5]
+// CHECK: msr CNTHV_CTL_EL2, x0 // encoding: [0x20,0xe3,0x1c,0xd5]
+// CHECK: msr SCTLR_EL12, x0 // encoding: [0x00,0x10,0x1d,0xd5]
+// CHECK: msr CPACR_EL12, x0 // encoding: [0x40,0x10,0x1d,0xd5]
+// CHECK: msr TTBR0_EL12, x0 // encoding: [0x00,0x20,0x1d,0xd5]
+// CHECK: msr TTBR1_EL12, x0 // encoding: [0x20,0x20,0x1d,0xd5]
+// CHECK: msr TCR_EL12, x0 // encoding: [0x40,0x20,0x1d,0xd5]
+// CHECK: msr AFSR0_EL12, x0 // encoding: [0x00,0x51,0x1d,0xd5]
+// CHECK: msr AFSR1_EL12, x0 // encoding: [0x20,0x51,0x1d,0xd5]
+// CHECK: msr ESR_EL12, x0 // encoding: [0x00,0x52,0x1d,0xd5]
+// CHECK: msr FAR_EL12, x0 // encoding: [0x00,0x60,0x1d,0xd5]
+// CHECK: msr MAIR_EL12, x0 // encoding: [0x00,0xa2,0x1d,0xd5]
+// CHECK: msr AMAIR_EL12, x0 // encoding: [0x00,0xa3,0x1d,0xd5]
+// CHECK: msr VBAR_EL12, x0 // encoding: [0x00,0xc0,0x1d,0xd5]
+// CHECK: msr CONTEXTIDR_EL12, x0 // encoding: [0x20,0xd0,0x1d,0xd5]
+// CHECK: msr CNTKCTL_EL12, x0 // encoding: [0x00,0xe1,0x1d,0xd5]
+// CHECK: msr CNTP_TVAL_EL02, x0 // encoding: [0x00,0xe2,0x1d,0xd5]
+// CHECK: msr CNTP_CTL_EL02, x0 // encoding: [0x20,0xe2,0x1d,0xd5]
+// CHECK: msr CNTP_CVAL_EL02, x0 // encoding: [0x40,0xe2,0x1d,0xd5]
+// CHECK: msr CNTV_TVAL_EL02, x0 // encoding: [0x00,0xe3,0x1d,0xd5]
+// CHECK: msr CNTV_CTL_EL02, x0 // encoding: [0x20,0xe3,0x1d,0xd5]
+// CHECK: msr CNTV_CVAL_EL02, x0 // encoding: [0x40,0xe3,0x1d,0xd5]
+// CHECK: msr SPSR_EL12, x0 // encoding: [0x00,0x40,0x1d,0xd5]
+// CHECK: msr ELR_EL12, x0 // encoding: [0x20,0x40,0x1d,0xd5]
Propchange: llvm/trunk/test/MC/AArch64/armv8.1a-vhe.s
------------------------------------------------------------------------------
svn:eol-style = native
Propchange: llvm/trunk/test/MC/AArch64/armv8.1a-vhe.s
------------------------------------------------------------------------------
svn:keywords = Rev Date Author URL Id
Added: llvm/trunk/test/MC/Disassembler/AArch64/armv8.1a-vhe.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/AArch64/armv8.1a-vhe.txt?rev=235107&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/AArch64/armv8.1a-vhe.txt (added)
+++ llvm/trunk/test/MC/Disassembler/AArch64/armv8.1a-vhe.txt Thu Apr 16 10:38:58 2015
@@ -0,0 +1,56 @@
+# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.1a --disassemble < %s | FileCheck %s
+
+0x20,0x20,0x1c,0xd5
+0x20,0xd0,0x1c,0xd5
+0x00,0xe3,0x1c,0xd5
+0x40,0xe3,0x1c,0xd5
+0x20,0xe3,0x1c,0xd5
+0x00,0x10,0x1d,0xd5
+0x40,0x10,0x1d,0xd5
+0x00,0x20,0x1d,0xd5
+0x20,0x20,0x1d,0xd5
+0x40,0x20,0x1d,0xd5
+0x00,0x51,0x1d,0xd5
+0x20,0x51,0x1d,0xd5
+0x00,0x52,0x1d,0xd5
+0x00,0x60,0x1d,0xd5
+0x00,0xa2,0x1d,0xd5
+0x00,0xa3,0x1d,0xd5
+0x00,0xc0,0x1d,0xd5
+0x20,0xd0,0x1d,0xd5
+0x00,0xe1,0x1d,0xd5
+0x00,0xe2,0x1d,0xd5
+0x20,0xe2,0x1d,0xd5
+0x40,0xe2,0x1d,0xd5
+0x00,0xe3,0x1d,0xd5
+0x20,0xe3,0x1d,0xd5
+0x40,0xe3,0x1d,0xd5
+0x00,0x40,0x1d,0xd5
+0x20,0x40,0x1d,0xd5
+# CHECK: msr TTBR1_EL2, x0
+# CHECK: msr CONTEXTIDR_EL2, x0
+# CHECK: msr CNTHV_TVAL_EL2, x0
+# CHECK: msr CNTHV_CVAL_EL2, x0
+# CHECK: msr CNTHV_CTL_EL2, x0
+# CHECK: msr SCTLR_EL12, x0
+# CHECK: msr CPACR_EL12, x0
+# CHECK: msr TTBR0_EL12, x0
+# CHECK: msr TTBR1_EL12, x0
+# CHECK: msr TCR_EL12, x0
+# CHECK: msr AFSR0_EL12, x0
+# CHECK: msr AFSR1_EL12, x0
+# CHECK: msr ESR_EL12, x0
+# CHECK: msr FAR_EL12, x0
+# CHECK: msr MAIR_EL12, x0
+# CHECK: msr AMAIR_EL12, x0
+# CHECK: msr VBAR_EL12, x0
+# CHECK: msr CONTEXTIDR_EL12, x0
+# CHECK: msr CNTKCTL_EL12, x0
+# CHECK: msr CNTP_TVAL_EL02, x0
+# CHECK: msr CNTP_CTL_EL02, x0
+# CHECK: msr CNTP_CVAL_EL02, x0
+# CHECK: msr CNTV_TVAL_EL02, x0
+# CHECK: msr CNTV_CTL_EL02, x0
+# CHECK: msr CNTV_CVAL_EL02, x0
+# CHECK: msr SPSR_EL12, x0
+# CHECK: msr ELR_EL12, x0
Propchange: llvm/trunk/test/MC/Disassembler/AArch64/armv8.1a-vhe.txt
------------------------------------------------------------------------------
svn:eol-style = native
Propchange: llvm/trunk/test/MC/Disassembler/AArch64/armv8.1a-vhe.txt
------------------------------------------------------------------------------
svn:keywords = Rev Date Author URL Id
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