[llvm] r235105 - [AArch64] Add v8.1a "Limited Ordering Regions" extension
Vladimir Sukharev
vladimir.sukharev at arm.com
Thu Apr 16 08:30:43 PDT 2015
Author: vsukharev
Date: Thu Apr 16 10:30:43 2015
New Revision: 235105
URL: http://llvm.org/viewvc/llvm-project?rev=235105&view=rev
Log:
[AArch64] Add v8.1a "Limited Ordering Regions" extension
Reviewers: t.p.northover
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D8499
Patch by: Tom Coxon
Added:
llvm/trunk/test/MC/AArch64/armv8.1a-lor.s (with props)
llvm/trunk/test/MC/Disassembler/AArch64/armv8.1a-lor.txt (with props)
Modified:
llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td
llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td
llvm/trunk/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
llvm/trunk/lib/Target/AArch64/Utils/AArch64BaseInfo.cpp
llvm/trunk/lib/Target/AArch64/Utils/AArch64BaseInfo.h
Modified: llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td?rev=235105&r1=235104&r2=235105&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td Thu Apr 16 10:30:43 2015
@@ -3288,6 +3288,10 @@ class LoadStoreExclusiveSimple<bits<2> s
: BaseLoadStoreExclusive<sz, o2, L, o1, o0, oops, iops, asm, operands> {
bits<5> Rt;
bits<5> Rn;
+ let Inst{20-16} = 0b11111;
+ let Unpredictable{20-16} = 0b11111;
+ let Inst{14-10} = 0b11111;
+ let Unpredictable{14-10} = 0b11111;
let Inst{9-5} = Rn;
let Inst{4-0} = Rt;
Modified: llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td?rev=235105&r1=235104&r2=235105&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td Thu Apr 16 10:30:43 2015
@@ -2314,6 +2314,20 @@ def STLXPX : StoreExclusivePair<0b11, 0,
def STXPW : StoreExclusivePair<0b10, 0, 0, 1, 0, GPR32, "stxp">;
def STXPX : StoreExclusivePair<0b11, 0, 0, 1, 0, GPR64, "stxp">;
+let Predicates = [HasV8_1a] in {
+ // v8.1a "Limited Order Region" extension load-acquire instructions
+ def LDLARW : LoadAcquire <0b10, 1, 1, 0, 0, GPR32, "ldlar">;
+ def LDLARX : LoadAcquire <0b11, 1, 1, 0, 0, GPR64, "ldlar">;
+ def LDLARB : LoadAcquire <0b00, 1, 1, 0, 0, GPR32, "ldlarb">;
+ def LDLARH : LoadAcquire <0b01, 1, 1, 0, 0, GPR32, "ldlarh">;
+
+ // v8.1a "Limited Order Region" extension store-release instructions
+ def STLLRW : StoreRelease <0b10, 1, 0, 0, 0, GPR32, "stllr">;
+ def STLLRX : StoreRelease <0b11, 1, 0, 0, 0, GPR64, "stllr">;
+ def STLLRB : StoreRelease <0b00, 1, 0, 0, 0, GPR32, "stllrb">;
+ def STLLRH : StoreRelease <0b01, 1, 0, 0, 0, GPR32, "stllrh">;
+}
+
//===----------------------------------------------------------------------===//
// Scaled floating point to integer conversion instructions.
//===----------------------------------------------------------------------===//
Modified: llvm/trunk/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp?rev=235105&r1=235104&r2=235105&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp Thu Apr 16 10:30:43 2015
@@ -1102,6 +1102,12 @@ static DecodeStatus DecodeExclusiveLdStI
case AArch64::STLRW:
case AArch64::STLRB:
case AArch64::STLRH:
+ case AArch64::STLLRW:
+ case AArch64::STLLRB:
+ case AArch64::STLLRH:
+ case AArch64::LDLARW:
+ case AArch64::LDLARB:
+ case AArch64::LDLARH:
DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
break;
case AArch64::STLXRX:
@@ -1112,6 +1118,8 @@ static DecodeStatus DecodeExclusiveLdStI
case AArch64::LDAXRX:
case AArch64::LDXRX:
case AArch64::STLRX:
+ case AArch64::LDLARX:
+ case AArch64::STLLRX:
DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
break;
case AArch64::STLXPW:
Modified: llvm/trunk/lib/Target/AArch64/Utils/AArch64BaseInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/Utils/AArch64BaseInfo.cpp?rev=235105&r1=235104&r2=235105&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/Utils/AArch64BaseInfo.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/Utils/AArch64BaseInfo.cpp Thu Apr 16 10:30:43 2015
@@ -765,6 +765,13 @@ const AArch64NamedImmMapper::Mapping AAr
// v8.1a "Privileged Access Never" extension-specific system registers
{"pan", PAN, AArch64::HasV8_1aOps},
+
+ // v8.1a "Limited Ordering Regions" extension-specific system registers
+ {"lorsa_el1", LORSA_EL1, AArch64::HasV8_1aOps},
+ {"lorea_el1", LOREA_EL1, AArch64::HasV8_1aOps},
+ {"lorn_el1", LORN_EL1, AArch64::HasV8_1aOps},
+ {"lorc_el1", LORC_EL1, AArch64::HasV8_1aOps},
+ {"lorid_el1", LORID_EL1, AArch64::HasV8_1aOps},
};
uint32_t
Modified: llvm/trunk/lib/Target/AArch64/Utils/AArch64BaseInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/Utils/AArch64BaseInfo.h?rev=235105&r1=235104&r2=235105&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/Utils/AArch64BaseInfo.h (original)
+++ llvm/trunk/lib/Target/AArch64/Utils/AArch64BaseInfo.h Thu Apr 16 10:30:43 2015
@@ -1141,6 +1141,13 @@ namespace AArch64SysReg {
// v8.1a "Privileged Access Never" extension-specific system registers
PAN = 0xc213, // 11 000 0100 0010 011
+ // v8.1a "Limited Ordering Regions" extension-specific system registers
+ LORSA_EL1 = 0xc520, // 11 000 1010 0100 000
+ LOREA_EL1 = 0xc521, // 11 000 1010 0100 001
+ LORN_EL1 = 0xc522, // 11 000 1010 0100 010
+ LORC_EL1 = 0xc523, // 11 000 1010 0100 011
+ LORID_EL1 = 0xc527, // 11 000 1010 0100 111
+
// Cyclone specific system registers
CPM_IOACC_CTL_EL3 = 0xff90,
};
Added: llvm/trunk/test/MC/AArch64/armv8.1a-lor.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/armv8.1a-lor.s?rev=235105&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/armv8.1a-lor.s (added)
+++ llvm/trunk/test/MC/AArch64/armv8.1a-lor.s Thu Apr 16 10:30:43 2015
@@ -0,0 +1,33 @@
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.1a < %s | FileCheck %s
+
+
+//------------------------------------------------------------------------------
+// Load acquire / store release
+//------------------------------------------------------------------------------
+ ldlarb w0,[x1]
+ ldlarh w0,[x1]
+ ldlar w0,[x1]
+ ldlar x0,[x1]
+// CHECK: ldlarb w0, [x1] // encoding: [0x20,0x7c,0xdf,0x08]
+// CHECK: ldlarh w0, [x1] // encoding: [0x20,0x7c,0xdf,0x48]
+// CHECK: ldlar w0, [x1] // encoding: [0x20,0x7c,0xdf,0x88]
+// CHECK: ldlar x0, [x1] // encoding: [0x20,0x7c,0xdf,0xc8]
+ stllrb w0,[x1]
+ stllrh w0,[x1]
+ stllr w0,[x1]
+ stllr x0,[x1]
+// CHECK: stllrb w0, [x1] // encoding: [0x20,0x7c,0x9f,0x08]
+// CHECK: stllrh w0, [x1] // encoding: [0x20,0x7c,0x9f,0x48]
+// CHECK: stllr w0, [x1] // encoding: [0x20,0x7c,0x9f,0x88]
+// CHECK: stllr x0, [x1] // encoding: [0x20,0x7c,0x9f,0xc8]
+
+ msr LORSA_EL1, x0
+ msr LOREA_EL1, x0
+ msr LORN_EL1, x0
+ msr LORC_EL1, x0
+ mrs x0, LORID_EL1
+// CHECK: msr LORSA_EL1, x0 // encoding: [0x00,0xa4,0x18,0xd5]
+// CHECK: msr LOREA_EL1, x0 // encoding: [0x20,0xa4,0x18,0xd5]
+// CHECK: msr LORN_EL1, x0 // encoding: [0x40,0xa4,0x18,0xd5]
+// CHECK: msr LORC_EL1, x0 // encoding: [0x60,0xa4,0x18,0xd5]
+// CHECK: mrs x0, LORID_EL1 // encoding: [0xe0,0xa4,0x38,0xd5]
Propchange: llvm/trunk/test/MC/AArch64/armv8.1a-lor.s
------------------------------------------------------------------------------
svn:eol-style = native
Propchange: llvm/trunk/test/MC/AArch64/armv8.1a-lor.s
------------------------------------------------------------------------------
svn:keywords = Rev Date Author URL Id
Added: llvm/trunk/test/MC/Disassembler/AArch64/armv8.1a-lor.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/AArch64/armv8.1a-lor.txt?rev=235105&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/AArch64/armv8.1a-lor.txt (added)
+++ llvm/trunk/test/MC/Disassembler/AArch64/armv8.1a-lor.txt Thu Apr 16 10:30:43 2015
@@ -0,0 +1,28 @@
+# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.1a --disassemble < %s | FileCheck %s
+
+0x20,0x7c,0xdf,0x08
+0x20,0x7c,0xdf,0x48
+0x20,0x7c,0xdf,0x88
+0x20,0x7c,0xdf,0xc8
+0x20,0x7c,0x9f,0x08
+0x20,0x7c,0x9f,0x48
+0x20,0x7c,0x9f,0x88
+0x20,0x7c,0x9f,0xc8
+# CHECK: ldlarb w0, [x1]
+# CHECK: ldlarh w0, [x1]
+# CHECK: ldlar w0, [x1]
+# CHECK: ldlar x0, [x1]
+# CHECK: stllrb w0, [x1]
+# CHECK: stllrh w0, [x1]
+# CHECK: stllr w0, [x1]
+# CHECK: stllr x0, [x1]
+0x00,0xa4,0x18,0xd5
+0x20,0xa4,0x18,0xd5
+0x40,0xa4,0x18,0xd5
+0x60,0xa4,0x18,0xd5
+0xe0,0xa4,0x38,0xd5
+# CHECK: msr LORSA_EL1, x0
+# CHECK: msr LOREA_EL1, x0
+# CHECK: msr LORN_EL1, x0
+# CHECK: msr LORC_EL1, x0
+# CHECK: mrs x0, LORID_EL1
Propchange: llvm/trunk/test/MC/Disassembler/AArch64/armv8.1a-lor.txt
------------------------------------------------------------------------------
svn:eol-style = native
Propchange: llvm/trunk/test/MC/Disassembler/AArch64/armv8.1a-lor.txt
------------------------------------------------------------------------------
svn:keywords = Rev Date Author URL Id
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