[llvm] r234768 - Revert revisions r234755, r234759, r234760
Krzysztof Parzyszek
kparzysz at codeaurora.org
Mon Apr 13 10:59:28 PDT 2015
I'm fixing this on Hexagon.
-K
On 4/13/2015 12:47 PM, Jan Vesely wrote:
> Author: jvesely
> Date: Mon Apr 13 12:47:15 2015
> New Revision: 234768
>
> URL: http://llvm.org/viewvc/llvm-project?rev=234768&view=rev
> Log:
> Revert revisions r234755, r234759, r234760
>
> Revert "Remove default in fully-covered switch (to fix Clang -Werror -Wcovered-switch-default)"
> Revert "R600: Add carry and borrow instructions. Use them to implement UADDO/USUBO"
> Revert "LegalizeDAG: Try to use Overflow operations when expanding ADD/SUB"
>
> Using overflow operations fails CodeGen/Generic/2011-07-07-ScheduleDAGCrash.ll
> on hexagon, nvptx, and r600. Revert while I investigate.
>
> Modified:
> llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
> llvm/trunk/lib/Target/R600/AMDGPUISelLowering.cpp
> llvm/trunk/lib/Target/R600/AMDGPUISelLowering.h
> llvm/trunk/lib/Target/R600/AMDGPUInstrInfo.td
> llvm/trunk/lib/Target/R600/AMDGPUSubtarget.h
> llvm/trunk/lib/Target/R600/EvergreenInstructions.td
> llvm/trunk/lib/Target/R600/R600ISelLowering.cpp
> llvm/trunk/lib/Target/R600/R600ISelLowering.h
> llvm/trunk/test/CodeGen/Hexagon/adde.ll
> llvm/trunk/test/CodeGen/Hexagon/sube.ll
> llvm/trunk/test/CodeGen/NVPTX/add-128bit.ll
> llvm/trunk/test/CodeGen/R600/add.ll
> llvm/trunk/test/CodeGen/R600/sub.ll
> llvm/trunk/test/CodeGen/R600/uaddo.ll
> llvm/trunk/test/CodeGen/R600/usubo.ll
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp?rev=234768&r1=234767&r2=234768&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp Mon Apr 13 12:47:15 2015
> @@ -1629,38 +1629,6 @@ void DAGTypeLegalizer::ExpandIntRes_ADDS
> return;
> }
>
> - bool hasOVF =
> - TLI.isOperationLegalOrCustom(N->getOpcode() == ISD::ADD ?
> - ISD::UADDO : ISD::USUBO,
> - TLI.getTypeToExpandTo(*DAG.getContext(), NVT));
> - if (hasOVF) {
> - SDVTList VTList = DAG.getVTList(NVT, NVT);
> - TargetLoweringBase::BooleanContent BoolType = TLI.getBooleanContents(NVT);
> - int RevOpc;
> - if (N->getOpcode() == ISD::ADD) {
> - RevOpc = ISD::SUB;
> - Lo = DAG.getNode(ISD::UADDO, dl, VTList, LoOps);
> - Hi = DAG.getNode(ISD::ADD, dl, NVT, makeArrayRef(HiOps, 2));
> - } else {
> - RevOpc = ISD::ADD;
> - Lo = DAG.getNode(ISD::USUBO, dl, VTList, LoOps);
> - Hi = DAG.getNode(ISD::SUB, dl, NVT, makeArrayRef(HiOps, 2));
> - }
> - SDValue OVF = Lo.getValue(1);
> -
> - switch (BoolType) {
> - case TargetLoweringBase::UndefinedBooleanContent:
> - OVF = DAG.getNode(ISD::AND, dl, NVT, DAG.getConstant(1, NVT), OVF);
> - // Fallthrough
> - case TargetLoweringBase::ZeroOrOneBooleanContent:
> - Hi = DAG.getNode(N->getOpcode(), dl, NVT, Hi, OVF);
> - break;
> - case TargetLoweringBase::ZeroOrNegativeOneBooleanContent:
> - Hi = DAG.getNode(RevOpc, dl, NVT, Hi, OVF);
> - }
> - return;
> - }
> -
> if (N->getOpcode() == ISD::ADD) {
> Lo = DAG.getNode(ISD::ADD, dl, NVT, LoOps);
> Hi = DAG.getNode(ISD::ADD, dl, NVT, makeArrayRef(HiOps, 2));
>
> Modified: llvm/trunk/lib/Target/R600/AMDGPUISelLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/AMDGPUISelLowering.cpp?rev=234768&r1=234767&r2=234768&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/R600/AMDGPUISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/R600/AMDGPUISelLowering.cpp Mon Apr 13 12:47:15 2015
> @@ -2763,12 +2763,6 @@ void AMDGPUTargetLowering::computeKnownB
> KnownZero, KnownOne, DAG, Depth);
> break;
>
> - case AMDGPUISD::CARRY:
> - case AMDGPUISD::BORROW: {
> - KnownZero = APInt::getHighBitsSet(32, 31);
> - break;
> - }
> -
> case AMDGPUISD::BFE_I32:
> case AMDGPUISD::BFE_U32: {
> ConstantSDNode *CWidth = dyn_cast<ConstantSDNode>(Op.getOperand(2));
> @@ -2811,10 +2805,6 @@ unsigned AMDGPUTargetLowering::ComputeNu
> return Width ? 32 - (Width->getZExtValue() & 0x1f) : 1;
> }
>
> - case AMDGPUISD::CARRY:
> - case AMDGPUISD::BORROW:
> - return 31;
> -
> default:
> return 1;
> }
>
> Modified: llvm/trunk/lib/Target/R600/AMDGPUISelLowering.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/AMDGPUISelLowering.h?rev=234768&r1=234767&r2=234768&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/R600/AMDGPUISelLowering.h (original)
> +++ llvm/trunk/lib/Target/R600/AMDGPUISelLowering.h Mon Apr 13 12:47:15 2015
> @@ -250,8 +250,6 @@ enum {
> LDEXP,
> FP_CLASS,
> DOT4,
> - CARRY,
> - BORROW,
> BFE_U32, // Extract range of bits with zero extension to 32-bits.
> BFE_I32, // Extract range of bits with sign extension to 32-bits.
> BFI, // (src0 & src1) | (~src0 & src2)
>
> Modified: llvm/trunk/lib/Target/R600/AMDGPUInstrInfo.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/AMDGPUInstrInfo.td?rev=234768&r1=234767&r2=234768&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/R600/AMDGPUInstrInfo.td (original)
> +++ llvm/trunk/lib/Target/R600/AMDGPUInstrInfo.td Mon Apr 13 12:47:15 2015
> @@ -136,13 +136,6 @@ def AMDGPUumin3 : SDNode<"AMDGPUISD::UMI
> [/*SDNPCommutative, SDNPAssociative*/]
> >;
>
> -// out = (src0 + src1 > 0xFFFFFFFF) ? 1 : 0
> -def AMDGPUcarry : SDNode<"AMDGPUISD::CARRY", SDTIntBinOp, []>;
> -
> -// out = (src1 > src0) ? 1 : 0
> -def AMDGPUborrow : SDNode<"AMDGPUISD::BORROW", SDTIntBinOp, []>;
> -
> -
> def AMDGPUcvt_f32_ubyte0 : SDNode<"AMDGPUISD::CVT_F32_UBYTE0",
> SDTIntToFPOp, []>;
> def AMDGPUcvt_f32_ubyte1 : SDNode<"AMDGPUISD::CVT_F32_UBYTE1",
>
> Modified: llvm/trunk/lib/Target/R600/AMDGPUSubtarget.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/AMDGPUSubtarget.h?rev=234768&r1=234767&r2=234768&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/R600/AMDGPUSubtarget.h (original)
> +++ llvm/trunk/lib/Target/R600/AMDGPUSubtarget.h Mon Apr 13 12:47:15 2015
> @@ -183,14 +183,6 @@ public:
> return (getGeneration() >= EVERGREEN);
> }
>
> - bool hasCARRY() const {
> - return (getGeneration() >= EVERGREEN);
> - }
> -
> - bool hasBORROW() const {
> - return (getGeneration() >= EVERGREEN);
> - }
> -
> bool IsIRStructurizerEnabled() const {
> return EnableIRStructurizer;
> }
>
> Modified: llvm/trunk/lib/Target/R600/EvergreenInstructions.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/EvergreenInstructions.td?rev=234768&r1=234767&r2=234768&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/R600/EvergreenInstructions.td (original)
> +++ llvm/trunk/lib/Target/R600/EvergreenInstructions.td Mon Apr 13 12:47:15 2015
> @@ -335,9 +335,6 @@ defm CUBE_eg : CUBE_Common<0xC0>;
>
> def BCNT_INT : R600_1OP_Helper <0xAA, "BCNT_INT", ctpop, VecALU>;
>
> -def ADDC_UINT : R600_2OP_Helper <0x52, "ADDC_UINT", AMDGPUcarry>;
> -def SUBB_UINT : R600_2OP_Helper <0x53, "SUBB_UINT", AMDGPUborrow>;
> -
> def FFBH_UINT : R600_1OP_Helper <0xAB, "FFBH_UINT", ctlz_zero_undef, VecALU>;
> def FFBL_INT : R600_1OP_Helper <0xAC, "FFBL_INT", cttz_zero_undef, VecALU>;
>
>
> Modified: llvm/trunk/lib/Target/R600/R600ISelLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/R600ISelLowering.cpp?rev=234768&r1=234767&r2=234768&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/R600/R600ISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/R600/R600ISelLowering.cpp Mon Apr 13 12:47:15 2015
> @@ -91,15 +91,6 @@ R600TargetLowering::R600TargetLowering(T
> setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
> setOperationAction(ISD::SELECT, MVT::v4i32, Expand);
>
> - // ADD, SUB overflow. These need to be Custom because
> - // SelectionDAGLegalize::LegalizeOp (LegalizeDAG.cpp)
> - // turns Legal into expand
> - if (Subtarget->hasCARRY())
> - setOperationAction(ISD::UADDO, MVT::i32, Custom);
> -
> - if (Subtarget->hasBORROW())
> - setOperationAction(ISD::USUBO, MVT::i32, Custom);
> -
> // Expand sign extension of vectors
> if (!Subtarget->hasBFE())
> setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
> @@ -172,6 +163,8 @@ R600TargetLowering::R600TargetLowering(T
> setTargetDAGCombine(ISD::SELECT_CC);
> setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
>
> + setOperationAction(ISD::SUB, MVT::i64, Expand);
> +
> // These should be replaced by UDVIREM, but it does not happen automatically
> // during Type Legalization
> setOperationAction(ISD::UDIV, MVT::i64, Custom);
> @@ -592,8 +585,6 @@ SDValue R600TargetLowering::LowerOperati
> case ISD::SHL_PARTS: return LowerSHLParts(Op, DAG);
> case ISD::SRA_PARTS:
> case ISD::SRL_PARTS: return LowerSRXParts(Op, DAG);
> - case ISD::UADDO: return LowerUADDSUBO(Op, DAG, ISD::ADD, AMDGPUISD::CARRY);
> - case ISD::USUBO: return LowerUADDSUBO(Op, DAG, ISD::SUB, AMDGPUISD::BORROW);
> case ISD::FCOS:
> case ISD::FSIN: return LowerTrig(Op, DAG);
> case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
> @@ -1085,24 +1076,6 @@ SDValue R600TargetLowering::LowerSRXPart
> return DAG.getNode(ISD::MERGE_VALUES, DL, DAG.getVTList(VT,VT), Lo, Hi);
> }
>
> -SDValue R600TargetLowering::LowerUADDSUBO(SDValue Op, SelectionDAG &DAG,
> - unsigned mainop, unsigned ovf) const {
> - SDLoc DL(Op);
> - EVT VT = Op.getValueType();
> -
> - SDValue Lo = Op.getOperand(0);
> - SDValue Hi = Op.getOperand(1);
> -
> - SDValue OVF = DAG.getNode(ovf, DL, VT, Lo, Hi);
> - // Extend sign.
> - OVF = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT, OVF,
> - DAG.getValueType(MVT::i1));
> -
> - SDValue Res = DAG.getNode(mainop, DL, VT, Lo, Hi);
> -
> - return DAG.getNode(ISD::MERGE_VALUES, DL, DAG.getVTList(VT, VT), Res, OVF);
> -}
> -
> SDValue R600TargetLowering::LowerFPTOUINT(SDValue Op, SelectionDAG &DAG) const {
> return DAG.getNode(
> ISD::SETCC,
>
> Modified: llvm/trunk/lib/Target/R600/R600ISelLowering.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/R600ISelLowering.h?rev=234768&r1=234767&r2=234768&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/R600/R600ISelLowering.h (original)
> +++ llvm/trunk/lib/Target/R600/R600ISelLowering.h Mon Apr 13 12:47:15 2015
> @@ -63,8 +63,6 @@ private:
> SDValue LowerTrig(SDValue Op, SelectionDAG &DAG) const;
> SDValue LowerSHLParts(SDValue Op, SelectionDAG &DAG) const;
> SDValue LowerSRXParts(SDValue Op, SelectionDAG &DAG) const;
> - SDValue LowerUADDSUBO(SDValue Op, SelectionDAG &DAG,
> - unsigned mainop, unsigned ovf) const;
>
> SDValue stackPtrToRegIndex(SDValue Ptr, unsigned StackWidth,
> SelectionDAG &DAG) const;
>
> Modified: llvm/trunk/test/CodeGen/Hexagon/adde.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/adde.ll?rev=234768&r1=234767&r2=234768&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/Hexagon/adde.ll (original)
> +++ llvm/trunk/test/CodeGen/Hexagon/adde.ll Mon Apr 13 12:47:15 2015
> @@ -1,9 +1,16 @@
> ; RUN: llc -march=hexagon -hexagon-expand-condsets=0 < %s | FileCheck %s
>
> +; CHECK: r{{[0-9]+:[0-9]+}} = #0
> +; CHECK: r{{[0-9]+:[0-9]+}} = #1
> ; CHECK: r{{[0-9]+:[0-9]+}} = add(r{{[0-9]+:[0-9]+}}, r{{[0-9]+:[0-9]+}})
> -; CHECK: r{{[0-9]+:[0-9]+}} = add(r{{[0-9]+:[0-9]+}}, r{{[0-9]+:[0-9]+}})
> ; CHECK: p{{[0-9]+}} = cmp.gtu(r{{[0-9]+:[0-9]+}}, r{{[0-9]+:[0-9]+}})
> -; CHECK: r{{[0-9]+}} = mux(p{{[0-9]+}}, #1, #0)
> +; CHECK: p{{[0-9]+}} = cmp.gtu(r{{[0-9]+:[0-9]+}}, r{{[0-9]+:[0-9]+}})
> +; CHECK: r{{[0-9]+}} = mux(p{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}})
> +; CHECK: r{{[0-9]+}} = mux(p{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}})
> +; CHECK: r{{[0-9]+:[0-9]+}} = combine(r{{[0-9]+}}, r{{[0-9]+}})
> +; CHECK: r{{[0-9]+}} = mux(p{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}})
> +; CHECK: r{{[0-9]+}} = mux(p{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}})
> +; CHECK: r{{[0-9]+:[0-9]+}} = combine(r{{[0-9]+}}, r{{[0-9]+}})
> ; CHECK: r{{[0-9]+:[0-9]+}} = add(r{{[0-9]+:[0-9]+}}, r{{[0-9]+:[0-9]+}})
>
>
>
> Modified: llvm/trunk/test/CodeGen/Hexagon/sube.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/sube.ll?rev=234768&r1=234767&r2=234768&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/Hexagon/sube.ll (original)
> +++ llvm/trunk/test/CodeGen/Hexagon/sube.ll Mon Apr 13 12:47:15 2015
> @@ -1,10 +1,13 @@
> ; RUN: llc -march=hexagon -hexagon-expand-condsets=0 < %s | FileCheck %s
>
> -; CHECK: r{{[0-9]+:[0-9]+}} = sub(r{{[0-9]+:[0-9]+}}, r{{[0-9]+:[0-9]+}})
> -; CHECK: r{{[0-9]+:[0-9]+}} = sub(r{{[0-9]+:[0-9]+}}, r{{[0-9]+:[0-9]+}})
> +; CHECK: r{{[0-9]+:[0-9]+}} = #0
> +; CHECK: r{{[0-9]+:[0-9]+}} = #1
> ; CHECK: p{{[0-9]+}} = cmp.gtu(r{{[0-9]+:[0-9]+}}, r{{[0-9]+:[0-9]+}})
> -; CHECK: r{{[0-9]+}} = mux(p{{[0-9]+}}, #1, #0)
> +; CHECK: r{{[0-9]+}} = mux(p{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}})
> +; CHECK: r{{[0-9]+}} = mux(p{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}})
> +; CHECK: r{{[0-9]+:[0-9]+}} = sub(r{{[0-9]+:[0-9]+}}, r{{[0-9]+:[0-9]+}})
> ; CHECK: r{{[0-9]+:[0-9]+}} = sub(r{{[0-9]+:[0-9]+}}, r{{[0-9]+:[0-9]+}})
> +; CHECK: r{{[0-9]+:[0-9]+}} = combine(r{{[0-9]+}}, r{{[0-9]+}})
>
> define void @check_sube_subc(i64 %AL, i64 %AH, i64 %BL, i64 %BH, i64* %RL, i64* %RH) {
> entry:
>
> Modified: llvm/trunk/test/CodeGen/NVPTX/add-128bit.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/NVPTX/add-128bit.ll?rev=234768&r1=234767&r2=234768&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/NVPTX/add-128bit.ll (original)
> +++ llvm/trunk/test/CodeGen/NVPTX/add-128bit.ll Mon Apr 13 12:47:15 2015
> @@ -7,8 +7,10 @@ target datalayout = "e-p:32:32:32-i1:8:8
> define void @foo(i64 %a, i64 %add, i128* %retptr) {
> ; CHECK: add.s64
> ; CHECK: setp.lt.u64
> +; CHECK: setp.lt.u64
> +; CHECK: selp.b64
> ; CHECK: selp.b64
> -; CHECK: sub.s64
> +; CHECK: add.s64
> %t1 = sext i64 %a to i128
> %add2 = zext i64 %add to i128
> %val = add i128 %t1, %add2
>
> Modified: llvm/trunk/test/CodeGen/R600/add.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/add.ll?rev=234768&r1=234767&r2=234768&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/R600/add.ll (original)
> +++ llvm/trunk/test/CodeGen/R600/add.ll Mon Apr 13 12:47:15 2015
> @@ -62,7 +62,6 @@ define void @test4(<4 x i32> addrspace(1
> ; EG: ADD_INT
> ; EG: ADD_INT
> ; EG: ADD_INT
> -
> ; SI: s_add_i32
> ; SI: s_add_i32
> ; SI: s_add_i32
> @@ -95,7 +94,6 @@ entry:
> ; EG: ADD_INT
> ; EG: ADD_INT
> ; EG: ADD_INT
> -
> ; SI: s_add_i32
> ; SI: s_add_i32
> ; SI: s_add_i32
> @@ -122,14 +120,6 @@ entry:
> ; FUNC-LABEL: {{^}}add64:
> ; SI: s_add_u32
> ; SI: s_addc_u32
> -
> -; EG: MEM_RAT_CACHELESS STORE_RAW [[LO:T[0-9]+\.[XYZW]]]
> -; EG: MEM_RAT_CACHELESS STORE_RAW [[HI:T[0-9]+\.[XYZW]]]
> -; EG-DAG: ADD_INT {{[* ]*}}[[LO]]
> -; EG-DAG: ADDC_UINT
> -; EG-DAG: ADD_INT
> -; EG-DAG: ADD_INT {{[* ]*}}[[HI]]
> -; EG-NOT: SUB
> define void @add64(i64 addrspace(1)* %out, i64 %a, i64 %b) {
> entry:
> %0 = add i64 %a, %b
> @@ -144,14 +134,6 @@ entry:
>
> ; FUNC-LABEL: {{^}}add64_sgpr_vgpr:
> ; SI-NOT: v_addc_u32_e32 s
> -
> -; EG: MEM_RAT_CACHELESS STORE_RAW [[LO:T[0-9]+\.[XYZW]]]
> -; EG: MEM_RAT_CACHELESS STORE_RAW [[HI:T[0-9]+\.[XYZW]]]
> -; EG-DAG: ADD_INT {{[* ]*}}[[LO]]
> -; EG-DAG: ADDC_UINT
> -; EG-DAG: ADD_INT
> -; EG-DAG: ADD_INT {{[* ]*}}[[HI]]
> -; EG-NOT: SUB
> define void @add64_sgpr_vgpr(i64 addrspace(1)* %out, i64 %a, i64 addrspace(1)* %in) {
> entry:
> %0 = load i64, i64 addrspace(1)* %in
> @@ -164,14 +146,6 @@ entry:
> ; FUNC-LABEL: {{^}}add64_in_branch:
> ; SI: s_add_u32
> ; SI: s_addc_u32
> -
> -; EG: MEM_RAT_CACHELESS STORE_RAW [[LO:T[0-9]+\.[XYZW]]]
> -; EG: MEM_RAT_CACHELESS STORE_RAW [[HI:T[0-9]+\.[XYZW]]]
> -; EG-DAG: ADD_INT {{[* ]*}}[[LO]]
> -; EG-DAG: ADDC_UINT
> -; EG-DAG: ADD_INT
> -; EG-DAG: ADD_INT {{[* ]*}}[[HI]]
> -; EG-NOT: SUB
> define void @add64_in_branch(i64 addrspace(1)* %out, i64 addrspace(1)* %in, i64 %a, i64 %b, i64 %c) {
> entry:
> %0 = icmp eq i64 %a, 0
>
> Modified: llvm/trunk/test/CodeGen/R600/sub.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/sub.ll?rev=234768&r1=234767&r2=234768&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/R600/sub.ll (original)
> +++ llvm/trunk/test/CodeGen/R600/sub.ll Mon Apr 13 12:47:15 2015
> @@ -58,13 +58,11 @@ define void @test_sub_v4i32(<4 x i32> ad
> ; SI: s_sub_u32
> ; SI: s_subb_u32
>
> -; EG: MEM_RAT_CACHELESS STORE_RAW [[LO:T[0-9]+\.[XYZW]]]
> -; EG: MEM_RAT_CACHELESS STORE_RAW [[HI:T[0-9]+\.[XYZW]]]
> -; EG-DAG: SUB_INT {{[* ]*}}[[LO]]
> -; EG-DAG: SUBB_UINT
> +; EG-DAG: SETGE_UINT
> +; EG-DAG: CNDE_INT
> +; EG-DAG: SUB_INT
> +; EG-DAG: SUB_INT
> ; EG-DAG: SUB_INT
> -; EG-DAG: SUB_INT {{[* ]*}}[[HI]]
> -; EG-NOT: SUB
> define void @s_sub_i64(i64 addrspace(1)* noalias %out, i64 %a, i64 %b) nounwind {
> %result = sub i64 %a, %b
> store i64 %result, i64 addrspace(1)* %out, align 8
> @@ -75,13 +73,11 @@ define void @s_sub_i64(i64 addrspace(1)*
> ; SI: v_sub_i32_e32
> ; SI: v_subb_u32_e32
>
> -; EG: MEM_RAT_CACHELESS STORE_RAW [[LO:T[0-9]+\.[XYZW]]]
> -; EG: MEM_RAT_CACHELESS STORE_RAW [[HI:T[0-9]+\.[XYZW]]]
> -; EG-DAG: SUB_INT {{[* ]*}}[[LO]]
> -; EG-DAG: SUBB_UINT
> +; EG-DAG: SETGE_UINT
> +; EG-DAG: CNDE_INT
> +; EG-DAG: SUB_INT
> +; EG-DAG: SUB_INT
> ; EG-DAG: SUB_INT
> -; EG-DAG: SUB_INT {{[* ]*}}[[HI]]
> -; EG-NOT: SUB
> define void @v_sub_i64(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %inA, i64 addrspace(1)* noalias %inB) nounwind {
> %tid = call i32 @llvm.r600.read.tidig.x() readnone
> %a_ptr = getelementptr i64, i64 addrspace(1)* %inA, i32 %tid
>
> Modified: llvm/trunk/test/CodeGen/R600/uaddo.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/uaddo.ll?rev=234768&r1=234767&r2=234768&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/R600/uaddo.ll (original)
> +++ llvm/trunk/test/CodeGen/R600/uaddo.ll Mon Apr 13 12:47:15 2015
> @@ -1,6 +1,6 @@
> ; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs< %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
> ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs< %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
> -; RUN: llc -march=r600 -mcpu=cypress -verify-machineinstrs< %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
> +; RUN: llc -march=r600 -mcpu=cypress -verify-machineinstrs< %s
>
> declare { i32, i1 } @llvm.uadd.with.overflow.i32(i32, i32) nounwind readnone
> declare { i64, i1 } @llvm.uadd.with.overflow.i64(i64, i64) nounwind readnone
> @@ -9,9 +9,6 @@ declare { i64, i1 } @llvm.uadd.with.over
> ; SI: add
> ; SI: addc
> ; SI: addc
> -
> -; EG: ADDC_UINT
> -; EG: ADDC_UINT
> define void @uaddo_i64_zext(i64 addrspace(1)* %out, i64 %a, i64 %b) nounwind {
> %uadd = call { i64, i1 } @llvm.uadd.with.overflow.i64(i64 %a, i64 %b) nounwind
> %val = extractvalue { i64, i1 } %uadd, 0
> @@ -24,9 +21,6 @@ define void @uaddo_i64_zext(i64 addrspac
>
> ; FUNC-LABEL: {{^}}s_uaddo_i32:
> ; SI: s_add_i32
> -
> -; EG: ADDC_UINT
> -; EG: ADD_INT
> define void @s_uaddo_i32(i32 addrspace(1)* %out, i1 addrspace(1)* %carryout, i32 %a, i32 %b) nounwind {
> %uadd = call { i32, i1 } @llvm.uadd.with.overflow.i32(i32 %a, i32 %b) nounwind
> %val = extractvalue { i32, i1 } %uadd, 0
> @@ -38,9 +32,6 @@ define void @s_uaddo_i32(i32 addrspace(1
>
> ; FUNC-LABEL: {{^}}v_uaddo_i32:
> ; SI: v_add_i32
> -
> -; EG: ADDC_UINT
> -; EG: ADD_INT
> define void @v_uaddo_i32(i32 addrspace(1)* %out, i1 addrspace(1)* %carryout, i32 addrspace(1)* %aptr, i32 addrspace(1)* %bptr) nounwind {
> %a = load i32, i32 addrspace(1)* %aptr, align 4
> %b = load i32, i32 addrspace(1)* %bptr, align 4
> @@ -55,9 +46,6 @@ define void @v_uaddo_i32(i32 addrspace(1
> ; FUNC-LABEL: {{^}}s_uaddo_i64:
> ; SI: s_add_u32
> ; SI: s_addc_u32
> -
> -; EG: ADDC_UINT
> -; EG: ADD_INT
> define void @s_uaddo_i64(i64 addrspace(1)* %out, i1 addrspace(1)* %carryout, i64 %a, i64 %b) nounwind {
> %uadd = call { i64, i1 } @llvm.uadd.with.overflow.i64(i64 %a, i64 %b) nounwind
> %val = extractvalue { i64, i1 } %uadd, 0
> @@ -70,9 +58,6 @@ define void @s_uaddo_i64(i64 addrspace(1
> ; FUNC-LABEL: {{^}}v_uaddo_i64:
> ; SI: v_add_i32
> ; SI: v_addc_u32
> -
> -; EG: ADDC_UINT
> -; EG: ADD_INT
> define void @v_uaddo_i64(i64 addrspace(1)* %out, i1 addrspace(1)* %carryout, i64 addrspace(1)* %aptr, i64 addrspace(1)* %bptr) nounwind {
> %a = load i64, i64 addrspace(1)* %aptr, align 4
> %b = load i64, i64 addrspace(1)* %bptr, align 4
>
> Modified: llvm/trunk/test/CodeGen/R600/usubo.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/usubo.ll?rev=234768&r1=234767&r2=234768&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/R600/usubo.ll (original)
> +++ llvm/trunk/test/CodeGen/R600/usubo.ll Mon Apr 13 12:47:15 2015
> @@ -1,14 +1,11 @@
> ; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs< %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
> ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs< %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
> -; RUN: llc -march=r600 -mcpu=cypress -verify-machineinstrs< %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
> +; RUN: llc -march=r600 -mcpu=cypress -verify-machineinstrs< %s
>
> declare { i32, i1 } @llvm.usub.with.overflow.i32(i32, i32) nounwind readnone
> declare { i64, i1 } @llvm.usub.with.overflow.i64(i64, i64) nounwind readnone
>
> ; FUNC-LABEL: {{^}}usubo_i64_zext:
> -
> -; EG: SUBB_UINT
> -; EG: ADDC_UINT
> define void @usubo_i64_zext(i64 addrspace(1)* %out, i64 %a, i64 %b) nounwind {
> %usub = call { i64, i1 } @llvm.usub.with.overflow.i64(i64 %a, i64 %b) nounwind
> %val = extractvalue { i64, i1 } %usub, 0
> @@ -21,9 +18,6 @@ define void @usubo_i64_zext(i64 addrspac
>
> ; FUNC-LABEL: {{^}}s_usubo_i32:
> ; SI: s_sub_i32
> -
> -; EG-DAG: SUBB_UINT
> -; EG-DAG: SUB_INT
> define void @s_usubo_i32(i32 addrspace(1)* %out, i1 addrspace(1)* %carryout, i32 %a, i32 %b) nounwind {
> %usub = call { i32, i1 } @llvm.usub.with.overflow.i32(i32 %a, i32 %b) nounwind
> %val = extractvalue { i32, i1 } %usub, 0
> @@ -35,9 +29,6 @@ define void @s_usubo_i32(i32 addrspace(1
>
> ; FUNC-LABEL: {{^}}v_usubo_i32:
> ; SI: v_subrev_i32_e32
> -
> -; EG-DAG: SUBB_UINT
> -; EG-DAG: SUB_INT
> define void @v_usubo_i32(i32 addrspace(1)* %out, i1 addrspace(1)* %carryout, i32 addrspace(1)* %aptr, i32 addrspace(1)* %bptr) nounwind {
> %a = load i32, i32 addrspace(1)* %aptr, align 4
> %b = load i32, i32 addrspace(1)* %bptr, align 4
> @@ -52,11 +43,6 @@ define void @v_usubo_i32(i32 addrspace(1
> ; FUNC-LABEL: {{^}}s_usubo_i64:
> ; SI: s_sub_u32
> ; SI: s_subb_u32
> -
> -; EG-DAG: SUBB_UINT
> -; EG-DAG: SUB_INT
> -; EG-DAG: SUB_INT
> -; EG: SUB_INT
> define void @s_usubo_i64(i64 addrspace(1)* %out, i1 addrspace(1)* %carryout, i64 %a, i64 %b) nounwind {
> %usub = call { i64, i1 } @llvm.usub.with.overflow.i64(i64 %a, i64 %b) nounwind
> %val = extractvalue { i64, i1 } %usub, 0
> @@ -69,11 +55,6 @@ define void @s_usubo_i64(i64 addrspace(1
> ; FUNC-LABEL: {{^}}v_usubo_i64:
> ; SI: v_sub_i32
> ; SI: v_subb_u32
> -
> -; EG-DAG: SUBB_UINT
> -; EG-DAG: SUB_INT
> -; EG-DAG: SUB_INT
> -; EG: SUB_INT
> define void @v_usubo_i64(i64 addrspace(1)* %out, i1 addrspace(1)* %carryout, i64 addrspace(1)* %aptr, i64 addrspace(1)* %bptr) nounwind {
> %a = load i64, i64 addrspace(1)* %aptr, align 4
> %b = load i64, i64 addrspace(1)* %bptr, align 4
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
hosted by The Linux Foundation
More information about the llvm-commits
mailing list