[PATCH] [mips] [IAS] Inline assemble-time shifting out of createLShiftOri. NFC.

[Toma Tabacu]

Hi dsanders,

Do the assemble-time shifts from createLShiftOri at the source, which groups all the shifting together, closer to the main logic path, and
store the results in concisely-named variables to improve code clarity.

http://reviews.llvm.org/D8973

Files:
  lib/Target/Mips/AsmParser/MipsAsmParser.cpp

Index: lib/Target/Mips/AsmParser/MipsAsmParser.cpp
===================================================================
--- lib/Target/Mips/AsmParser/MipsAsmParser.cpp
+++ lib/Target/Mips/AsmParser/MipsAsmParser.cpp
@@ -1649,12 +1649,11 @@
   Instructions.push_back(tmpInst);
 }
 
-template <int Shift, bool PerformShift>
+template <bool PerformShift>
 void createLShiftOri(int64_t Value, unsigned RegNo, SMLoc IDLoc,
                    SmallVectorImpl<MCInst> &Instructions) {
-  createLShiftOri<PerformShift>(
-      MCOperand::CreateImm(((Value & (0xffffLL << Shift)) >> Shift)), RegNo,
-      IDLoc, Instructions);
+  createLShiftOri<PerformShift>(MCOperand::CreateImm(Value), RegNo, IDLoc,
+                                Instructions);
 }
 }
 
@@ -1733,11 +1732,14 @@
     // For all other values which are representable as a 32-bit integer:
     // li d,j => lui d,hi16(j)
     //           ori d,d,lo16(j)
+    uint16_t Hi16 = (ImmValue & (0xffffLL << 16)) >> 16;
+    uint16_t Lo16 = ImmValue & 0xffffLL;
+
     tmpInst.setOpcode(Mips::LUi);
     tmpInst.addOperand(MCOperand::CreateReg(Reg));
-    tmpInst.addOperand(MCOperand::CreateImm((ImmValue & 0xffff0000) >> 16));
+    tmpInst.addOperand(MCOperand::CreateImm(Hi16));
     Instructions.push_back(tmpInst);
-    createLShiftOri<0, false>(ImmValue, Reg, IDLoc, Instructions);
+    createLShiftOri<false>(Lo16, Reg, IDLoc, Instructions);
   } else if ((ImmValue & (0xffffLL << 48)) == 0) {
     if (!isGP64bit()) {
       Error(IDLoc, "instruction requires a 64-bit architecture");
@@ -1757,13 +1759,16 @@
     //           ori d,d,hi16(lo32(j))
     //           dsll d,d,16
     //           ori d,d,lo16(lo32(j))
+    uint16_t Lo16OfHi32 = (ImmValue & (0xffffLL << 32)) >> 32;
+    uint16_t Hi16OfLo32 = (ImmValue & (0xffffLL << 16)) >> 16;
+    uint16_t Lo16OfLo32 = ImmValue & 0xffffLL;
+
     tmpInst.setOpcode(Mips::LUi);
     tmpInst.addOperand(MCOperand::CreateReg(Reg));
-    tmpInst.addOperand(
-        MCOperand::CreateImm((ImmValue & (0xffffLL << 32)) >> 32));
+    tmpInst.addOperand(MCOperand::CreateImm(Lo16OfHi32));
     Instructions.push_back(tmpInst);
-    createLShiftOri<16, false>(ImmValue, Reg, IDLoc, Instructions);
-    createLShiftOri<0, true>(ImmValue, Reg, IDLoc, Instructions);
+    createLShiftOri<false>(Hi16OfLo32, Reg, IDLoc, Instructions);
+    createLShiftOri<true>(Lo16OfLo32, Reg, IDLoc, Instructions);
   } else {
     if (!isGP64bit()) {
       Error(IDLoc, "instruction requires a 64-bit architecture");
@@ -1784,14 +1789,18 @@
     //           ori d,d,hi16(lo32(j))
     //           dsll d,d,16
     //           ori d,d,lo16(lo32(j))
+    uint16_t Hi16OfHi32 = (ImmValue & (0xffffLL << 48)) >> 48;
+    uint16_t Lo16OfHi32 = (ImmValue & (0xffffLL << 32)) >> 32;
+    uint16_t Hi16OfLo32 = (ImmValue & (0xffffLL << 16)) >> 16;
+    uint16_t Lo16OfLo32 = ImmValue & 0xffffLL;
+
     tmpInst.setOpcode(Mips::LUi);
     tmpInst.addOperand(MCOperand::CreateReg(Reg));
-    tmpInst.addOperand(
-        MCOperand::CreateImm((ImmValue & (0xffffLL << 48)) >> 48));
+    tmpInst.addOperand(MCOperand::CreateImm(Hi16OfHi32));
     Instructions.push_back(tmpInst);
-    createLShiftOri<32, false>(ImmValue, Reg, IDLoc, Instructions);
-    createLShiftOri<16, true>(ImmValue, Reg, IDLoc, Instructions);
-    createLShiftOri<0, true>(ImmValue, Reg, IDLoc, Instructions);
+    createLShiftOri<false>(Lo16OfHi32, Reg, IDLoc, Instructions);
+    createLShiftOri<true>(Hi16OfLo32, Reg, IDLoc, Instructions);
+    createLShiftOri<true>(Lo16OfLo32, Reg, IDLoc, Instructions);
   }
   return false;
 }

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