[PATCH] [mips] [IAS] Rename the createShiftOr function to createLShiftOri. NFC.
Toma Tabacu
toma.tabacu at imgtec.com
Fri Apr 10 07:40:59 PDT 2015
Hi dsanders,
The new name is more accurate with regard to the functionality.
http://reviews.llvm.org/D8968
Files:
lib/Target/Mips/AsmParser/MipsAsmParser.cpp
Index: lib/Target/Mips/AsmParser/MipsAsmParser.cpp
===================================================================
--- lib/Target/Mips/AsmParser/MipsAsmParser.cpp
+++ lib/Target/Mips/AsmParser/MipsAsmParser.cpp
@@ -1629,7 +1629,7 @@
namespace {
template <bool PerformShift>
-void createShiftOr(MCOperand Operand, unsigned RegNo, SMLoc IDLoc,
+void createLShiftOri(MCOperand Operand, unsigned RegNo, SMLoc IDLoc,
SmallVectorImpl<MCInst> &Instructions) {
MCInst tmpInst;
if (PerformShift) {
@@ -1650,9 +1650,9 @@
}
template <int Shift, bool PerformShift>
-void createShiftOr(int64_t Value, unsigned RegNo, SMLoc IDLoc,
+void createLShiftOri(int64_t Value, unsigned RegNo, SMLoc IDLoc,
SmallVectorImpl<MCInst> &Instructions) {
- createShiftOr<PerformShift>(
+ createLShiftOri<PerformShift>(
MCOperand::CreateImm(((Value & (0xffffLL << Shift)) >> Shift)), RegNo,
IDLoc, Instructions);
}
@@ -1737,7 +1737,7 @@
tmpInst.addOperand(MCOperand::CreateReg(Reg));
tmpInst.addOperand(MCOperand::CreateImm((ImmValue & 0xffff0000) >> 16));
Instructions.push_back(tmpInst);
- createShiftOr<0, false>(ImmValue, Reg, IDLoc, Instructions);
+ createLShiftOri<0, false>(ImmValue, Reg, IDLoc, Instructions);
} else if ((ImmValue & (0xffffLL << 48)) == 0) {
if (!isGP64bit()) {
Error(IDLoc, "instruction requires a 64-bit architecture");
@@ -1762,8 +1762,8 @@
tmpInst.addOperand(
MCOperand::CreateImm((ImmValue & (0xffffLL << 32)) >> 32));
Instructions.push_back(tmpInst);
- createShiftOr<16, false>(ImmValue, Reg, IDLoc, Instructions);
- createShiftOr<0, true>(ImmValue, Reg, IDLoc, Instructions);
+ createLShiftOri<16, false>(ImmValue, Reg, IDLoc, Instructions);
+ createLShiftOri<0, true>(ImmValue, Reg, IDLoc, Instructions);
} else {
if (!isGP64bit()) {
Error(IDLoc, "instruction requires a 64-bit architecture");
@@ -1789,9 +1789,9 @@
tmpInst.addOperand(
MCOperand::CreateImm((ImmValue & (0xffffLL << 48)) >> 48));
Instructions.push_back(tmpInst);
- createShiftOr<32, false>(ImmValue, Reg, IDLoc, Instructions);
- createShiftOr<16, true>(ImmValue, Reg, IDLoc, Instructions);
- createShiftOr<0, true>(ImmValue, Reg, IDLoc, Instructions);
+ createLShiftOri<32, false>(ImmValue, Reg, IDLoc, Instructions);
+ createLShiftOri<16, true>(ImmValue, Reg, IDLoc, Instructions);
+ createLShiftOri<0, true>(ImmValue, Reg, IDLoc, Instructions);
}
return false;
}
@@ -1930,11 +1930,11 @@
tmpInst.addOperand(MCOperand::CreateExpr(HighestExpr));
Instructions.push_back(tmpInst);
- createShiftOr<false>(MCOperand::CreateExpr(HigherExpr), RegNo, SMLoc(),
+ createLShiftOri<false>(MCOperand::CreateExpr(HigherExpr), RegNo, SMLoc(),
Instructions);
- createShiftOr<true>(MCOperand::CreateExpr(HiExpr), RegNo, SMLoc(),
+ createLShiftOri<true>(MCOperand::CreateExpr(HiExpr), RegNo, SMLoc(),
Instructions);
- createShiftOr<true>(MCOperand::CreateExpr(LoExpr), RegNo, SMLoc(),
+ createLShiftOri<true>(MCOperand::CreateExpr(LoExpr), RegNo, SMLoc(),
Instructions);
} else {
// Otherwise, expand to:
@@ -1945,7 +1945,7 @@
tmpInst.addOperand(MCOperand::CreateExpr(HiExpr));
Instructions.push_back(tmpInst);
- createShiftOr<false>(MCOperand::CreateExpr(LoExpr), RegNo, SMLoc(),
+ createLShiftOri<false>(MCOperand::CreateExpr(LoExpr), RegNo, SMLoc(),
Instructions);
}
}
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