[llvm] r234406 - [mips] [IAS] Do not generate redundant move when expanding lw/sw with symbol.

[Toma Tabacu]

Author: tomatabacu
Date: Wed Apr  8 08:52:41 2015
New Revision: 234406

URL: http://llvm.org/viewvc/llvm-project?rev=234406&view=rev
Log:
[mips] [IAS] Do not generate redundant move when expanding lw/sw with symbol.

Summary:
Even though there is no 2nd register operand in the "lw/sw $8, symbol" case, we still try to find one, 
and we end up with $0, which makes us generate an unnecessary "addu $8, $8, $0" (a.k.a. "move $8, $8").

We can avoid this by checking if the 2nd register operand is different from $0, before generating the addu.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D8055

Modified:
    llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
    llvm/trunk/test/MC/Mips/mips-expansions.s

Modified: llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp?rev=234406&r1=234405&r2=234406&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp Wed Apr  8 08:52:41 2015
@@ -2078,12 +2078,14 @@ void MipsAsmParser::expandMemInst(MCInst
   // Prepare TempInst for next instruction.
   TempInst.clear();
   // Add temp register to base.
-  TempInst.setOpcode(Mips::ADDu);
-  TempInst.addOperand(MCOperand::CreateReg(TmpRegNum));
-  TempInst.addOperand(MCOperand::CreateReg(TmpRegNum));
-  TempInst.addOperand(MCOperand::CreateReg(BaseRegNum));
-  Instructions.push_back(TempInst);
-  TempInst.clear();
+  if (BaseRegNum != Mips::ZERO) {
+    TempInst.setOpcode(Mips::ADDu);
+    TempInst.addOperand(MCOperand::CreateReg(TmpRegNum));
+    TempInst.addOperand(MCOperand::CreateReg(TmpRegNum));
+    TempInst.addOperand(MCOperand::CreateReg(BaseRegNum));
+    Instructions.push_back(TempInst);
+    TempInst.clear();
+  }
   // And finally, create original instruction with low part
   // of offset and new base.
   TempInst.setOpcode(Inst.getOpcode());

Modified: llvm/trunk/test/MC/Mips/mips-expansions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips-expansions.s?rev=234406&r1=234405&r2=234406&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips-expansions.s (original)
+++ llvm/trunk/test/MC/Mips/mips-expansions.s Wed Apr  8 08:52:41 2015
@@ -50,6 +50,17 @@
 # CHECK: addu    $1, $1, $9              # encoding: [0x21,0x08,0x29,0x00]
 # CHECK: sw      $10, 57920($1)          # encoding: [0x40,0xe2,0x2a,0xac]
 
+# CHECK:     lui     $8, %hi(symbol)     # encoding: [A,A,0x08,0x3c]
+# CHECK:                                 #   fixup A - offset: 0, value: symbol at ABS_HI, kind: fixup_Mips_HI16
+# CHECK-NOT: move    $8, $8              # encoding: [0x21,0x40,0x00,0x01]
+# CHECK:     lw      $8, %lo(symbol)($8) # encoding: [A,A,0x08,0x8d]
+# CHECK:                                 #   fixup A - offset: 0, value: symbol at ABS_LO, kind: fixup_Mips_LO16
+# CHECK:     lui     $1, %hi(symbol)     # encoding: [A,A,0x01,0x3c]
+# CHECK:                                 #   fixup A - offset: 0, value: symbol at ABS_HI, kind: fixup_Mips_HI16
+# CHECK-NOT: move    $1, $1              # encoding: [0x21,0x08,0x20,0x00]
+# CHECK:     sw      $8, %lo(symbol)($1) # encoding: [A,A,0x28,0xac]
+# CHECK:                                 #   fixup A - offset: 0, value: symbol at ABS_LO, kind: fixup_Mips_LO16
+
 # CHECK: lui     $1, %hi(symbol)
 # CHECK: ldc1    $f0, %lo(symbol)($1)
 # CHECK: lui     $1, %hi(symbol)
@@ -77,5 +88,8 @@
     lw  $t2, 655483($a0)
     sw  $t2, 123456($t1)
 
+    lw  $8, symbol
+    sw  $8, symbol
+
     ldc1 $f0, symbol
     sdc1 $f0, symbol