[llvm] r234092 - [DAGCombiner] Canonicalize vector constants for ADD/MUL/AND/OR/XOR re-association
Simon Pilgrim
llvm-dev at redking.me.uk
Sat Apr 4 03:20:32 PDT 2015
Author: rksimon
Date: Sat Apr 4 05:20:31 2015
New Revision: 234092
URL: http://llvm.org/viewvc/llvm-project?rev=234092&view=rev
Log:
[DAGCombiner] Canonicalize vector constants for ADD/MUL/AND/OR/XOR re-association
Scalar integers are commuted to move constants to the RHS for re-association - this ensures vectors do the same.
Modified:
llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
llvm/trunk/test/CodeGen/X86/vec_reassociate.ll
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=234092&r1=234091&r2=234092&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Sat Apr 4 05:20:31 2015
@@ -1598,7 +1598,8 @@ SDValue DAGCombiner::visitADD(SDNode *N)
if (N0C && N1C)
return DAG.FoldConstantArithmetic(ISD::ADD, VT, N0C, N1C);
// canonicalize constant to RHS
- if (N0C && !N1C)
+ if (isConstantIntBuildVectorOrConstantInt(N0) &&
+ !isConstantIntBuildVectorOrConstantInt(N1))
return DAG.getNode(ISD::ADD, SDLoc(N), VT, N1, N0);
// fold (add x, 0) -> x
if (N1C && N1C->isNullValue())
@@ -1995,8 +1996,9 @@ SDValue DAGCombiner::visitMUL(SDNode *N)
if (N0IsConst && N1IsConst)
return DAG.FoldConstantArithmetic(ISD::MUL, VT, N0.getNode(), N1.getNode());
- // canonicalize constant to RHS
- if (N0IsConst && !N1IsConst)
+ // canonicalize constant to RHS (vector doesn't have to splat)
+ if (isConstantIntBuildVectorOrConstantInt(N0) &&
+ !isConstantIntBuildVectorOrConstantInt(N1))
return DAG.getNode(ISD::MUL, SDLoc(N), VT, N1, N0);
// fold (mul x, 0) -> 0
if (N1IsConst && ConstValue1 == 0)
@@ -2829,7 +2831,8 @@ SDValue DAGCombiner::visitAND(SDNode *N)
if (N0C && N1C)
return DAG.FoldConstantArithmetic(ISD::AND, VT, N0C, N1C);
// canonicalize constant to RHS
- if (N0C && !N1C)
+ if (isConstantIntBuildVectorOrConstantInt(N0) &&
+ !isConstantIntBuildVectorOrConstantInt(N1))
return DAG.getNode(ISD::AND, SDLoc(N), VT, N1, N0);
// fold (and x, -1) -> x
if (N1C && N1C->isAllOnesValue())
@@ -3545,7 +3548,8 @@ SDValue DAGCombiner::visitOR(SDNode *N)
if (N0C && N1C)
return DAG.FoldConstantArithmetic(ISD::OR, VT, N0C, N1C);
// canonicalize constant to RHS
- if (N0C && !N1C)
+ if (isConstantIntBuildVectorOrConstantInt(N0) &&
+ !isConstantIntBuildVectorOrConstantInt(N1))
return DAG.getNode(ISD::OR, SDLoc(N), VT, N1, N0);
// fold (or x, 0) -> x
if (N1C && N1C->isNullValue())
@@ -3887,7 +3891,8 @@ SDValue DAGCombiner::visitXOR(SDNode *N)
if (N0C && N1C)
return DAG.FoldConstantArithmetic(ISD::XOR, VT, N0C, N1C);
// canonicalize constant to RHS
- if (N0C && !N1C)
+ if (isConstantIntBuildVectorOrConstantInt(N0) &&
+ !isConstantIntBuildVectorOrConstantInt(N1))
return DAG.getNode(ISD::XOR, SDLoc(N), VT, N1, N0);
// fold (xor x, 0) -> x
if (N1C && N1C->isNullValue())
Modified: llvm/trunk/test/CodeGen/X86/vec_reassociate.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_reassociate.ll?rev=234092&r1=234091&r2=234092&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/vec_reassociate.ll (original)
+++ llvm/trunk/test/CodeGen/X86/vec_reassociate.ll Sat Apr 4 05:20:31 2015
@@ -11,11 +11,22 @@ define <4 x i32> @add_4i32(<4 x i32> %a0
ret <4 x i32> %3
}
+define <4 x i32> @add_4i32_commute(<4 x i32> %a0, <4 x i32> %a1) {
+ ;CHECK-LABEL: @add_4i32_commute
+ ;CHECK: # BB#0:
+ ;CHECK-NEXT: paddd %xmm1, %xmm0
+ ;CHECK-NEXT: retq
+ %1 = add <4 x i32> <i32 1, i32 -2, i32 3, i32 -4>, %a0
+ %2 = add <4 x i32> <i32 -1, i32 2, i32 -3, i32 4>, %a1
+ %3 = add <4 x i32> %1, %2
+ ret <4 x i32> %3
+}
+
define <4 x i32> @mul_4i32(<4 x i32> %a0, <4 x i32> %a1) {
;CHECK-LABEL: @mul_4i32
;CHECK: # BB#0:
;CHECK-NEXT: pmulld %xmm1, %xmm0
- ;CHECK-NEXT: pmulld .LCPI1_0(%rip), %xmm0
+ ;CHECK-NEXT: pmulld .LCPI2_0(%rip), %xmm0
;CHECK-NEXT: retq
%1 = mul <4 x i32> %a0, <i32 1, i32 2, i32 3, i32 4>
%2 = mul <4 x i32> %a1, <i32 4, i32 3, i32 2, i32 1>
@@ -23,11 +34,23 @@ define <4 x i32> @mul_4i32(<4 x i32> %a0
ret <4 x i32> %3
}
+define <4 x i32> @mul_4i32_commute(<4 x i32> %a0, <4 x i32> %a1) {
+ ;CHECK-LABEL: @mul_4i32_commute
+ ;CHECK: # BB#0:
+ ;CHECK-NEXT: pmulld %xmm1, %xmm0
+ ;CHECK-NEXT: pmulld .LCPI3_0(%rip), %xmm0
+ ;CHECK-NEXT: retq
+ %1 = mul <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %a0
+ %2 = mul <4 x i32> <i32 4, i32 3, i32 2, i32 1>, %a1
+ %3 = mul <4 x i32> %1, %2
+ ret <4 x i32> %3
+}
+
define <4 x i32> @and_4i32(<4 x i32> %a0, <4 x i32> %a1) {
;CHECK-LABEL: @and_4i32
;CHECK: # BB#0:
;CHECK-NEXT: andps %xmm1, %xmm0
- ;CHECK-NEXT: andps .LCPI2_0(%rip), %xmm0
+ ;CHECK-NEXT: andps .LCPI4_0(%rip), %xmm0
;CHECK-NEXT: retq
%1 = and <4 x i32> %a0, <i32 -2, i32 -2, i32 3, i32 3>
%2 = and <4 x i32> %a1, <i32 -1, i32 -1, i32 1, i32 1>
@@ -35,11 +58,23 @@ define <4 x i32> @and_4i32(<4 x i32> %a0
ret <4 x i32> %3
}
+define <4 x i32> @and_4i32_commute(<4 x i32> %a0, <4 x i32> %a1) {
+ ;CHECK-LABEL: @and_4i32_commute
+ ;CHECK: # BB#0:
+ ;CHECK-NEXT: andps %xmm1, %xmm0
+ ;CHECK-NEXT: andps .LCPI5_0(%rip), %xmm0
+ ;CHECK-NEXT: retq
+ %1 = and <4 x i32> <i32 -2, i32 -2, i32 3, i32 3>, %a0
+ %2 = and <4 x i32> <i32 -1, i32 -1, i32 1, i32 1>, %a1
+ %3 = and <4 x i32> %1, %2
+ ret <4 x i32> %3
+}
+
define <4 x i32> @or_4i32(<4 x i32> %a0, <4 x i32> %a1) {
;CHECK-LABEL: @or_4i32
;CHECK: # BB#0:
;CHECK-NEXT: orps %xmm1, %xmm0
- ;CHECK-NEXT: orps .LCPI3_0(%rip), %xmm0
+ ;CHECK-NEXT: orps .LCPI6_0(%rip), %xmm0
;CHECK-NEXT: retq
%1 = or <4 x i32> %a0, <i32 -2, i32 -2, i32 3, i32 3>
%2 = or <4 x i32> %a1, <i32 -1, i32 -1, i32 1, i32 1>
@@ -47,14 +82,38 @@ define <4 x i32> @or_4i32(<4 x i32> %a0,
ret <4 x i32> %3
}
+define <4 x i32> @or_4i32_commute(<4 x i32> %a0, <4 x i32> %a1) {
+ ;CHECK-LABEL: @or_4i32_commute
+ ;CHECK: # BB#0:
+ ;CHECK-NEXT: orps %xmm1, %xmm0
+ ;CHECK-NEXT: orps .LCPI7_0(%rip), %xmm0
+ ;CHECK-NEXT: retq
+ %1 = or <4 x i32> <i32 -2, i32 -2, i32 3, i32 3>, %a0
+ %2 = or <4 x i32> <i32 -1, i32 -1, i32 1, i32 1>, %a1
+ %3 = or <4 x i32> %1, %2
+ ret <4 x i32> %3
+}
+
define <4 x i32> @xor_4i32(<4 x i32> %a0, <4 x i32> %a1) {
;CHECK-LABEL: @xor_4i32
;CHECK: # BB#0:
;CHECK-NEXT: xorps %xmm1, %xmm0
- ;CHECK-NEXT: xorps .LCPI4_0(%rip), %xmm0
+ ;CHECK-NEXT: xorps .LCPI8_0(%rip), %xmm0
;CHECK-NEXT: retq
%1 = xor <4 x i32> %a0, <i32 -2, i32 -2, i32 3, i32 3>
%2 = xor <4 x i32> %a1, <i32 -1, i32 -1, i32 1, i32 1>
%3 = xor <4 x i32> %1, %2
ret <4 x i32> %3
}
+
+define <4 x i32> @xor_4i32_commute(<4 x i32> %a0, <4 x i32> %a1) {
+ ;CHECK-LABEL: @xor_4i32_commute
+ ;CHECK: # BB#0:
+ ;CHECK-NEXT: xorps %xmm1, %xmm0
+ ;CHECK-NEXT: xorps .LCPI9_0(%rip), %xmm0
+ ;CHECK-NEXT: retq
+ %1 = xor <4 x i32> <i32 -2, i32 -2, i32 3, i32 3>, %a0
+ %2 = xor <4 x i32> <i32 -1, i32 -1, i32 1, i32 1>, %a1
+ %3 = xor <4 x i32> %1, %2
+ ret <4 x i32> %3
+}
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