[llvm] r233936 - [AArch64] Add a comment to make it explicit why we increased the complexity.

[Quentin Colombet]

Author: qcolombet
Date: Thu Apr  2 13:54:23 2015
New Revision: 233936

URL: http://llvm.org/viewvc/llvm-project?rev=233936&view=rev
Log:
[AArch64] Add a comment to make it explicit why we increased the complexity.
Follow-up of r233653.

Modified:
    llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td

Modified: llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td?rev=233936&r1=233935&r2=233936&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td Thu Apr  2 13:54:23 2015
@@ -1637,6 +1637,10 @@ multiclass AddSub<bit isSub, string mnem
                   SDPatternOperator OpNode = null_frag> {
   let hasSideEffects = 0, isReMaterializable = 1, isAsCheapAsAMove = 1 in {
   // Add/Subtract immediate
+  // Increase the weight of the immediate variant to try to match it before
+  // the extended register variant.
+  // We used to match the register variant before the immediate when the
+  // register argument could be implicitly zero-extended.
   let AddedComplexity = 6 in
   def Wri  : BaseAddSubImm<isSub, 0, GPR32sp, GPR32sp, addsub_shifted_imm32,
                            mnemonic, OpNode> {