[llvm] r233832 - [X86] Don't accidentally select shll $1, %eax when shrinking an immediate.

[Rafael Espíndola]

Thanks!

On 1 April 2015 at 15:01, Benjamin Kramer <benny.kra at googlemail.com> wrote:
> Author: d0k
> Date: Wed Apr  1 14:01:09 2015
> New Revision: 233832
>
> URL: http://llvm.org/viewvc/llvm-project?rev=233832&view=rev
> Log:
> [X86] Don't accidentally select shll $1, %eax when shrinking an immediate.
>
> addl has higher throughput and this was needlessly picking a suboptimal
> encoding causing PR23098.
>
> I wish there was a way of doing this without further duplicating tbl-
> generated patterns, but so far I haven't found one.
>
> Modified:
>     llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
>     llvm/trunk/test/CodeGen/X86/narrow-shl-cst.ll
>
> Modified: llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp?rev=233832&r1=233831&r2=233832&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp Wed Apr  1 14:01:09 2015
> @@ -2187,7 +2187,7 @@ SDNode *X86DAGToDAGISel::Select(SDNode *
>      if (Opcode != ISD::AND && (Val & RemovedBitsMask) != 0)
>        break;
>
> -    unsigned ShlOp, Op;
> +    unsigned ShlOp, AddOp, Op;
>      MVT CstVT = NVT;
>
>      // Check the minimum bitwidth for the new constant.
> @@ -2208,6 +2208,7 @@ SDNode *X86DAGToDAGISel::Select(SDNode *
>      case MVT::i32:
>        assert(CstVT == MVT::i8);
>        ShlOp = X86::SHL32ri;
> +      AddOp = X86::ADD32rr;
>
>        switch (Opcode) {
>        default: llvm_unreachable("Impossible opcode");
> @@ -2219,6 +2220,7 @@ SDNode *X86DAGToDAGISel::Select(SDNode *
>      case MVT::i64:
>        assert(CstVT == MVT::i8 || CstVT == MVT::i32);
>        ShlOp = X86::SHL64ri;
> +      AddOp = X86::ADD64rr;
>
>        switch (Opcode) {
>        default: llvm_unreachable("Impossible opcode");
> @@ -2232,6 +2234,9 @@ SDNode *X86DAGToDAGISel::Select(SDNode *
>      // Emit the smaller op and the shift.
>      SDValue NewCst = CurDAG->getTargetConstant(Val >> ShlVal, CstVT);
>      SDNode *New = CurDAG->getMachineNode(Op, dl, NVT, N0->getOperand(0),NewCst);
> +    if (ShlVal == 1)
> +      return CurDAG->SelectNodeTo(Node, AddOp, NVT, SDValue(New, 0),
> +                                  SDValue(New, 0));
>      return CurDAG->SelectNodeTo(Node, ShlOp, NVT, SDValue(New, 0),
>                                  getI8Imm(ShlVal));
>    }
>
> Modified: llvm/trunk/test/CodeGen/X86/narrow-shl-cst.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/narrow-shl-cst.ll?rev=233832&r1=233831&r2=233832&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/X86/narrow-shl-cst.ll (original)
> +++ llvm/trunk/test/CodeGen/X86/narrow-shl-cst.ll Wed Apr  1 14:01:09 2015
> @@ -99,3 +99,26 @@ define i64 @test11(i64 %x) nounwind {
>  ; CHECK: xorq $-65536
>  ; CHECK: shlq $33
>  }
> +
> +; PR23098
> +define i32 @test12(i32 %x, i32* %y) nounwind {
> +  %and = shl i32 %x, 1
> +  %shl = and i32 %and, 255
> +  store i32 %shl, i32* %y
> +  ret i32 %shl
> +; CHECK-LABEL: test12:
> +; CHECK: andl $127
> +; CHECK-NEXT: addl
> +; CHECK-NOT: shl
> +}
> +
> +define i64 @test13(i64 %x, i64* %y) nounwind {
> +  %and = shl i64 %x, 1
> +  %shl = and i64 %and, 255
> +  store i64 %shl, i64* %y
> +  ret i64 %shl
> +; CHECK-LABEL: test13:
> +; CHECK: andq $127
> +; CHECK-NEXT: addq
> +; CHECK-NOT: shl
> +}
>
>
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