[PATCH] [DAGCombiner] Combine shuffles of BUILD_VECTOR and SCALAR_TO_VECTOR

[Sanjay Patel]

REPOSITORY
  rL LLVM

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Comment at: test/CodeGen/X86/mmx-bitcast.ll:78
@@ +77,3 @@
+; CHECK-NEXT:    punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
+; CHECK-NEXT:    movd %xmm1, %rax
+; CHECK-NEXT:    retq
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andreadb wrote:
> RKSimon wrote:
> > RKSimon wrote:
> > > andreadb wrote:
> > > > I don't think this is related to your patch. However, this looks like a bug to me. Shouldn't this be a 'movq'?
> > > movd deals with 32 and 64-bit gprs <-> vector moves. movq does vector load/stores and vector <-> vector moves. Its a funny old world.
> > Actually scrub that - this does appear to be a bug. Its is a (v)movq instruction - but encoded similar to the (v)movd and completely separate to the (v)movq vector version.
> Anyway, this problem is not related to your patch. In case, you can raise a bug for it.
I had a similar question in:
http://reviews.llvm.org/D8691

Looks like some weirdness due to opcode prefixes; one of the movq versions won't work on a 64-bit system.

http://reviews.llvm.org/D8516

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