[llvm] r233666 - [bpf] mark mov instructions as ReMaterializable

Alexei Starovoitov alexei.starovoitov at gmail.com
Mon Mar 30 19:49:58 PDT 2015


Author: ast
Date: Mon Mar 30 21:49:58 2015
New Revision: 233666

URL: http://llvm.org/viewvc/llvm-project?rev=233666&view=rev
Log:
[bpf] mark mov instructions as ReMaterializable

loading immediate into register is cheap, so take advantage of remat.

Modified:
    llvm/trunk/lib/Target/BPF/BPFInstrInfo.td
    llvm/trunk/test/CodeGen/BPF/basictest.ll

Modified: llvm/trunk/lib/Target/BPF/BPFInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/BPF/BPFInstrInfo.td?rev=233666&r1=233665&r2=233666&view=diff
==============================================================================
--- llvm/trunk/lib/Target/BPF/BPFInstrInfo.td (original)
+++ llvm/trunk/lib/Target/BPF/BPFInstrInfo.td Mon Mar 30 21:49:58 2015
@@ -231,8 +231,6 @@ class MOV_RI<string OpcodeStr>
   let BPFSrc = 0;   // BPF_K
   let BPFClass = 7; // BPF_ALU64
 }
-def MOV_rr : MOV_RR<"mov">;
-def MOV_ri : MOV_RI<"mov">;
 
 class LD_IMM64<bits<4> Pseudo, string OpcodeStr>
     : InstBPF<(outs GPR:$dst), (ins u64imm:$imm),
@@ -255,7 +253,12 @@ class LD_IMM64<bits<4> Pseudo, string Op
   let size = 3;     // BPF_DW
   let BPFClass = 0; // BPF_LD
 }
+
+let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
 def LD_imm64 : LD_IMM64<0, "ld_64">;
+def MOV_rr : MOV_RR<"mov">;
+def MOV_ri : MOV_RI<"mov">;
+}
 
 def LD_pseudo
     : InstBPF<(outs GPR:$dst), (ins i64imm:$pseudo, u64imm:$imm),

Modified: llvm/trunk/test/CodeGen/BPF/basictest.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/BPF/basictest.ll?rev=233666&r1=233665&r2=233666&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/BPF/basictest.ll (original)
+++ llvm/trunk/test/CodeGen/BPF/basictest.ll Mon Mar 30 21:49:58 2015
@@ -8,8 +8,8 @@ define i32 @test0(i32 %X) {
 }
 
 ; CHECK-LABEL: store_imm:
-; CHECK: stw  0(r1), r0
-; CHECK: stw  4(r2), r0
+; CHECK: stw  0(r1), r{{[03]}}
+; CHECK: stw  4(r2), r{{[03]}}
 define i32 @store_imm(i32* %a, i32* %b) {
 entry:
   store i32 0, i32* %a, align 4





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