[PATCH] [PPC64LE] Remove unnecessary swaps from lane-insensitive vector computations

[Bill Schmidt]

In http://reviews.llvm.org/D8565#149183, @chandlerc wrote:

> I'd like to understand why you opted for doing this in MI instead of at the IR level? In particular, it seems odd to have the loop vectorizer and other tools build vectorized code in the "wrong" way and then fix it if we can later.


The extra swap instructions are not introduced until instruction selection, so the IR level is already correct.  The instruction selector is too myopic to view entire computation webs, so we have to be conservative and generate code that uses true-LE register representations, then clean up at a later time when we can see the big picture.  (So both the disease and the cure are introduced in the back end.)


REPOSITORY
  rL LLVM

http://reviews.llvm.org/D8565

EMAIL PREFERENCES
  http://reviews.llvm.org/settings/panel/emailpreferences/