[PATCH] [AArch64] Add v8.1a atomic instructions

[Vladimir Sukharev]

REPOSITORY
  rL LLVM

================
Comment at: lib/Target/AArch64/AArch64InstrFormats.td:8731-8732
@@ +8730,4 @@
+
+multiclass BaseAliasLDOp<string asm> {
+  def : BaseAliasLD<"st" # asm # "lb", GPR32, WZR, !cast<Instruction>("LD" # _B_release_ # asm)>;
+  def : BaseAliasLD<"st" # asm # "lh", GPR32, WZR, !cast<Instruction>("LD" # _H_release_ # asm)>;
----------------
t.p.northover wrote:
> It's also rather odd that the "BaseAliasLD" classes actually define mnemonics starting with "st".
I'd wish instructions would be better named as "LDST<op>" and "ST<op>"....
That way it semantics be clear, so ST just doesn't save loaded value in reg

================
Comment at: lib/Target/AArch64/AArch64InstrFormats.td:8767
@@ +8766,3 @@
+
+multiclass STOPregister<string asm, string instr> {
+  def : BaseSTOPregister<asm # "lb", GPR32, WZR, 
----------------
I'd wish instructions would be better named as "LDST<op>" and "ST<op>"....
That way it semantics be clear, so ST just doesn't save loaded value in reg

================
Comment at: lib/Target/AArch64/AArch64RegisterInfo.td:608-609
@@ +607,4 @@
+
+def Pair32 : RegisterTuples<[sube32, subo32], [(rotl GPR32, 0), (rotl GPR32, 1)]>;
+def Pair64 : RegisterTuples<[sube64, subo64], [(rotl GPR64, 0), (rotl GPR64, 1)]>;
+
----------------
t.p.northover wrote:
> We should probably mention GPRPair here, for readability in "-debug" if nothing else. (Elsewhere too, just because there are no FPRPairs now, doesn't mean there won't be in future).
I'm gonna rename it to WSeqPairs and XSeqPairs, similar to existing DSeqPairs and QSeqPairs

================
Comment at: lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp:4331
@@ +4330,3 @@
+       isWReg = WRegClass.contains(FirstReg);
+  if (!isXReg && !isWReg) {
+    Error(S, "expected register");
----------------
About top-level template "tryParseGPRSeqPair<>"  and generic function:
hmmm, is there a way for AArch64AsmParser (methods MatchOperandParserImpl and tryCustomParseOperand in AArch64GenAsmMatcher.inc) to guess in advance which pair to expect - MCK_WSeqPair or MCK_XSeqPair?

I guess without that knowledge it is possible only to call this generic tryParseGPRSeqPair from tryCustomParseOperand, and it will find out the size of actual operands.
I've just tried to use a template and face only tryParseGPRSeqPair<32>() is being called for both test lines, and 64-bit variant is never called, 
```
 //CASP instruction
 casp x0, x1, x2, x3, [x4]
 casp w0, w1, w2, w3, [x4]
```

================
Comment at: lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp:4361
@@ +4360,3 @@
+      (isWReg && !WRegClass.contains(SecondReg))) {
+    Error(E,"expected consecutive registers of same size");
+    return MatchOperand_ParseFail;
----------------
No paranoia, second complicated check is needed against pairs like "w0, x1", I've added some tests for that, like
```
//CHECK-ERROR: error: expected consecutive registers of same size
//CHECK-ERROR: casp w0, x1, x2, x3, [x5]
```

================
Comment at: lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp:4372
@@ +4371,3 @@
+           &AArch64MCRegisterClasses[AArch64::WSeqPairsClassRegClassID]);
+  }
+
----------------
Introduced usage of AArch64MCRegisterClasses causes the need of explicit dependency AArch64Info -> AArch64Desc
Without this change, linker issues an error in shared library mode:
llvm::AArch64MCRegisterClasses could not be found in AArch64Disassembler.cpp:1558 and 1571

================
Comment at: lib/Target/AArch64/Disassembler/LLVMBuild.txt:22
@@ -21,3 +21,3 @@
 parent = AArch64
-required_libraries = AArch64Info AArch64Utils MC MCDisassembler Support
+required_libraries = AArch64Desc AArch64Info AArch64Utils MC MCDisassembler Support
 add_to_library_groups = AArch64
----------------
Introduced usage of AArch64MCRegisterClasses causes the need of explicit dependency AArch64Info -> AArch64Desc
Without this change, linker issues an error in shared library mode:
llvm::AArch64MCRegisterClasses could not be found in AArch64Disassembler.cpp:1558 and 1571

http://reviews.llvm.org/D8501

EMAIL PREFERENCES
  http://reviews.llvm.org/settings/panel/emailpreferences/