[PATCH] RegAllocGreedy: Improve live interval order in ReverseLocal mode

[Andrew Trick]

> On Mar 26, 2015, at 9:58 AM, Andrew Trick <atrick at apple.com> wrote:
> 
>> 
>> On Mar 25, 2015, at 8:01 PM, Matthias Braun <matze at braunis.de> wrote:
>> 
>> Hi qcolombet, atrick,
>> 
>> When allocating live intervals in linear order and all of them are local
>> to a single basic block you get an optimal coloring. This is also true
>> if you reverse the order, but it is not true if you sort live ranges
>> beginnings in reverse order, change to sort live range endings in
>> reverse order. Take the following live ranges for example:
>> 
>>  |---| |--------|
>> |----------| |-------|
>> 
>> They get colored suboptimally with 3 registers if you sort the live range
>> starting points in reverse order (but optimally with live range begins in order,
>> or live range ends in reverse order).
> 
> You’re absolutely right. The code as-is was intentional though, and known not to give optimal colorings. That heuristic is not about coloring but about compile time as the comment above attempts to explain.

That said, it would be really great to remove that hack, as long as you also change the comments to reflect your change and have data on large-register-file targets. I initially wanted optimal coloring for all local allocation but ran into a few regressions that we didn’t want to live with at the time

(1) forward-order resulted in at least one compile time issue where we assign a large number of physical registers right away for loads, then repeatedly check interferences on all of them. I think your data is more up-to-date and complete so hopefully you can remove that workaround now.

(2) On “normal” targets, for very large blocks, we were not spilling effectively. Hence the ForceGlobal heuristic threshold.

Andy

>> No testcase as none of the (in tree) targets use reverse order mode.
>> 
>> http://reviews.llvm.org/D8625
>> 
>> Files:
>> lib/CodeGen/RegAllocGreedy.cpp
>> 
>> Index: lib/CodeGen/RegAllocGreedy.cpp
>> ===================================================================
>> --- lib/CodeGen/RegAllocGreedy.cpp
>> +++ lib/CodeGen/RegAllocGreedy.cpp
>> @@ -552,7 +552,7 @@
>>        // Allocating bottom up may allow many short LRGs to be assigned first
>>        // to one of the cheap registers. This could be much faster for very
>>        // large blocks on targets with many physical registers.
>> -        Prio = Indexes->getZeroIndex().getInstrDistance(LI->beginIndex());
>> +        Prio = Indexes->getZeroIndex().getInstrDistance(LI->endIndex());
>>      }
>>    }
>>    else {
>> 
>> EMAIL PREFERENCES
>> http://reviews.llvm.org/settings/panel/emailpreferences/
>> <D8625.22695.patch>
> 
> 
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