[PATCH] Add LLVM support for remaining integer divide and permute instructions from ISA 2.06

[Bill Schmidt]

REPOSITORY
  rL LLVM

================
Comment at: lib/Target/PowerPC/PPC.td:163
@@ +162,3 @@
+def ProcessorFeatures {
+  list<SubtargetFeature> Power7FeatureList =
+      [FeatureISA206, DirectivePwr7, FeatureAltivec, FeatureVSX,
----------------
nemanjai wrote:
> hfinkel wrote:
> > wschmidt wrote:
> > > I don't care for the FeatureISA206 choice.  It contradicts the existing design (there are plenty of features called out that are also in ISA 2.06, so why is this one special?), and is redundant with Power7FeatureList (if you have a Power7FeatureList, shouldn't it just be previous features + FeatureISA206 under this philosophy?).
> > > 
> > > I think you should go back to Hal's suggestion and provide relevant features that are grouped in a reasonable way.  For this patch, that would be something like FeatureExtDiv and FeatureBitPerm.  I don't think we have a need to disrupt the existing design.
> > I agree with Bill agreeing with me ;)
> > 
> > That having been said, I would like to get a better handle on the features associated with ISA revisions, and group those together. So please add fine-grained features (for one thing, we'll likely have CodeGen support for these at some point, at least bpermd). As a separate change, we can add feature groups for the ISA revisions, and then use those to define the default sets of features for the processors defined.
> > 
> OK, so to summarize:
> - In this patch, add fine-grained control for the instructions that are implemented (I will add FeatureExtDiv and FeatureBitPerm - should I add a "d" at the end of that?)
> - In a future patch, provide something along the lines of these feature groups (FeatureISA206 in this case)
You can add a "D" if you like; I don't care either way.  It protects against a future feature that does bit permute on another data type, I suppose.

http://reviews.llvm.org/D8406

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