[PATCH] [aarch64] Distinguish the 'Q' and 'm' inline assembly memory constraints.

[Daniel Sanders]

REPOSITORY
  rL LLVM

http://reviews.llvm.org/D8177

Files:
  llvm/trunk/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
  llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.h

Index: llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.h
===================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.h
+++ llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.h
@@ -475,8 +475,12 @@
 
   unsigned getInlineAsmMemConstraint(
       const std::string &ConstraintCode) const override {
-    // FIXME: Map different constraints differently.
-    return InlineAsm::Constraint_m;
+    if (ConstraintCode == "Q")
+      return InlineAsm::Constraint_Q;
+    // FIXME: clang has code for 'Ump', 'Utf', 'Usa', and 'Ush' but these are
+    //        followed by llvm_unreachable so we'll leave them unimplemented in
+    //        the backend for now.
+    return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
   }
 
   bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
Index: llvm/trunk/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
===================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
+++ llvm/trunk/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
@@ -212,13 +212,19 @@
 
 bool AArch64DAGToDAGISel::SelectInlineAsmMemoryOperand(
     const SDValue &Op, unsigned ConstraintID, std::vector<SDValue> &OutOps) {
-  assert(ConstraintID == InlineAsm::Constraint_m &&
-         "unexpected asm memory constraint");
-  // Require the address to be in a register.  That is safe for all AArch64
-  // variants and it is hard to do anything much smarter without knowing
-  // how the operand is used.
-  OutOps.push_back(Op);
-  return false;
+  switch(ConstraintID) {
+  default:
+    llvm_unreachable("Unexpected asm memory constraint");
+  case InlineAsm::Constraint_i:
+  case InlineAsm::Constraint_m:
+  case InlineAsm::Constraint_Q:
+    // Require the address to be in a register.  That is safe for all AArch64
+    // variants and it is hard to do anything much smarter without knowing
+    // how the operand is used.
+    OutOps.push_back(Op);
+    return false;
+  }
+  return true;
 }
 
 /// SelectArithImmed - Select an immediate value that can be represented as

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