[PATCH] [AArch64] enable rematerialization of float 0 values

[Geoff Berry]

Hi Tim,

Thanks for the feedback, I've incorporated your suggestions.

I'm working on a test case, but I'm having trouble creating a FMOV 0 live range in IR that lives across a point in the code where I can insert inline asm to force it to be spilled.
If I try using a phi(0.0, x) to create the live range, the problem is I can't insert the inline asm to force a spill between the phi and the end of the predecessor where the COPY will be inserted.

Do you have any other ideas for generating a FMOV 0 that I can force to be spilled?


--
Geoff Berry
Employee of Qualcomm Innovation Center, Inc.
 Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project

-----Original Message-----
From: Tim Northover [mailto:t.p.northover at gmail.com] 
Sent: Friday, March 20, 2015 2:30 PM
To: Geoff Berry
Cc: Matthias Braun; LLVM Commits
Subject: Re: [PATCH] [AArch64] enable rematerialization of float 0 values

Hi Geoff,

> -def : Pat<(f32 (fpimm0)), (FMOVWSr WZR)>, Requires<[NoZCZ]>; -def :
> Pat<(f64 (fpimm0)), (FMOVXDr XZR)>, Requires<[NoZCZ]>;
> +// Add separate opcode for FMOV 0 so we can mark it as 
> +isReMaterializable let isReMaterializable = 1, isCodeGenOnly = 1 in 
> +defm FMOV0 : UnscaledConversion<"fmov">;
> +
> +def : Pat<(f32 (fpimm0)), (FMOV0WSr WZR)>, Requires<[NoZCZ]>; def :
> +Pat<(f64 (fpimm0)), (FMOV0XDr XZR)>, Requires<[NoZCZ]>;

The idea of a more targeted pseudo-instruction is probably a good one.
But that particular implementation creates loads of heavy-weight Pseudo-instructions (encoding info, asm info, ...), most of which are never used.

I'd suggest something along the lines of:

let isReMaterializable = 1, isCodeGenOnly = 1 in {

def FMOVS0: Pseudo<(outs FPR32:$Rd), (ins), [(set f32:$Rd, (fpimm0))]>,
      PseudoInstExpansion<(FMOVWSr FPR32:$Rd, WZR)>,
      Requires<[NoZCZ]>;

<similar FMOVD0>
}

Also, there's still no test.

Cheers.

Tim.