[PATCH] Use movw/movt instead of constant pool loads to lower byval parameter copies

[Tim Northover]

Couple of minor points:


================
Comment at: lib/Target/ARM/ARMISelLowering.cpp:7143
@@ -7142,3 +7142,3 @@
   unsigned varEnd = MRI.createVirtualRegister(TRC);
-  if (IsThumb2) {
+  if (IsThumb2 || Subtarget->useMovt(*MF)) {
     unsigned Vtmp = varEnd;
----------------
Couldn't this be simplified to just Subtarget->useMovt(*MF)?

================
Comment at: test/CodeGen/ARM/struct_byval.ll:6
@@ +5,3 @@
+; RUN: llc < %s -mtriple=armv7-unknown-nacl-gnueabi | FileCheck %s -check-prefix=NACL
+; NACL-NOT: .LCPI
+
----------------
Not tests like this are a bit sketchy. There's a massive range of incorrect behaviour that could be produced but get past. Especially as you've actually added ARM code, I think you should be testing that's correct.

It'd also be good to make sure we don't try to produce movw/movt on CPUs that don't actually have them. That's surprisingly easy to do with C++ code manually using BuildMI.

http://reviews.llvm.org/D8442

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