[PATCH] Add LLVM support for remaining integer divide and permute instructions from ISA 2.06

[hfinkel at anl.gov]

REPOSITORY
  rL LLVM

================
Comment at: lib/Target/PowerPC/PPCSubtarget.cpp:148
@@ +147,3 @@
+  IsPwr8Up = CPUName == "ppc64le" || CPUName == "pwr8";
+  IsPwr7Up = CPUName == "pwr7" || IsPwr8Up;
+  IsISA206Up = IsPwr7Up;
----------------
nemanjai wrote:
> hfinkel wrote:
> > No... target features in PPC.td please.
> > 
> In response to this comment and the one about the predicate...
> 
> The brief history of this design decision is that target features have a limitation. Namely, the target is limited to 64 of them. Now I haven't come across any fundamental reason for this, it is just that tblgen does not handle any more. The reason it doesn't is that in the generated code, each feature is a uint64_t entity that is 1 left-shifted by n (where n is the feature's zero-based ordinal number). At my last check, we were at around 58 features. So I did this to avoid blowing past the 64 feature limit for things that can easily be encoded in the C++ portion.
> If everyone agrees that target features are the way to go and we don't want to worry about defining too many of these features, I'll be happy to change it.
Don't worry about it. Other targets are also running up against this limit, and there is a patchset under review to increase it.

http://reviews.llvm.org/D8406

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