[PATCH] Add LLVM support for remaining integer divide and permute instructions from ISA 2.06
hfinkel at anl.gov
hfinkel at anl.gov
Wed Mar 18 13:46:10 PDT 2015
REPOSITORY
rL LLVM
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Comment at: lib/Target/PowerPC/PPCInstrInfo.td:717
@@ -716,1 +716,3 @@
def NaNsFPMath : Predicate<"!TM.Options.NoNaNsFPMath">;
+def IsPwr7Up : Predicate<"PPCSubTarget->isPwr7Up()">;
+def IsPwr8Up : Predicate<"PPCSubTarget->isPwr8Up()">;
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wschmidt wrote:
> I'm a tiny bit not enthused about the name -- IsPwr7OrHigher, perhaps? Pwr7Up sounds like an energy drink. ;) If nobody else dislikes it, leave it as is, though.
So true ;) -- Yea, I don't like it either.
Just make a target feature, and name it after some characteristic instruction. HasDIVDE perhaps?
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Comment at: lib/Target/PowerPC/PPCSubtarget.cpp:148
@@ +147,3 @@
+ IsPwr8Up = CPUName == "ppc64le" || CPUName == "pwr8";
+ IsPwr7Up = CPUName == "pwr7" || IsPwr8Up;
+ IsISA206Up = IsPwr7Up;
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No... target features in PPC.td please.
http://reviews.llvm.org/D8406
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