[PATCH] Add LLVM support for remaining integer divide and permute instructions from ISA 2.06

[Nemanja Ivanovic]

Hi hfinkel, wschmidt, kbarton, echristo,

This is the back end portion of Review D8398. Similarly to the front end, the back end got flags for checking if the target implements ISA 2.06 and up (and whether it is a Power7 and up CPU), etc.

The integer divide instructions that were already implemented were changed slightly since both the record form and the non-record form were specified as "First" and "Cracked". However, Book IV states that the non-record forms are not cracked. So I have changed the multiclass to specify this.
Finally, the record form instructions are implemented only for [inline] assembly and no builtins were provided. This is consistent with GCC. As noted in the front end review, the -mpopcntd option has no effect on these (in contrast with GCC).

REPOSITORY
  rL LLVM

http://reviews.llvm.org/D8406

Files:
  include/llvm/IR/IntrinsicsPowerPC.td
  lib/Target/PowerPC/PPCInstr64Bit.td
  lib/Target/PowerPC/PPCInstrInfo.td
  lib/Target/PowerPC/PPCSubtarget.cpp
  lib/Target/PowerPC/PPCSubtarget.h
  lib/Target/PowerPC/README.txt
  test/CodeGen/PowerPC/div-e-32.ll
  test/CodeGen/PowerPC/div-e-all.ll
  test/MC/Disassembler/PowerPC/ppc64-encoding.txt
  test/MC/PowerPC/ppc64-encoding.s

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