[PATCH] Fix bug while building FP16 constant vectors for AArch64

[Pirama Arumuga Nainar]

REPOSITORY
  rL LLVM

http://reviews.llvm.org/D8369

Files:
  llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/trunk/test/CodeGen/AArch64/fp16-v4-instructions.ll

Index: llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp
===================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -5892,8 +5892,10 @@
 
     if (VT.getVectorElementType().isFloatingPoint()) {
       SmallVector<SDValue, 8> Ops;
-      MVT NewType =
-          (VT.getVectorElementType() == MVT::f32) ? MVT::i32 : MVT::i64;
+      EVT EltTy = VT.getVectorElementType();
+      assert ((EltTy == MVT::f16 || EltTy == MVT::f32 || EltTy == MVT::f64) &&
+              "Unsupported floating-point vector type");
+      MVT NewType = MVT::getIntegerVT(EltTy.getSizeInBits());
       for (unsigned i = 0; i < NumElts; ++i)
         Ops.push_back(DAG.getNode(ISD::BITCAST, dl, NewType, Op.getOperand(i)));
       EVT VecVT = EVT::getVectorVT(*DAG.getContext(), NewType, NumElts);
Index: llvm/trunk/test/CodeGen/AArch64/fp16-v4-instructions.ll
===================================================================
--- llvm/trunk/test/CodeGen/AArch64/fp16-v4-instructions.ll
+++ llvm/trunk/test/CodeGen/AArch64/fp16-v4-instructions.ll
@@ -12,6 +12,15 @@
 }
 
 
+define <4 x half> @build_h4(<4 x half> %a) {
+entry:
+; CHECK-LABEL: build_h4:
+; CHECK: movz [[GPR:w[0-9]+]], #0x3ccd
+; CHECK: dup v0.4h, [[GPR]]
+  ret <4 x half> <half 0xH3CCD, half 0xH3CCD, half 0xH3CCD, half 0xH3CCD>
+}
+
+
 define <4 x half> @sub_h(<4 x half> %a, <4 x half> %b) {
 entry:
 ; CHECK-LABEL: sub_h:

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