[llvm] r232480 - Re-commit: [hexagon] Distinguish the 'o', 'v', and 'm' inline assembly memory constraints.

[Daniel Sanders]

Author: dsanders
Date: Tue Mar 17 09:37:39 2015
New Revision: 232480

URL: http://llvm.org/viewvc/llvm-project?rev=232480&view=rev
Log:
Re-commit: [hexagon] Distinguish the 'o', 'v', and 'm' inline assembly memory constraints.

Summary:
But still handle them the same way since I don't know how they differ on
this target.

No functional change intended.

Reviewers: kparzysz, adasgupt

Reviewed By: kparzysz, adasgupt

Subscribers: colinl, llvm-commits

Differential Revision: http://reviews.llvm.org/D8204

Like for the PowerPC target, I've had to add 'i' to the constraint mappings in
order to pass 2007-12-17-InvokeAsm.ll. It's not clear why 'i' has historically
been treated as a memory constraint.


Modified:
    llvm/trunk/include/llvm/IR/InlineAsm.h
    llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
    llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.h

Modified: llvm/trunk/include/llvm/IR/InlineAsm.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IR/InlineAsm.h?rev=232480&r1=232479&r2=232480&view=diff
==============================================================================
--- llvm/trunk/include/llvm/IR/InlineAsm.h (original)
+++ llvm/trunk/include/llvm/IR/InlineAsm.h Tue Mar 17 09:37:39 2015
@@ -243,7 +243,7 @@ public:
     Constraint_i,
     Constraint_m,
     Constraint_o,
-    Constraint_v, // Unused at the moment since Constraint_m is always used.
+    Constraint_v,
     Constraint_Q,
     Constraint_Z,
     Constraint_Zy,

Modified: llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp?rev=232480&r1=232479&r2=232480&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp Tue Mar 17 09:37:39 2015
@@ -1108,11 +1108,12 @@ SelectInlineAsmMemoryOperand(const SDVal
   SDValue Inp = Op, Res;
 
   switch (ConstraintID) {
-  case InlineAsm::Constraint_o:   // Offsetable.
-  case InlineAsm::Constraint_v:   // Not offsetable.
   default:
     return true;
-  case InlineAsm::Constraint_m:   // Memory.
+  case InlineAsm::Constraint_i:
+  case InlineAsm::Constraint_o: // Offsetable.
+  case InlineAsm::Constraint_v: // Not offsetable.
+  case InlineAsm::Constraint_m: // Memory.
     if (SelectAddrFI(Inp, Res))
       OutOps.push_back(Res);
     else

Modified: llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.h?rev=232480&r1=232479&r2=232480&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.h (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.h Tue Mar 17 09:37:39 2015
@@ -185,8 +185,11 @@ bool isPositiveHalfWord(SDNode *N);
 
     unsigned getInlineAsmMemConstraint(
         const std::string &ConstraintCode) const override {
-      // FIXME: Map different constraints differently.
-      return InlineAsm::Constraint_m;
+      if (ConstraintCode == "o")
+        return InlineAsm::Constraint_o;
+      else if (ConstraintCode == "v")
+        return InlineAsm::Constraint_v;
+      return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
     }
 
     // Intrinsics