[llvm] r232473 - [mips] [IAS] Add support for the XOR $reg, imm pseudo-instruction.
Toma Tabacu
toma.tabacu at imgtec.com
Tue Mar 17 06:17:44 PDT 2015
Author: tomatabacu
Date: Tue Mar 17 08:17:44 2015
New Revision: 232473
URL: http://llvm.org/viewvc/llvm-project?rev=232473&view=rev
Log:
[mips] [IAS] Add support for the XOR $reg,imm pseudo-instruction.
Summary:
This adds a MipsInstAlias which expands to XORi $reg,$reg,imm. For example, "xor $6, 0x3A" should be expanded to "xori $6, $6, 58".
This should work for all MIPS ISAs.
Reviewers: dsanders
Reviewed By: dsanders
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D8284
Modified:
llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
llvm/trunk/test/MC/Mips/mips1/valid.s
llvm/trunk/test/MC/Mips/mips2/valid.s
llvm/trunk/test/MC/Mips/mips3/valid.s
llvm/trunk/test/MC/Mips/mips32/valid.s
llvm/trunk/test/MC/Mips/mips32r2/valid.s
llvm/trunk/test/MC/Mips/mips32r3/valid.s
llvm/trunk/test/MC/Mips/mips32r5/valid.s
llvm/trunk/test/MC/Mips/mips32r6/valid.s
llvm/trunk/test/MC/Mips/mips4/valid.s
llvm/trunk/test/MC/Mips/mips5/valid.s
llvm/trunk/test/MC/Mips/mips64/valid.s
llvm/trunk/test/MC/Mips/mips64r2/valid.s
llvm/trunk/test/MC/Mips/mips64r3/valid.s
llvm/trunk/test/MC/Mips/mips64r5/valid.s
llvm/trunk/test/MC/Mips/mips64r6/valid.s
Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=232473&r1=232472&r2=232473&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Tue Mar 17 08:17:44 2015
@@ -1580,6 +1580,8 @@ def : MipsInstAlias<"sltu $rt, $rs, $imm
(SLTiu GPR32Opnd:$rt, GPR32Opnd:$rs, simm16:$imm), 0>;
def : MipsInstAlias<"xor $rs, $rt, $imm",
(XORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
+def : MipsInstAlias<"xor $rs, $imm",
+ (XORi GPR32Opnd:$rs, GPR32Opnd:$rs, uimm16:$imm), 0>;
def : MipsInstAlias<"or $rs, $rt, $imm",
(ORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
def : MipsInstAlias<"or $rs, $imm",
Modified: llvm/trunk/test/MC/Mips/mips1/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips1/valid.s?rev=232473&r1=232472&r2=232473&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips1/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips1/valid.s Tue Mar 17 08:17:44 2015
@@ -116,3 +116,4 @@
tlbwi # CHECK: tlbwi # encoding: [0x42,0x00,0x00,0x02]
tlbwr # CHECK: tlbwr # encoding: [0x42,0x00,0x00,0x06]
xor $s2,$a0,$s8
+ xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04]
Modified: llvm/trunk/test/MC/Mips/mips2/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips2/valid.s?rev=232473&r1=232472&r2=232473&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips2/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips2/valid.s Tue Mar 17 08:17:44 2015
@@ -165,3 +165,4 @@
trunc.w.d $f22,$f15
trunc.w.s $f28,$f30
xor $s2,$a0,$s8
+ xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04]
Modified: llvm/trunk/test/MC/Mips/mips3/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips3/valid.s?rev=232473&r1=232472&r2=232473&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips3/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips3/valid.s Tue Mar 17 08:17:44 2015
@@ -228,3 +228,4 @@
trunc.w.d $f22,$f15
trunc.w.s $f28,$f30
xor $s2,$a0,$s8
+ xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04]
Modified: llvm/trunk/test/MC/Mips/mips32/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips32/valid.s?rev=232473&r1=232472&r2=232473&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips32/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips32/valid.s Tue Mar 17 08:17:44 2015
@@ -195,3 +195,4 @@
trunc.w.d $f22,$f15
trunc.w.s $f28,$f30
xor $s2,$a0,$s8
+ xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04]
Modified: llvm/trunk/test/MC/Mips/mips32r2/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips32r2/valid.s?rev=232473&r1=232472&r2=232473&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips32r2/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips32r2/valid.s Tue Mar 17 08:17:44 2015
@@ -233,4 +233,5 @@
trunc.w.s $f28,$f30
wsbh $k1,$9
xor $s2,$a0,$s8
+ xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04]
synci -15842($a2) # CHECK: synci -15842($6) # encoding: [0x04,0xdf,0xc2,0x1e]
Modified: llvm/trunk/test/MC/Mips/mips32r3/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips32r3/valid.s?rev=232473&r1=232472&r2=232473&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips32r3/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips32r3/valid.s Tue Mar 17 08:17:44 2015
@@ -233,4 +233,5 @@
trunc.w.s $f28,$f30
wsbh $k1,$9
xor $s2,$a0,$s8
+ xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04]
synci -15842($a2) # CHECK: synci -15842($6) # encoding: [0x04,0xdf,0xc2,0x1e]
Modified: llvm/trunk/test/MC/Mips/mips32r5/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips32r5/valid.s?rev=232473&r1=232472&r2=232473&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips32r5/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips32r5/valid.s Tue Mar 17 08:17:44 2015
@@ -233,4 +233,5 @@
trunc.w.s $f28,$f30
wsbh $k1,$9
xor $s2,$a0,$s8
+ xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04]
synci -15842($a2) # CHECK: synci -15842($6) # encoding: [0x04,0xdf,0xc2,0x1e]
Modified: llvm/trunk/test/MC/Mips/mips32r6/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips32r6/valid.s?rev=232473&r1=232472&r2=232473&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips32r6/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips32r6/valid.s Tue Mar 17 08:17:44 2015
@@ -175,3 +175,4 @@
tltu $16,$29,1016 # CHECK: tltu $16, $sp, 1016 # encoding: [0x02,0x1d,0xfe,0x33]
tne $6,$17 # CHECK: tne $6, $17 # encoding: [0x00,0xd1,0x00,0x36]
tne $7,$8,885 # CHECK: tne $7, $8, 885 # encoding: [0x00,0xe8,0xdd,0x76]
+ xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04]
Modified: llvm/trunk/test/MC/Mips/mips4/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips4/valid.s?rev=232473&r1=232472&r2=232473&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips4/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips4/valid.s Tue Mar 17 08:17:44 2015
@@ -257,3 +257,4 @@
trunc.w.d $f22,$f15
trunc.w.s $f28,$f30
xor $s2,$a0,$s8
+ xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04]
Modified: llvm/trunk/test/MC/Mips/mips5/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips5/valid.s?rev=232473&r1=232472&r2=232473&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips5/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips5/valid.s Tue Mar 17 08:17:44 2015
@@ -259,3 +259,4 @@
trunc.w.d $f22,$f15
trunc.w.s $f28,$f30
xor $s2,$a0,$s8
+ xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04]
Modified: llvm/trunk/test/MC/Mips/mips64/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips64/valid.s?rev=232473&r1=232472&r2=232473&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips64/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips64/valid.s Tue Mar 17 08:17:44 2015
@@ -276,3 +276,4 @@
trunc.w.d $f22,$f15
trunc.w.s $f28,$f30
xor $s2,$a0,$s8
+ xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04]
Modified: llvm/trunk/test/MC/Mips/mips64r2/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips64r2/valid.s?rev=232473&r1=232472&r2=232473&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips64r2/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips64r2/valid.s Tue Mar 17 08:17:44 2015
@@ -302,4 +302,5 @@
trunc.w.d $f22,$f15
trunc.w.s $f28,$f30
xor $s2,$a0,$s8
+ xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04]
wsbh $k1,$9
Modified: llvm/trunk/test/MC/Mips/mips64r3/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips64r3/valid.s?rev=232473&r1=232472&r2=232473&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips64r3/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips64r3/valid.s Tue Mar 17 08:17:44 2015
@@ -302,4 +302,5 @@
trunc.w.d $f22,$f15
trunc.w.s $f28,$f30
xor $s2,$a0,$s8
+ xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04]
wsbh $k1,$9
Modified: llvm/trunk/test/MC/Mips/mips64r5/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips64r5/valid.s?rev=232473&r1=232472&r2=232473&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips64r5/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips64r5/valid.s Tue Mar 17 08:17:44 2015
@@ -302,4 +302,5 @@
trunc.w.d $f22,$f15
trunc.w.s $f28,$f30
xor $s2,$a0,$s8
+ xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04]
wsbh $k1,$9
Modified: llvm/trunk/test/MC/Mips/mips64r6/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips64r6/valid.s?rev=232473&r1=232472&r2=232473&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips64r6/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips64r6/valid.s Tue Mar 17 08:17:44 2015
@@ -198,3 +198,4 @@
tltu $16,$29,1016 # CHECK: tltu $16, $sp, 1016 # encoding: [0x02,0x1d,0xfe,0x33]
tne $6,$17 # CHECK: tne $6, $17 # encoding: [0x00,0xd1,0x00,0x36]
tne $7,$8,885 # CHECK: tne $7, $8, 885 # encoding: [0x00,0xe8,0xdd,0x76]
+ xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04]
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