[llvm] r231979 - Have getCallPreservedMask and getThisCallPreservedMask take a
Eric Christopher
echristo at gmail.com
Fri Mar 13 14:58:01 PDT 2015
On Fri, Mar 13, 2015 at 2:32 PM Akira Hatanaka <ahatanak at gmail.com> wrote:
> Is this not a bug in AsmPrinter::EmitInlineAsm? If I fix it to pass the
> copy of the per-function subtarget to MCTargetAsmParser, and compile your
> example IR with llc, I don't see the error "<inline asm> instruction
> requires: NEON" anymore . Patch is attached.
>
> Ha. Missed it by -> <- much.
This seems like a reasonable patch (minus the MachineFunction stuff). Go
ahead and migrate the comment (suitably modified) for the module level
inline asm from where it was in EmitInlineAsm to the new place where you
construct it in doInitialization.
I'll try to pull out the subtarget bits from the apis leading into the
assembler and see if that's sufficient for the rest of the problems. If
not, I'll construct a few more annoying testcases - this was just one off
the top of my head.
-eric
> On Fri, Mar 13, 2015 at 1:28 PM, Eric Christopher <echristo at gmail.com>
> wrote:
>
>>
>>
>> On Fri, Mar 13, 2015 at 9:06 AM Akira Hatanaka <ahatanak at gmail.com>
>> wrote:
>>
>>> On Thu, Mar 12, 2015 at 6:27 PM, Eric Christopher <echristo at gmail.com>
>>> wrote:
>>>
>>>>
>>>>
>>>> On Thu, Mar 12, 2015 at 5:31 PM Eric Christopher <echristo at gmail.com>
>>>> wrote:
>>>>
>>>>> On Thu, Mar 12, 2015 at 5:20 PM Eric Christopher <echristo at gmail.com>
>>>>> wrote:
>>>>>
>>>>>> On Thu, Mar 12, 2015 at 5:07 PM Akira Hatanaka <ahatanak at gmail.com>
>>>>>> wrote:
>>>>>>
>>>>>>> On Wed, Mar 11, 2015 at 3:50 PM, Eric Christopher <
>>>>>>> echristo at gmail.com> wrote:
>>>>>>>
>>>>>>>> In case anyone is wondering what's going on here, the rough idea:
>>>>>>>>
>>>>>>>> TargetRegisterInfo depends on MCRegisterInfo which is not, in fact,
>>>>>>>> subtarget dependent. TargetRegisterInfo is, in general, just a bunch of
>>>>>>>> layering APIs on top of MCRegisterInfo and nearly all of them already take
>>>>>>>> a MachineFunction anyhow. Extend this slightly and just have TRI be an API
>>>>>>>> layer that's subtarget independent and we can move it to the TargetMachine
>>>>>>>> level. Prompting this is the desire to have the MC layer not be subtarget
>>>>>>>> dependent as much as possible - and not during configuration if possible.
>>>>>>>>
>>>>>>>>
>>>>>>> If MCRegisterInfo is subtarget independent, meaning you'll always
>>>>>>> get the same MCRegisterInfo object regardless of what subtarget you have as
>>>>>>> long as the target is the same, why does moving TargetRegisterInfo
>>>>>>>
>>>>>>
>>>>>> It's not making the MC layer less subtarget dependent, it's how we
>>>>>> access the MC layer. See things like LLVMTargetMachine.cpp for an
>>>>>> illustration.
>>>>>>
>>>>>>
>>>>>>> to TargetMachine make the MC layer less subtarget dependent? Also,
>>>>>>> this will make it impossible for targets to have different subclasses of
>>>>>>> TargetRegisterInfo, which might make the design less clean.
>>>>>>>
>>>>>>>
>>>>>> This is trivial to fix, you can see what I've been doing there.
>>>>>>
>>>>>>
>>>>>>> Perhaps I'm just not understanding your long term plan to fix the MC
>>>>>>> layer. Could you elaborate?
>>>>>>>
>>>>>>
>>>>>> It's not a fix for the MC layer it's a fix for the layer above it.
>>>>>> Basically right now TRI has an is-a relationship with MCRegisterInfo - it
>>>>>> should have a has-a relationship as should anything that determines overall
>>>>>> module layout. The rest of asm info depends on MCRegisterInfo and so I'm
>>>>>> moving this up because it's relatively simple to do and fixes the problem
>>>>>> without having to change the TRI->MRI relationship.
>>>>>>
>>>>>>
>>>>> To be clear here I'm not saying that this is the only way forward.
>>>>> Other options involve having the TargetMachine own a particular set of MC
>>>>> level bits that involve module writing and separate that out from the
>>>>> various subtarget specific things that asm and mcinst printing need at the
>>>>> function level. (Yes, sadly these things are different because of various
>>>>> annoyances with instruction encoding and subtargets).
>>>>>
>>>>> All of LLVMTargetMachine::addPassesToEmitFile are going to need to
>>>>> change ultimately.
>>>>>
>>>>>
>>>> I'll look more into the separation I was talking about above (is-a ->
>>>> has-a) and go a bit deeper into that before continuing with the change to
>>>> move things. That said, I'm going to leave the TRI changes I've already got
>>>> (minus the AArch64 if I decide to go otherwise) because they're pretty nice
>>>> cleanups IMO. :)
>>>>
>>>>
>>> Changing TargetRegisterInfo to own MCRegisterInfo doesn't look too
>>> complicated, if you decide to go down that route.
>>>
>>>
>> I think it's a bit more complicated than you think, but largely the churn
>> might be fun. Also, you have to figure out what does own MCRegisterInfo and
>> how that gets initialized, blah blah blah. Anyhow, still thinking a bit.
>>
>>
>>> Is this something that is needed to enable subtarget switching at the MC
>>> level or just a clean-up? I seems to me that you've already made
>>>
>>
>> The former.
>>
>>
>>> most of the necessary changes in AsmPrinter and other places to use the
>>> subtarget owned by MachineFunction rather than the one owned by
>>> TargetMachine. What else is needed to enable function multi-versioning
>>> other than initializing MachineFunction's constructor with the per-function
>>> subtarget (by calling getSubtargetImpl(const Function&)) and changing clang
>>> to embed function attributes "target-cpu" and "target-features" in the IR?
>>>
>>
>> The problem is in the actual assembler. It's checking the subtarget
>> before constructing up the backend bits. A simple testcase that should work
>> is this:
>>
>> ; ModuleID = 'new.bc'
>> target datalayout =
>> "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
>> target triple = "armv4t-apple-macosx10.4.0"
>>
>> ; Function Attrs: nounwind
>> define i32 @foo() #0 {
>> entry:
>> ret i32 0
>> }
>>
>> ; Function Attrs: nounwind
>> define i32 @bar(i32 %a) #1 {
>> entry:
>> %retval = alloca i32, align 4
>> %a.addr = alloca i32, align 4
>> store i32 %a, i32* %a.addr, align 4
>> call void asm sideeffect "vabs.s8 d16, d16", ""() #2, !srcloc !4
>> %0 = load i32, i32* %retval
>> ret i32 %0
>> }
>>
>> attributes #0 = { nounwind "less-precise-fpmad"="false"
>> "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"
>> "no-infs-fp-math"="false" "no-nans-fp-math"="false"
>> "stack-protector-buffer-size"="8" "target-cpu"="arm7tdmi"
>> "target-features"="-neon,-crypto" "unsafe-fp-math"="false"
>> "use-soft-float"="true" }
>> attributes #1 = { nounwind "less-precise-fpmad"="false"
>> "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"
>> "no-infs-fp-math"="false" "no-nans-fp-math"="false"
>> "stack-protector-buffer-size"="8" "target-cpu"="arm7tdmi"
>> "target-features"="+vfp3,+neon,-crypto" "unsafe-fp-math"="false"
>> "use-soft-float"="true" }
>> attributes #2 = { nounwind }
>>
>> !llvm.ident = !{!0, !0}
>> !llvm.module.flags = !{!1, !2, !3}
>>
>> !0 = !{!"clang version 3.7.0 (trunk 232173) (llvm/trunk 232182)"}
>> !1 = !{i32 1, !"wchar_size", i32 4}
>> !2 = !{i32 1, !"min_enum_size", i32 4}
>> !3 = !{i32 1, !"PIC Level", i32 2}
>> !4 = !{i32 26}
>>
>> where it's using the default -neon subtarget, even though the function
>> specified a +neon feature on the function.
>>
>> I.e. you can't do:
>>
>> clang file-with-neon.c -mfpu=neon -S -emit-llvm
>> clang file-with-no-neon.c -S -emit-llvm
>> llvm-link <both bc files> -o link.bc
>> clang <options without neon> link.bc
>>
>> with a file that has neon inline assembly. (Let alone anything that
>> actually wanted to codegen and then assemble I think as well, but I didn't
>> test it.).
>> Don't even get me started about replacing that neon with a nop and doing
>> pre-v6t encoding checks.
>>
>> dzur:~/tmp> cat foo.c
>> int foo (void) {
>> return 0;
>> }
>> dzur:~/tmp> cat bar.c
>> int bar (int a) {
>> asm("vabs.s8 d16, d16");
>> }
>>
>> Also, the passes being added to the pass manager as we spoke about before.
>>
>> Basically until a naked getSubtarget/getSubtargetImpl are removed we're
>> not there yet.
>>
>> -eric
>>
>>
>>>
>>> -eric
>>>>
>>>>
>>>>> -eric
>>>>>
>>>>>
>>>>>> -eric
>>>>>>
>>>>>>
>>>>>>>
>>>>>>> -eric
>>>>>>>>
>>>>>>>> On Wed, Mar 11, 2015 at 3:46 PM Eric Christopher <
>>>>>>>> echristo at gmail.com> wrote:
>>>>>>>>
>>>>>>>>> Author: echristo
>>>>>>>>> Date: Wed Mar 11 17:42:13 2015
>>>>>>>>> New Revision: 231979
>>>>>>>>>
>>>>>>>>> URL: http://llvm.org/viewvc/llvm-project?rev=231979&view=rev
>>>>>>>>> Log:
>>>>>>>>> Have getCallPreservedMask and getThisCallPreservedMask take a
>>>>>>>>> MachineFunction argument so that we can grab subtarget specific
>>>>>>>>> features off of it.
>>>>>>>>>
>>>>>>>>> Modified:
>>>>>>>>> llvm/trunk/include/llvm/Target/TargetRegisterInfo.h
>>>>>>>>> llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
>>>>>>>>> llvm/trunk/lib/Target/AArch64/AArch64FastISel.cpp
>>>>>>>>> llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp
>>>>>>>>> llvm/trunk/lib/Target/AArch64/AArch64RegisterInfo.cpp
>>>>>>>>> llvm/trunk/lib/Target/AArch64/AArch64RegisterInfo.h
>>>>>>>>> llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp
>>>>>>>>> llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h
>>>>>>>>> llvm/trunk/lib/Target/ARM/ARMFastISel.cpp
>>>>>>>>> llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
>>>>>>>>> llvm/trunk/lib/Target/Mips/MipsFastISel.cpp
>>>>>>>>> llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
>>>>>>>>> llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp
>>>>>>>>> llvm/trunk/lib/Target/Mips/MipsRegisterInfo.h
>>>>>>>>> llvm/trunk/lib/Target/PowerPC/PPCFastISel.cpp
>>>>>>>>> llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
>>>>>>>>> llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp
>>>>>>>>> llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.h
>>>>>>>>> llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp
>>>>>>>>> llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.cpp
>>>>>>>>> llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.h
>>>>>>>>> llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp
>>>>>>>>> llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.cpp
>>>>>>>>> llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.h
>>>>>>>>> llvm/trunk/lib/Target/X86/X86FastISel.cpp
>>>>>>>>> llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
>>>>>>>>> llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp
>>>>>>>>> llvm/trunk/lib/Target/X86/X86RegisterInfo.h
>>>>>>>>>
>>>>>>>>> Modified: llvm/trunk/include/llvm/Target/TargetRegisterInfo.h
>>>>>>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/
>>>>>>>>> Target/TargetRegisterInfo.h?rev=231979&r1=231978&r2=231979&v
>>>>>>>>> iew=diff
>>>>>>>>> ============================================================
>>>>>>>>> ==================
>>>>>>>>> --- llvm/trunk/include/llvm/Target/TargetRegisterInfo.h (original)
>>>>>>>>> +++ llvm/trunk/include/llvm/Target/TargetRegisterInfo.h Wed Mar
>>>>>>>>> 11 17:42:13 2015
>>>>>>>>> @@ -428,7 +428,7 @@ public:
>>>>>>>>> getCalleeSavedRegs(const MachineFunction *MF) const = 0;
>>>>>>>>>
>>>>>>>>> /// getCallPreservedMask - Return a mask of call-preserved
>>>>>>>>> registers for the
>>>>>>>>> - /// given calling convention on the current sub-target. The
>>>>>>>>> mask should
>>>>>>>>> + /// given calling convention on the current function. The mask
>>>>>>>>> should
>>>>>>>>> /// include all call-preserved aliases. This is used by the
>>>>>>>>> register
>>>>>>>>> /// allocator to determine which registers can be live across a
>>>>>>>>> call.
>>>>>>>>> ///
>>>>>>>>> @@ -445,7 +445,8 @@ public:
>>>>>>>>> /// instructions should use implicit-def operands to indicate
>>>>>>>>> call clobbered
>>>>>>>>> /// registers.
>>>>>>>>> ///
>>>>>>>>> - virtual const uint32_t *getCallPreservedMask(CallingConv::ID)
>>>>>>>>> const {
>>>>>>>>> + virtual const uint32_t *getCallPreservedMask(const
>>>>>>>>> MachineFunction &MF,
>>>>>>>>> + CallingConv::ID)
>>>>>>>>> const {
>>>>>>>>> // The default mask clobbers everything. All targets should
>>>>>>>>> override.
>>>>>>>>> return nullptr;
>>>>>>>>> }
>>>>>>>>>
>>>>>>>>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
>>>>>>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/S
>>>>>>>>> electionDAG/FastISel.cpp?rev=231979&r1=231978&r2=231979&view=diff
>>>>>>>>> ============================================================
>>>>>>>>> ==================
>>>>>>>>> --- llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp (original)
>>>>>>>>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp Wed Mar 11
>>>>>>>>> 17:42:13 2015
>>>>>>>>> @@ -801,7 +801,8 @@ bool FastISel::selectPatchpoint(const Ca
>>>>>>>>> return false;
>>>>>>>>>
>>>>>>>>> // Push the register mask info.
>>>>>>>>> - Ops.push_back(MachineOperand::CreateRegMask(TRI.getCallPrese
>>>>>>>>> rvedMask(CC)));
>>>>>>>>> + Ops.push_back(MachineOperand::CreateRegMask(
>>>>>>>>> + TRI.getCallPreservedMask(*FuncInfo.MF, CC)));
>>>>>>>>>
>>>>>>>>> // Add scratch registers as implicit def and early clobber.
>>>>>>>>> const MCPhysReg *ScratchRegs = TLI.getScratchRegisters(CC);
>>>>>>>>>
>>>>>>>>> Modified: llvm/trunk/lib/Target/AArch64/AArch64FastISel.cpp
>>>>>>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AA
>>>>>>>>> rch64/AArch64FastISel.cpp?rev=231979&r1=231978&r2=231979&view=diff
>>>>>>>>> ============================================================
>>>>>>>>> ==================
>>>>>>>>> --- llvm/trunk/lib/Target/AArch64/AArch64FastISel.cpp (original)
>>>>>>>>> +++ llvm/trunk/lib/Target/AArch64/AArch64FastISel.cpp Wed Mar 11
>>>>>>>>> 17:42:13 2015
>>>>>>>>> @@ -3158,7 +3158,7 @@ bool AArch64FastISel::fastLowerCall(Call
>>>>>>>>>
>>>>>>>>> // Add a register mask with the call-preserved registers.
>>>>>>>>> // Proper defs for return values will be added by
>>>>>>>>> setPhysRegsDeadExcept().
>>>>>>>>> - MIB.addRegMask(TRI.getCallPreservedMask(CC));
>>>>>>>>> + MIB.addRegMask(TRI.getCallPreservedMask(*FuncInfo.MF, CC));
>>>>>>>>>
>>>>>>>>> CLI.Call = MIB;
>>>>>>>>>
>>>>>>>>>
>>>>>>>>> Modified: llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp
>>>>>>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AA
>>>>>>>>> rch64/AArch64ISelLowering.cpp?rev=231979&r1=231978&r2=231979
>>>>>>>>> &view=diff
>>>>>>>>> ============================================================
>>>>>>>>> ==================
>>>>>>>>> --- llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp
>>>>>>>>> (original)
>>>>>>>>> +++ llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp Wed Mar
>>>>>>>>> 11 17:42:13 2015
>>>>>>>>> @@ -2794,13 +2794,13 @@ AArch64TargetLowering::LowerCall(CallLow
>>>>>>>>> const AArch64RegisterInfo *TRI = Subtarget->getRegisterInfo();
>>>>>>>>> if (IsThisReturn) {
>>>>>>>>> // For 'this' returns, use the X0-preserving mask if
>>>>>>>>> applicable
>>>>>>>>> - Mask = TRI->getThisReturnPreservedMask(CallConv);
>>>>>>>>> + Mask = TRI->getThisReturnPreservedMask(MF, CallConv);
>>>>>>>>> if (!Mask) {
>>>>>>>>> IsThisReturn = false;
>>>>>>>>> - Mask = TRI->getCallPreservedMask(CallConv);
>>>>>>>>> + Mask = TRI->getCallPreservedMask(MF, CallConv);
>>>>>>>>> }
>>>>>>>>> } else
>>>>>>>>> - Mask = TRI->getCallPreservedMask(CallConv);
>>>>>>>>> + Mask = TRI->getCallPreservedMask(MF, CallConv);
>>>>>>>>>
>>>>>>>>> assert(Mask && "Missing call preserved mask for calling
>>>>>>>>> convention");
>>>>>>>>> Ops.push_back(DAG.getRegisterMask(Mask));
>>>>>>>>>
>>>>>>>>> Modified: llvm/trunk/lib/Target/AArch64/AArch64RegisterInfo.cpp
>>>>>>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AA
>>>>>>>>> rch64/AArch64RegisterInfo.cpp?rev=231979&r1=231978&r2=231979
>>>>>>>>> &view=diff
>>>>>>>>> ============================================================
>>>>>>>>> ==================
>>>>>>>>> --- llvm/trunk/lib/Target/AArch64/AArch64RegisterInfo.cpp
>>>>>>>>> (original)
>>>>>>>>> +++ llvm/trunk/lib/Target/AArch64/AArch64RegisterInfo.cpp Wed Mar
>>>>>>>>> 11 17:42:13 2015
>>>>>>>>> @@ -55,7 +55,8 @@ AArch64RegisterInfo::getCalleeSavedRegs(
>>>>>>>>> }
>>>>>>>>>
>>>>>>>>> const uint32_t *
>>>>>>>>> -AArch64RegisterInfo::getCallPreservedMask(CallingConv::ID CC)
>>>>>>>>> const {
>>>>>>>>> +AArch64RegisterInfo::getCallPreservedMask(const MachineFunction
>>>>>>>>> &MF,
>>>>>>>>> + CallingConv::ID CC)
>>>>>>>>> const {
>>>>>>>>> if (CC == CallingConv::GHC)
>>>>>>>>> // This is academic becase all GHC calls are (supposed to be)
>>>>>>>>> tail calls
>>>>>>>>> return CSR_AArch64_NoRegs_RegMask;
>>>>>>>>> @@ -74,7 +75,8 @@ const uint32_t *AArch64RegisterInfo::get
>>>>>>>>> }
>>>>>>>>>
>>>>>>>>> const uint32_t *
>>>>>>>>> -AArch64RegisterInfo::getThisReturnPreservedMask(CallingConv::ID
>>>>>>>>> CC) const {
>>>>>>>>> +AArch64RegisterInfo::getThisReturnPreservedMask(const
>>>>>>>>> MachineFunction &MF,
>>>>>>>>> + CallingConv::ID
>>>>>>>>> CC) const {
>>>>>>>>> // This should return a register mask that is the same as that
>>>>>>>>> returned by
>>>>>>>>> // getCallPreservedMask but that additionally preserves the
>>>>>>>>> register used for
>>>>>>>>> // the first i64 argument (which must also be the register used
>>>>>>>>> to return a
>>>>>>>>>
>>>>>>>>> Modified: llvm/trunk/lib/Target/AArch64/AArch64RegisterInfo.h
>>>>>>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AA
>>>>>>>>> rch64/AArch64RegisterInfo.h?rev=231979&r1=231978&r2=231979&v
>>>>>>>>> iew=diff
>>>>>>>>> ============================================================
>>>>>>>>> ==================
>>>>>>>>> --- llvm/trunk/lib/Target/AArch64/AArch64RegisterInfo.h (original)
>>>>>>>>> +++ llvm/trunk/lib/Target/AArch64/AArch64RegisterInfo.h Wed Mar
>>>>>>>>> 11 17:42:13 2015
>>>>>>>>> @@ -37,7 +37,8 @@ public:
>>>>>>>>>
>>>>>>>>> /// Code Generation virtual methods...
>>>>>>>>> const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF)
>>>>>>>>> const override;
>>>>>>>>> - const uint32_t *getCallPreservedMask(CallingConv::ID) const
>>>>>>>>> override;
>>>>>>>>> + const uint32_t *getCallPreservedMask(const MachineFunction &MF,
>>>>>>>>> + CallingConv::ID) const
>>>>>>>>> override;
>>>>>>>>>
>>>>>>>>> unsigned getCSRFirstUseCost() const override {
>>>>>>>>> // The cost will be compared against BlockFrequency where
>>>>>>>>> entry has the
>>>>>>>>> @@ -58,7 +59,8 @@ public:
>>>>>>>>> ///
>>>>>>>>> /// Should return NULL in the case that the calling convention
>>>>>>>>> does not have
>>>>>>>>> /// this property
>>>>>>>>> - const uint32_t *getThisReturnPreservedMask(CallingConv::ID)
>>>>>>>>> const;
>>>>>>>>> + const uint32_t *getThisReturnPreservedMask(const
>>>>>>>>> MachineFunction &MF,
>>>>>>>>> + CallingConv::ID)
>>>>>>>>> const;
>>>>>>>>>
>>>>>>>>> BitVector getReservedRegs(const MachineFunction &MF) const
>>>>>>>>> override;
>>>>>>>>> const TargetRegisterClass *
>>>>>>>>>
>>>>>>>>> Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp
>>>>>>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AR
>>>>>>>>> M/ARMBaseRegisterInfo.cpp?rev=231979&r1=231978&r2=231979&view=diff
>>>>>>>>> ============================================================
>>>>>>>>> ==================
>>>>>>>>> --- llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp (original)
>>>>>>>>> +++ llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Wed Mar 11
>>>>>>>>> 17:42:13 2015
>>>>>>>>> @@ -87,8 +87,9 @@ ARMBaseRegisterInfo::getCalleeSavedRegs(
>>>>>>>>> return RegList;
>>>>>>>>> }
>>>>>>>>>
>>>>>>>>> -const uint32_t*
>>>>>>>>> -ARMBaseRegisterInfo::getCallPreservedMask(CallingConv::ID CC)
>>>>>>>>> const {
>>>>>>>>> +const uint32_t *
>>>>>>>>> +ARMBaseRegisterInfo::getCallPreservedMask(const MachineFunction
>>>>>>>>> &MF,
>>>>>>>>> + CallingConv::ID CC)
>>>>>>>>> const {
>>>>>>>>> if (CC == CallingConv::GHC)
>>>>>>>>> // This is academic becase all GHC calls are (supposed to be)
>>>>>>>>> tail calls
>>>>>>>>> return CSR_NoRegs_RegMask;
>>>>>>>>> @@ -100,8 +101,9 @@ ARMBaseRegisterInfo::getNoPreservedMask(
>>>>>>>>> return CSR_NoRegs_RegMask;
>>>>>>>>> }
>>>>>>>>>
>>>>>>>>> -const uint32_t*
>>>>>>>>> -ARMBaseRegisterInfo::getThisReturnPreservedMask(CallingConv::ID
>>>>>>>>> CC) const {
>>>>>>>>> +const uint32_t *
>>>>>>>>> +ARMBaseRegisterInfo::getThisReturnPreservedMask(const
>>>>>>>>> MachineFunction &MF,
>>>>>>>>> + CallingConv::ID
>>>>>>>>> CC) const {
>>>>>>>>> // This should return a register mask that is the same as that
>>>>>>>>> returned by
>>>>>>>>> // getCallPreservedMask but that additionally preserves the
>>>>>>>>> register used for
>>>>>>>>> // the first i32 argument (which must also be the register used
>>>>>>>>> to return a
>>>>>>>>>
>>>>>>>>> Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h
>>>>>>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AR
>>>>>>>>> M/ARMBaseRegisterInfo.h?rev=231979&r1=231978&r2=231979&view=diff
>>>>>>>>> ============================================================
>>>>>>>>> ==================
>>>>>>>>> --- llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h (original)
>>>>>>>>> +++ llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h Wed Mar 11
>>>>>>>>> 17:42:13 2015
>>>>>>>>> @@ -101,7 +101,8 @@ protected:
>>>>>>>>> public:
>>>>>>>>> /// Code Generation virtual methods...
>>>>>>>>> const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF)
>>>>>>>>> const override;
>>>>>>>>> - const uint32_t *getCallPreservedMask(CallingConv::ID) const
>>>>>>>>> override;
>>>>>>>>> + const uint32_t *getCallPreservedMask(const MachineFunction &MF,
>>>>>>>>> + CallingConv::ID) const
>>>>>>>>> override;
>>>>>>>>> const uint32_t *getNoPreservedMask() const;
>>>>>>>>>
>>>>>>>>> /// getThisReturnPreservedMask - Returns a call preserved mask
>>>>>>>>> specific to the
>>>>>>>>> @@ -112,7 +113,8 @@ public:
>>>>>>>>> ///
>>>>>>>>> /// Should return NULL in the case that the calling convention
>>>>>>>>> does not have
>>>>>>>>> /// this property
>>>>>>>>> - const uint32_t *getThisReturnPreservedMask(CallingConv::ID)
>>>>>>>>> const;
>>>>>>>>> + const uint32_t *getThisReturnPreservedMask(const
>>>>>>>>> MachineFunction &MF,
>>>>>>>>> + CallingConv::ID)
>>>>>>>>> const;
>>>>>>>>>
>>>>>>>>> BitVector getReservedRegs(const MachineFunction &MF) const
>>>>>>>>> override;
>>>>>>>>>
>>>>>>>>>
>>>>>>>>> Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp
>>>>>>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AR
>>>>>>>>> M/ARMFastISel.cpp?rev=231979&r1=231978&r2=231979&view=diff
>>>>>>>>> ============================================================
>>>>>>>>> ==================
>>>>>>>>> --- llvm/trunk/lib/Target/ARM/ARMFastISel.cpp (original)
>>>>>>>>> +++ llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Wed Mar 11 17:42:13
>>>>>>>>> 2015
>>>>>>>>> @@ -2265,7 +2265,7 @@ bool ARMFastISel::ARMEmitLibcall(const I
>>>>>>>>>
>>>>>>>>> // Add a register mask with the call-preserved registers.
>>>>>>>>> // Proper defs for return values will be added by
>>>>>>>>> setPhysRegsDeadExcept().
>>>>>>>>> - MIB.addRegMask(TRI.getCallPreservedMask(CC));
>>>>>>>>> + MIB.addRegMask(TRI.getCallPreservedMask(*FuncInfo.MF, CC));
>>>>>>>>>
>>>>>>>>> // Finish off the call including any return values.
>>>>>>>>> SmallVector<unsigned, 4> UsedRegs;
>>>>>>>>> @@ -2416,7 +2416,7 @@ bool ARMFastISel::SelectCall(const Instr
>>>>>>>>>
>>>>>>>>> // Add a register mask with the call-preserved registers.
>>>>>>>>> // Proper defs for return values will be added by
>>>>>>>>> setPhysRegsDeadExcept().
>>>>>>>>> - MIB.addRegMask(TRI.getCallPreservedMask(CC));
>>>>>>>>> + MIB.addRegMask(TRI.getCallPreservedMask(*FuncInfo.MF, CC));
>>>>>>>>>
>>>>>>>>> // Finish off the call including any return values.
>>>>>>>>> SmallVector<unsigned, 4> UsedRegs;
>>>>>>>>>
>>>>>>>>> Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
>>>>>>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AR
>>>>>>>>> M/ARMISelLowering.cpp?rev=231979&r1=231978&r2=231979&view=diff
>>>>>>>>> ============================================================
>>>>>>>>> ==================
>>>>>>>>> --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
>>>>>>>>> +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Wed Mar 11
>>>>>>>>> 17:42:13 2015
>>>>>>>>> @@ -1814,16 +1814,16 @@ ARMTargetLowering::LowerCall(TargetLower
>>>>>>>>> const ARMBaseRegisterInfo *ARI = Subtarget->getRegisterInfo();
>>>>>>>>> if (isThisReturn) {
>>>>>>>>> // For 'this' returns, use the R0-preserving mask if
>>>>>>>>> applicable
>>>>>>>>> - Mask = ARI->getThisReturnPreservedMask(CallConv);
>>>>>>>>> + Mask = ARI->getThisReturnPreservedMask(MF, CallConv);
>>>>>>>>> if (!Mask) {
>>>>>>>>> // Set isThisReturn to false if the calling convention is
>>>>>>>>> not one that
>>>>>>>>> // allows 'returned' to be modeled in this way, so
>>>>>>>>> LowerCallResult does
>>>>>>>>> // not try to pass 'this' straight through
>>>>>>>>> isThisReturn = false;
>>>>>>>>> - Mask = ARI->getCallPreservedMask(CallConv);
>>>>>>>>> + Mask = ARI->getCallPreservedMask(MF, CallConv);
>>>>>>>>> }
>>>>>>>>> } else
>>>>>>>>> - Mask = ARI->getCallPreservedMask(CallConv);
>>>>>>>>> + Mask = ARI->getCallPreservedMask(MF, CallConv);
>>>>>>>>>
>>>>>>>>> assert(Mask && "Missing call preserved mask for calling
>>>>>>>>> convention");
>>>>>>>>> Ops.push_back(DAG.getRegisterMask(Mask));
>>>>>>>>>
>>>>>>>>> Modified: llvm/trunk/lib/Target/Mips/MipsFastISel.cpp
>>>>>>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mi
>>>>>>>>> ps/MipsFastISel.cpp?rev=231979&r1=231978&r2=231979&view=diff
>>>>>>>>> ============================================================
>>>>>>>>> ==================
>>>>>>>>> --- llvm/trunk/lib/Target/Mips/MipsFastISel.cpp (original)
>>>>>>>>> +++ llvm/trunk/lib/Target/Mips/MipsFastISel.cpp Wed Mar 11
>>>>>>>>> 17:42:13 2015
>>>>>>>>> @@ -1167,7 +1167,7 @@ bool MipsFastISel::fastLowerCall(CallLow
>>>>>>>>>
>>>>>>>>> // Add a register mask with the call-preserved registers.
>>>>>>>>> // Proper defs for return values will be added by
>>>>>>>>> setPhysRegsDeadExcept().
>>>>>>>>> - MIB.addRegMask(TRI.getCallPreservedMask(CC));
>>>>>>>>> + MIB.addRegMask(TRI.getCallPreservedMask(*FuncInfo.MF, CC));
>>>>>>>>>
>>>>>>>>> CLI.Call = MIB;
>>>>>>>>>
>>>>>>>>>
>>>>>>>>> Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
>>>>>>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mi
>>>>>>>>> ps/MipsISelLowering.cpp?rev=231979&r1=231978&r2=231979&view=diff
>>>>>>>>> ============================================================
>>>>>>>>> ==================
>>>>>>>>> --- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original)
>>>>>>>>> +++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Wed Mar 11
>>>>>>>>> 17:42:13 2015
>>>>>>>>> @@ -2481,7 +2481,8 @@ getOpndList(SmallVectorImpl<SDValue> &Op
>>>>>>>>>
>>>>>>>>> // Add a register mask operand representing the call-preserved
>>>>>>>>> registers.
>>>>>>>>> const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
>>>>>>>>> - const uint32_t *Mask = TRI->getCallPreservedMask(CLI.CallConv);
>>>>>>>>> + const uint32_t *Mask =
>>>>>>>>> + TRI->getCallPreservedMask(CLI.DAG.getMachineFunction(),
>>>>>>>>> CLI.CallConv);
>>>>>>>>> assert(Mask && "Missing call preserved mask for calling
>>>>>>>>> convention");
>>>>>>>>> if (Subtarget.inMips16HardFloat()) {
>>>>>>>>> if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(CLI.Callee))
>>>>>>>>> {
>>>>>>>>>
>>>>>>>>> Modified: llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp
>>>>>>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mi
>>>>>>>>> ps/MipsRegisterInfo.cpp?rev=231979&r1=231978&r2=231979&view=diff
>>>>>>>>> ============================================================
>>>>>>>>> ==================
>>>>>>>>> --- llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp (original)
>>>>>>>>> +++ llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp Wed Mar 11
>>>>>>>>> 17:42:13 2015
>>>>>>>>> @@ -100,8 +100,9 @@ MipsRegisterInfo::getCalleeSavedRegs(con
>>>>>>>>> return CSR_O32_SaveList;
>>>>>>>>> }
>>>>>>>>>
>>>>>>>>> -const uint32_t*
>>>>>>>>> -MipsRegisterInfo::getCallPreservedMask(CallingConv::ID) const {
>>>>>>>>> +const uint32_t *
>>>>>>>>> +MipsRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
>>>>>>>>> + CallingConv::ID) const {
>>>>>>>>> if (Subtarget.isSingleFloat())
>>>>>>>>> return CSR_SingleFloatOnly_RegMask;
>>>>>>>>>
>>>>>>>>>
>>>>>>>>> Modified: llvm/trunk/lib/Target/Mips/MipsRegisterInfo.h
>>>>>>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mi
>>>>>>>>> ps/MipsRegisterInfo.h?rev=231979&r1=231978&r2=231979&view=diff
>>>>>>>>> ============================================================
>>>>>>>>> ==================
>>>>>>>>> --- llvm/trunk/lib/Target/Mips/MipsRegisterInfo.h (original)
>>>>>>>>> +++ llvm/trunk/lib/Target/Mips/MipsRegisterInfo.h Wed Mar 11
>>>>>>>>> 17:42:13 2015
>>>>>>>>> @@ -48,7 +48,8 @@ public:
>>>>>>>>> unsigned getRegPressureLimit(const TargetRegisterClass *RC,
>>>>>>>>> MachineFunction &MF) const
>>>>>>>>> override;
>>>>>>>>> const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF)
>>>>>>>>> const override;
>>>>>>>>> - const uint32_t *getCallPreservedMask(CallingConv::ID) const
>>>>>>>>> override;
>>>>>>>>> + const uint32_t *getCallPreservedMask(const MachineFunction &MF,
>>>>>>>>> + CallingConv::ID) const
>>>>>>>>> override;
>>>>>>>>> static const uint32_t *getMips16RetHelperMask();
>>>>>>>>>
>>>>>>>>> BitVector getReservedRegs(const MachineFunction &MF) const
>>>>>>>>> override;
>>>>>>>>>
>>>>>>>>> Modified: llvm/trunk/lib/Target/PowerPC/PPCFastISel.cpp
>>>>>>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Po
>>>>>>>>> werPC/PPCFastISel.cpp?rev=231979&r1=231978&r2=231979&view=diff
>>>>>>>>> ============================================================
>>>>>>>>> ==================
>>>>>>>>> --- llvm/trunk/lib/Target/PowerPC/PPCFastISel.cpp (original)
>>>>>>>>> +++ llvm/trunk/lib/Target/PowerPC/PPCFastISel.cpp Wed Mar 11
>>>>>>>>> 17:42:13 2015
>>>>>>>>> @@ -1532,7 +1532,7 @@ bool PPCFastISel::fastLowerCall(CallLowe
>>>>>>>>>
>>>>>>>>> // Add a register mask with the call-preserved registers.
>>>>>>>>> Proper
>>>>>>>>> // defs for return values will be added by
>>>>>>>>> setPhysRegsDeadExcept().
>>>>>>>>> - MIB.addRegMask(TRI.getCallPreservedMask(CC));
>>>>>>>>> + MIB.addRegMask(TRI.getCallPreservedMask(*FuncInfo.MF, CC));
>>>>>>>>>
>>>>>>>>> CLI.Call = MIB;
>>>>>>>>>
>>>>>>>>>
>>>>>>>>> Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
>>>>>>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Po
>>>>>>>>> werPC/PPCISelLowering.cpp?rev=231979&r1=231978&r2=231979&view=diff
>>>>>>>>> ============================================================
>>>>>>>>> ==================
>>>>>>>>> --- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original)
>>>>>>>>> +++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Wed Mar 11
>>>>>>>>> 17:42:13 2015
>>>>>>>>> @@ -4187,7 +4187,8 @@ PPCTargetLowering::FinishCall(CallingCon
>>>>>>>>>
>>>>>>>>> // Add a register mask operand representing the call-preserved
>>>>>>>>> registers.
>>>>>>>>> const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
>>>>>>>>> - const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
>>>>>>>>> + const uint32_t *Mask =
>>>>>>>>> + TRI->getCallPreservedMask(DAG.getMachineFunction(),
>>>>>>>>> CallConv);
>>>>>>>>> assert(Mask && "Missing call preserved mask for calling
>>>>>>>>> convention");
>>>>>>>>> Ops.push_back(DAG.getRegisterMask(Mask));
>>>>>>>>>
>>>>>>>>>
>>>>>>>>> Modified: llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp
>>>>>>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Po
>>>>>>>>> werPC/PPCRegisterInfo.cpp?rev=231979&r1=231978&r2=231979&view=diff
>>>>>>>>> ============================================================
>>>>>>>>> ==================
>>>>>>>>> --- llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp (original)
>>>>>>>>> +++ llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp Wed Mar 11
>>>>>>>>> 17:42:13 2015
>>>>>>>>> @@ -128,8 +128,9 @@ PPCRegisterInfo::getCalleeSavedRegs(cons
>>>>>>>>> CSR_SVR432_SaveList);
>>>>>>>>> }
>>>>>>>>>
>>>>>>>>> -const uint32_t*
>>>>>>>>> -PPCRegisterInfo::getCallPreservedMask(CallingConv::ID CC) const {
>>>>>>>>> +const uint32_t *
>>>>>>>>> +PPCRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
>>>>>>>>> + CallingConv::ID CC) const {
>>>>>>>>> if (CC == CallingConv::AnyReg) {
>>>>>>>>> if (Subtarget.hasVSX())
>>>>>>>>> return CSR_64_AllRegs_VSX_RegMask;
>>>>>>>>>
>>>>>>>>> Modified: llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.h
>>>>>>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Po
>>>>>>>>> werPC/PPCRegisterInfo.h?rev=231979&r1=231978&r2=231979&view=diff
>>>>>>>>> ============================================================
>>>>>>>>> ==================
>>>>>>>>> --- llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.h (original)
>>>>>>>>> +++ llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.h Wed Mar 11
>>>>>>>>> 17:42:13 2015
>>>>>>>>> @@ -46,7 +46,8 @@ public:
>>>>>>>>>
>>>>>>>>> /// Code Generation virtual methods...
>>>>>>>>> const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF)
>>>>>>>>> const override;
>>>>>>>>> - const uint32_t *getCallPreservedMask(CallingConv::ID CC) const
>>>>>>>>> override;
>>>>>>>>> + const uint32_t *getCallPreservedMask(const MachineFunction &MF,
>>>>>>>>> + CallingConv::ID CC) const
>>>>>>>>> override;
>>>>>>>>> const uint32_t *getNoPreservedMask() const;
>>>>>>>>>
>>>>>>>>> void adjustStackMapLiveOutMask(uint32_t *Mask) const override;
>>>>>>>>>
>>>>>>>>> Modified: llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp
>>>>>>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sp
>>>>>>>>> arc/SparcISelLowering.cpp?rev=231979&r1=231978&r2=231979&view=diff
>>>>>>>>> ============================================================
>>>>>>>>> ==================
>>>>>>>>> --- llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp (original)
>>>>>>>>> +++ llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp Wed Mar 11
>>>>>>>>> 17:42:13 2015
>>>>>>>>> @@ -915,9 +915,10 @@ SparcTargetLowering::LowerCall_32(Target
>>>>>>>>>
>>>>>>>>> // Add a register mask operand representing the call-preserved
>>>>>>>>> registers.
>>>>>>>>> const SparcRegisterInfo *TRI = Subtarget->getRegisterInfo();
>>>>>>>>> - const uint32_t *Mask = ((hasReturnsTwice)
>>>>>>>>> - ? TRI->getRTCallPreservedMask(CallConv)
>>>>>>>>> - : TRI->getCallPreservedMask(CallConv));
>>>>>>>>> + const uint32_t *Mask =
>>>>>>>>> + ((hasReturnsTwice)
>>>>>>>>> + ? TRI->getRTCallPreservedMask(CallConv)
>>>>>>>>> + : TRI->getCallPreservedMask(DAG.getMachineFunction(),
>>>>>>>>> CallConv));
>>>>>>>>> assert(Mask && "Missing call preserved mask for calling
>>>>>>>>> convention");
>>>>>>>>> Ops.push_back(DAG.getRegisterMask(Mask));
>>>>>>>>>
>>>>>>>>> @@ -1229,7 +1230,8 @@ SparcTargetLowering::LowerCall_64(Target
>>>>>>>>> const SparcRegisterInfo *TRI = Subtarget->getRegisterInfo();
>>>>>>>>> const uint32_t *Mask =
>>>>>>>>> ((hasReturnsTwice) ? TRI->getRTCallPreservedMask(CL
>>>>>>>>> I.CallConv)
>>>>>>>>> - : TRI->getCallPreservedMask(CLI.
>>>>>>>>> CallConv));
>>>>>>>>> + : TRI->getCallPreservedMask(DAG.
>>>>>>>>> getMachineFunction(),
>>>>>>>>> +
>>>>>>>>> CLI.CallConv));
>>>>>>>>> assert(Mask && "Missing call preserved mask for calling
>>>>>>>>> convention");
>>>>>>>>> Ops.push_back(DAG.getRegisterMask(Mask));
>>>>>>>>>
>>>>>>>>> @@ -1904,8 +1906,8 @@ SDValue SparcTargetLowering::LowerGlobal
>>>>>>>>> Ops.push_back(Callee);
>>>>>>>>> Ops.push_back(Symbol);
>>>>>>>>> Ops.push_back(DAG.getRegister(SP::O0, PtrVT));
>>>>>>>>> - const uint32_t *Mask =
>>>>>>>>> - Subtarget->getRegisterInfo()->getCallPreservedMask(
>>>>>>>>> CallingConv::C);
>>>>>>>>> + const uint32_t *Mask = Subtarget->getRegisterInfo()->
>>>>>>>>> getCallPreservedMask(
>>>>>>>>> + DAG.getMachineFunction(), CallingConv::C);
>>>>>>>>> assert(Mask && "Missing call preserved mask for calling
>>>>>>>>> convention");
>>>>>>>>> Ops.push_back(DAG.getRegisterMask(Mask));
>>>>>>>>> Ops.push_back(InFlag);
>>>>>>>>>
>>>>>>>>> Modified: llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.cpp
>>>>>>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sp
>>>>>>>>> arc/SparcRegisterInfo.cpp?rev=231979&r1=231978&r2=231979&view=diff
>>>>>>>>> ============================================================
>>>>>>>>> ==================
>>>>>>>>> --- llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.cpp (original)
>>>>>>>>> +++ llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.cpp Wed Mar 11
>>>>>>>>> 17:42:13 2015
>>>>>>>>> @@ -43,8 +43,9 @@ SparcRegisterInfo::getCalleeSavedRegs(co
>>>>>>>>> return CSR_SaveList;
>>>>>>>>> }
>>>>>>>>>
>>>>>>>>> -const uint32_t*
>>>>>>>>> -SparcRegisterInfo::getCallPreservedMask(CallingConv::ID CC)
>>>>>>>>> const {
>>>>>>>>> +const uint32_t *
>>>>>>>>> +SparcRegisterInfo::getCallPreservedMask(const MachineFunction
>>>>>>>>> &MF,
>>>>>>>>> + CallingConv::ID CC) const
>>>>>>>>> {
>>>>>>>>> return CSR_RegMask;
>>>>>>>>> }
>>>>>>>>>
>>>>>>>>>
>>>>>>>>> Modified: llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.h
>>>>>>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sp
>>>>>>>>> arc/SparcRegisterInfo.h?rev=231979&r1=231978&r2=231979&view=diff
>>>>>>>>> ============================================================
>>>>>>>>> ==================
>>>>>>>>> --- llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.h (original)
>>>>>>>>> +++ llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.h Wed Mar 11
>>>>>>>>> 17:42:13 2015
>>>>>>>>> @@ -32,7 +32,8 @@ struct SparcRegisterInfo : public SparcG
>>>>>>>>>
>>>>>>>>> /// Code Generation virtual methods...
>>>>>>>>> const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF)
>>>>>>>>> const override;
>>>>>>>>> - const uint32_t* getCallPreservedMask(CallingConv::ID CC) const
>>>>>>>>> override;
>>>>>>>>> + const uint32_t *getCallPreservedMask(const MachineFunction &MF,
>>>>>>>>> + CallingConv::ID CC) const
>>>>>>>>> override;
>>>>>>>>>
>>>>>>>>> const uint32_t* getRTCallPreservedMask(CallingConv::ID CC)
>>>>>>>>> const;
>>>>>>>>>
>>>>>>>>>
>>>>>>>>> Modified: llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp
>>>>>>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sy
>>>>>>>>> stemZ/SystemZISelLowering.cpp?rev=231979&r1=231978&r2=231979
>>>>>>>>> &view=diff
>>>>>>>>> ============================================================
>>>>>>>>> ==================
>>>>>>>>> --- llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp
>>>>>>>>> (original)
>>>>>>>>> +++ llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp Wed Mar
>>>>>>>>> 11 17:42:13 2015
>>>>>>>>> @@ -920,7 +920,7 @@ SystemZTargetLowering::LowerCall(CallLow
>>>>>>>>>
>>>>>>>>> // Add a register mask operand representing the call-preserved
>>>>>>>>> registers.
>>>>>>>>> const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
>>>>>>>>> - const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
>>>>>>>>> + const uint32_t *Mask = TRI->getCallPreservedMask(MF, CallConv);
>>>>>>>>> assert(Mask && "Missing call preserved mask for calling
>>>>>>>>> convention");
>>>>>>>>> Ops.push_back(DAG.getRegisterMask(Mask));
>>>>>>>>>
>>>>>>>>> @@ -1858,7 +1858,8 @@ SDValue SystemZTargetLowering::lowerTLSG
>>>>>>>>>
>>>>>>>>> // Add a register mask operand representing the call-preserved
>>>>>>>>> registers.
>>>>>>>>> const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
>>>>>>>>> - const uint32_t *Mask = TRI->getCallPreservedMask(Call
>>>>>>>>> ingConv::C);
>>>>>>>>> + const uint32_t *Mask =
>>>>>>>>> + TRI->getCallPreservedMask(DAG.getMachineFunction(),
>>>>>>>>> CallingConv::C);
>>>>>>>>> assert(Mask && "Missing call preserved mask for calling
>>>>>>>>> convention");
>>>>>>>>> Ops.push_back(DAG.getRegisterMask(Mask));
>>>>>>>>>
>>>>>>>>>
>>>>>>>>> Modified: llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.cpp
>>>>>>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sy
>>>>>>>>> stemZ/SystemZRegisterInfo.cpp?rev=231979&r1=231978&r2=231979
>>>>>>>>> &view=diff
>>>>>>>>> ============================================================
>>>>>>>>> ==================
>>>>>>>>> --- llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.cpp
>>>>>>>>> (original)
>>>>>>>>> +++ llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.cpp Wed Mar
>>>>>>>>> 11 17:42:13 2015
>>>>>>>>> @@ -28,7 +28,8 @@ SystemZRegisterInfo::getCalleeSavedRegs(
>>>>>>>>> }
>>>>>>>>>
>>>>>>>>> const uint32_t *
>>>>>>>>> -SystemZRegisterInfo::getCallPreservedMask(CallingConv::ID CC)
>>>>>>>>> const {
>>>>>>>>> +SystemZRegisterInfo::getCallPreservedMask(const MachineFunction
>>>>>>>>> &MF,
>>>>>>>>> + CallingConv::ID CC)
>>>>>>>>> const {
>>>>>>>>> return CSR_SystemZ_RegMask;
>>>>>>>>> }
>>>>>>>>>
>>>>>>>>>
>>>>>>>>> Modified: llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.h
>>>>>>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sy
>>>>>>>>> stemZ/SystemZRegisterInfo.h?rev=231979&r1=231978&r2=231979&v
>>>>>>>>> iew=diff
>>>>>>>>> ============================================================
>>>>>>>>> ==================
>>>>>>>>> --- llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.h (original)
>>>>>>>>> +++ llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.h Wed Mar
>>>>>>>>> 11 17:42:13 2015
>>>>>>>>> @@ -44,7 +44,8 @@ public:
>>>>>>>>> return true;
>>>>>>>>> }
>>>>>>>>> const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF)
>>>>>>>>> const override;
>>>>>>>>> - const uint32_t *getCallPreservedMask(CallingConv::ID CC) const
>>>>>>>>> override;
>>>>>>>>> + const uint32_t *getCallPreservedMask(const MachineFunction &MF,
>>>>>>>>> + CallingConv::ID CC) const
>>>>>>>>> override;
>>>>>>>>> BitVector getReservedRegs(const MachineFunction &MF) const
>>>>>>>>> override;
>>>>>>>>> void eliminateFrameIndex(MachineBasicBlock::iterator MI,
>>>>>>>>> int SPAdj, unsigned FIOperandNum,
>>>>>>>>>
>>>>>>>>> Modified: llvm/trunk/lib/Target/X86/X86FastISel.cpp
>>>>>>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X8
>>>>>>>>> 6/X86FastISel.cpp?rev=231979&r1=231978&r2=231979&view=diff
>>>>>>>>> ============================================================
>>>>>>>>> ==================
>>>>>>>>> --- llvm/trunk/lib/Target/X86/X86FastISel.cpp (original)
>>>>>>>>> +++ llvm/trunk/lib/Target/X86/X86FastISel.cpp Wed Mar 11 17:42:13
>>>>>>>>> 2015
>>>>>>>>> @@ -3062,7 +3062,7 @@ bool X86FastISel::fastLowerCall(CallLowe
>>>>>>>>>
>>>>>>>>> // Add a register mask operand representing the call-preserved
>>>>>>>>> registers.
>>>>>>>>> // Proper defs for return values will be added by
>>>>>>>>> setPhysRegsDeadExcept().
>>>>>>>>> - MIB.addRegMask(TRI.getCallPreservedMask(CC));
>>>>>>>>> + MIB.addRegMask(TRI.getCallPreservedMask(*FuncInfo.MF, CC));
>>>>>>>>>
>>>>>>>>> // Add an implicit use GOT pointer in EBX.
>>>>>>>>> if (Subtarget->isPICStyleGOT())
>>>>>>>>>
>>>>>>>>> Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
>>>>>>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X8
>>>>>>>>> 6/X86ISelLowering.cpp?rev=231979&r1=231978&r2=231979&view=diff
>>>>>>>>> ============================================================
>>>>>>>>> ==================
>>>>>>>>> --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
>>>>>>>>> +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Wed Mar 11
>>>>>>>>> 17:42:13 2015
>>>>>>>>> @@ -3161,7 +3161,7 @@ X86TargetLowering::LowerCall(TargetLower
>>>>>>>>>
>>>>>>>>> // Add a register mask operand representing the call-preserved
>>>>>>>>> registers.
>>>>>>>>> const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
>>>>>>>>> - const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
>>>>>>>>> + const uint32_t *Mask = TRI->getCallPreservedMask(MF, CallConv);
>>>>>>>>> assert(Mask && "Missing call preserved mask for calling
>>>>>>>>> convention");
>>>>>>>>> Ops.push_back(DAG.getRegisterMask(Mask));
>>>>>>>>>
>>>>>>>>> @@ -18453,7 +18453,7 @@ X86TargetLowering::EmitLoweredSegAlloca(
>>>>>>>>>
>>>>>>>>> // Calls into a routine in libgcc to allocate more space from
>>>>>>>>> the heap.
>>>>>>>>> const uint32_t *RegMask =
>>>>>>>>> - Subtarget->getRegisterInfo()->getCallPreservedMask(
>>>>>>>>> CallingConv::C);
>>>>>>>>> + Subtarget->getRegisterInfo()->getCallPreservedMask(*MF,
>>>>>>>>> CallingConv::C);
>>>>>>>>> if (IsLP64) {
>>>>>>>>> BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
>>>>>>>>> .addReg(sizeVReg);
>>>>>>>>> @@ -18538,7 +18538,7 @@ X86TargetLowering::EmitLoweredTLSCall(Ma
>>>>>>>>> // FIXME: The 32-bit calls have non-standard calling
>>>>>>>>> conventions. Use a
>>>>>>>>> // proper register mask.
>>>>>>>>> const uint32_t *RegMask =
>>>>>>>>> - Subtarget->getRegisterInfo()->getCallPreservedMask(
>>>>>>>>> CallingConv::C);
>>>>>>>>> + Subtarget->getRegisterInfo()->getCallPreservedMask(*F,
>>>>>>>>> CallingConv::C);
>>>>>>>>> if (Subtarget->is64Bit()) {
>>>>>>>>> MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
>>>>>>>>> TII->get(X86::MOV64rm),
>>>>>>>>> X86::RDI)
>>>>>>>>>
>>>>>>>>> Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp
>>>>>>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X8
>>>>>>>>> 6/X86RegisterInfo.cpp?rev=231979&r1=231978&r2=231979&view=diff
>>>>>>>>> ============================================================
>>>>>>>>> ==================
>>>>>>>>> --- llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp (original)
>>>>>>>>> +++ llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp Wed Mar 11
>>>>>>>>> 17:42:13 2015
>>>>>>>>> @@ -277,8 +277,9 @@ X86RegisterInfo::getCalleeSavedRegs(cons
>>>>>>>>> return CSR_32_SaveList;
>>>>>>>>> }
>>>>>>>>>
>>>>>>>>> -const uint32_t*
>>>>>>>>> -X86RegisterInfo::getCallPreservedMask(CallingConv::ID CC) const {
>>>>>>>>> +const uint32_t *
>>>>>>>>> +X86RegisterInfo::getCallPreservedMask(const MachineFunction &MF,
>>>>>>>>> + CallingConv::ID CC) const {
>>>>>>>>> bool HasAVX = Subtarget.hasAVX();
>>>>>>>>> bool HasAVX512 = Subtarget.hasAVX512();
>>>>>>>>>
>>>>>>>>> @@ -360,7 +361,7 @@ BitVector X86RegisterInfo::getReservedRe
>>>>>>>>> // Set the base-pointer register and its aliases as reserved if
>>>>>>>>> needed.
>>>>>>>>> if (hasBasePointer(MF)) {
>>>>>>>>> CallingConv::ID CC = MF.getFunction()->getCallingConv();
>>>>>>>>> - const uint32_t* RegMask = getCallPreservedMask(CC);
>>>>>>>>> + const uint32_t *RegMask = getCallPreservedMask(MF, CC);
>>>>>>>>> if (MachineOperand::clobbersPhysReg(RegMask,
>>>>>>>>> getBaseRegister()))
>>>>>>>>> report_fatal_error(
>>>>>>>>> "Stack realignment in presence of dynamic allocas is not
>>>>>>>>> supported with"
>>>>>>>>>
>>>>>>>>> Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.h
>>>>>>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X8
>>>>>>>>> 6/X86RegisterInfo.h?rev=231979&r1=231978&r2=231979&view=diff
>>>>>>>>> ============================================================
>>>>>>>>> ==================
>>>>>>>>> --- llvm/trunk/lib/Target/X86/X86RegisterInfo.h (original)
>>>>>>>>> +++ llvm/trunk/lib/Target/X86/X86RegisterInfo.h Wed Mar 11
>>>>>>>>> 17:42:13 2015
>>>>>>>>> @@ -99,7 +99,8 @@ public:
>>>>>>>>> /// callee-save registers on this target.
>>>>>>>>> const MCPhysReg *
>>>>>>>>> getCalleeSavedRegs(const MachineFunction* MF) const override;
>>>>>>>>> - const uint32_t *getCallPreservedMask(CallingConv::ID) const
>>>>>>>>> override;
>>>>>>>>> + const uint32_t *getCallPreservedMask(const MachineFunction &MF,
>>>>>>>>> + CallingConv::ID) const
>>>>>>>>> override;
>>>>>>>>> const uint32_t *getNoPreservedMask() const;
>>>>>>>>>
>>>>>>>>> /// getReservedRegs - Returns a bitset indexed by physical
>>>>>>>>> register number
>>>>>>>>>
>>>>>>>>>
>>>>>>>>> _______________________________________________
>>>>>>>>> llvm-commits mailing list
>>>>>>>>> llvm-commits at cs.uiuc.edu
>>>>>>>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>>>>>>>>>
>>>>>>>>
>>>>>>>> _______________________________________________
>>>>>>>> llvm-commits mailing list
>>>>>>>> llvm-commits at cs.uiuc.edu
>>>>>>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>>>>>>>>
>>>>>>>>
>
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