[PATCH] [mips] [IAS] Add support for the XOR $reg, imm pseudo-instruction.

[Daniel Sanders]

LGTM


================
Comment at: lib/Target/Mips/MipsInstrInfo.td:1583-1584
@@ -1582,2 +1582,4 @@
                     (XORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
+def : MipsInstAlias<"xor $rs, $imm",
+                    (XORi GPR32Opnd:$rs, GPR32Opnd:$rs, uimm16:$imm), 0>;
 def : MipsInstAlias<"or $rs, $rt, $imm",
----------------
Just to mention it: This isn't quite right for the 64-bit ISA's but it will do the correct thing as far as the assembler is concerned by virtue of having the same opcode. It's not a problem with any tools we currently develop so no changes required.

http://reviews.llvm.org/D8284

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