[PATCH] [mips] Add assembler support for the .cprestore directive.
Toma Tabacu
toma.tabacu at imgtec.com
Fri Mar 13 08:33:46 PDT 2015
Replied to an inline comment.
================
Comment at: lib/Target/Mips/AsmParser/MipsAsmParser.cpp:1806-1816
@@ -1750,9 +1805,13 @@
if (AssemblerOptions.back()->isReorder()) {
- // This is a 32-bit NOP because these 2 pseudo-instructions
- // do not have a short delay slot.
MCInst NopInst;
- NopInst.setOpcode(Mips::SLL);
- NopInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
- NopInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
- NopInst.addOperand(MCOperand::CreateImm(0));
+ if (hasShortDelaySlot(JalrInst.getOpcode())) {
+ NopInst.setOpcode(Mips::MOVE16_MM);
+ NopInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
+ NopInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
+ } else {
+ NopInst.setOpcode(Mips::SLL);
+ NopInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
+ NopInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
+ NopInst.addOperand(MCOperand::CreateImm(0));
+ }
Instructions.push_back(NopInst);
----------------
dsanders wrote:
> We ought to factor out the nop emission at some point
Done in http://reviews.llvm.org/D8320. I'd rather wait until that gets committed before I update this one, instead of juggling around with all these patches.
http://reviews.llvm.org/D6267
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