[llvm] r232027 - Add infrastructure for support of multiple memory constraints.
Hal Finkel
hfinkel at anl.gov
Thu Mar 12 13:13:27 PDT 2015
Hi Daniel,
I reverted this in r232093 because it caused https://llvm.org/bugs/show_bug.cgi?id=22883
-Hal
----- Original Message -----
> From: "Daniel Sanders" <daniel.sanders at imgtec.com>
> To: llvm-commits at cs.uiuc.edu
> Sent: Thursday, March 12, 2015 6:00:49 AM
> Subject: [llvm] r232027 - Add infrastructure for support of multiple memory constraints.
>
> Author: dsanders
> Date: Thu Mar 12 06:00:48 2015
> New Revision: 232027
>
> URL: http://llvm.org/viewvc/llvm-project?rev=232027&view=rev
> Log:
> Add infrastructure for support of multiple memory constraints.
>
> Summary:
> The operand flag word for ISD::INLINEASM nodes now contains a 15-bit
> memory constraint ID when the operand kind is Kind_Mem. This
> constraint
> ID is a numeric equivalent to the constraint code string and is
> converted
> with a target specific hook in TargetLowering.
>
> This patch maps all memory constraints to InlineAsm::Constraint_m so
> there
> is no functional change at this point. It just proves that using
> these
> previously unused bits in the encoding of the flag word doesn't break
> anything.
>
> The next patch will make each target preserve the current mapping of
> everything to Constraint_m for itself while changing the target
> independent
> implementation of the hook to return Constraint_Unknown
> appropriately. Each
> target will then be adapted in separate patches to use appropriate
> Constraint_*
> values.
>
> Reviewers: hfinkel
>
> Reviewed By: hfinkel
>
> Subscribers: hfinkel, jholewinski, llvm-commits
>
> Differential Revision: http://reviews.llvm.org/D8171
>
> Modified:
> llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h
> llvm/trunk/include/llvm/IR/InlineAsm.h
> llvm/trunk/include/llvm/Target/TargetLowering.h
> llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
> llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
> llvm/trunk/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
> llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp
> llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
> llvm/trunk/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp
> llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp
> llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.h
> llvm/trunk/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
> llvm/trunk/lib/Target/NVPTX/NVPTXISelDAGToDAG.h
> llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
> llvm/trunk/lib/Target/Sparc/SparcISelDAGToDAG.cpp
> llvm/trunk/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
> llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
> llvm/trunk/lib/Target/XCore/XCoreISelDAGToDAG.cpp
>
> Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h?rev=232027&r1=232026&r2=232027&view=diff
> ==============================================================================
> --- llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h (original)
> +++ llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h Thu Mar 12
> 06:00:48 2015
> @@ -80,12 +80,12 @@ public:
> virtual SDNode *Select(SDNode *N) = 0;
>
> /// SelectInlineAsmMemoryOperand - Select the specified address as
> a target
> - /// addressing mode, according to the specified constraint code.
> If this does
> + /// addressing mode, according to the specified constraint. If
> this does
> /// not match or is not implemented, return true. The resultant
> operands
> /// (which will appear in the machine instruction) should be added
> to the
> /// OutOps vector.
> virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
> - char ConstraintCode,
> + unsigned ConstraintID,
> std::vector<SDValue>
> &OutOps) {
> return true;
> }
>
> Modified: llvm/trunk/include/llvm/IR/InlineAsm.h
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IR/InlineAsm.h?rev=232027&r1=232026&r2=232027&view=diff
> ==============================================================================
> --- llvm/trunk/include/llvm/IR/InlineAsm.h (original)
> +++ llvm/trunk/include/llvm/IR/InlineAsm.h Thu Mar 12 06:00:48 2015
> @@ -189,6 +189,19 @@ public:
>
> // These are helper methods for dealing with flags in the
> INLINEASM SDNode
> // in the backend.
> + //
> + // The encoding of the flag word is currently:
> + // Bits 2-0 - A Kind_* value indicating the kind of the operand.
> + // Bits 15-3 - The number of SDNode operands associated with
> this inline
> + // assembly operand.
> + // If bits 2-0 are Kind_Mem:
> + // Bit 31 - 0
> + // Bit 30-16 - A Constraint_* value indicating the original
> constraint
> + // code.
> + // Else if bit 31 is set:
> + // Bit 30-16 - The operand number that this operand must
> match.
> + // Else if bit 31 is clear:
> + // Bit 30-16 - The register class ID to use for the operand.
>
> enum : uint32_t {
> // Fixed operands on an INLINEASM SDNode.
> @@ -220,6 +233,17 @@ public:
> Kind_Imm = 5, // Immediate.
> Kind_Mem = 6, // Memory operand, "m".
>
> + // Memory constraint codes.
> + // These could be tablegenerated but there's little need to do
> that since
> + // there's plenty of space in the encoding to support the union
> of all
> + // constraint codes for all targets.
> + Constraint_Unknown = 0,
> + Constraint_m,
> + Constraint_o, // Unused at the moment since Constraint_m is
> always used.
> + Constraint_v, // Unused at the moment since Constraint_m is
> always used.
> + Constraints_Max = Constraint_v,
> + Constraints_ShiftAmount = 16,
> +
> Flag_MatchingOperand = 0x80000000
> };
>
> @@ -252,6 +276,15 @@ public:
> return InputFlag | (RC << 16);
> }
>
> + /// Augment an existing flag word returned by getFlagWord with the
> constraint
> + /// code for a memory constraint.
> + static unsigned getFlagWordForMem(unsigned InputFlag, unsigned
> Constraint) {
> + assert(Constraint <= 0x7fff && "Too large a memory constraint
> ID");
> + assert(Constraint <= Constraints_Max && "Unknown constraint
> ID");
> + assert((InputFlag & ~0xffff) == 0 && "High bits already contain
> data");
> + return InputFlag | (Constraint << Constraints_ShiftAmount);
> + }
> +
> static unsigned getKind(unsigned Flags) {
> return Flags & 7;
> }
> @@ -266,6 +299,11 @@ public:
> return getKind(Flag) == Kind_Clobber;
> }
>
> + static unsigned getMemoryConstraintID(unsigned Flag) {
> + assert(isMemKind(Flag));
> + return (Flag >> Constraints_ShiftAmount) & 0x7fff;
> + }
> +
> /// getNumOperandRegisters - Extract the number of registers field
> from the
> /// inline asm operand flag.
> static unsigned getNumOperandRegisters(unsigned Flag) {
>
> Modified: llvm/trunk/include/llvm/Target/TargetLowering.h
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetLowering.h?rev=232027&r1=232026&r2=232027&view=diff
> ==============================================================================
> --- llvm/trunk/include/llvm/Target/TargetLowering.h (original)
> +++ llvm/trunk/include/llvm/Target/TargetLowering.h Thu Mar 12
> 06:00:48 2015
> @@ -2625,6 +2625,13 @@ public:
> getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
> const std::string &Constraint, MVT
> VT) const;
>
> + virtual unsigned
> + getInlineAsmMemConstraint(const std::string &ConstraintCode) const
> {
> + // FIXME: This currently maps all constraints to the the same
> code.
> + // This will be corrected once all targets are updated.
> + return InlineAsm::Constraint_m;
> + }
> +
> /// Try to replace an X constraint, which matches anything, with
> another that
> /// has more specific requirements based on the type of the
> corresponding
> /// operand. This returns null if there is no replacement to
> make.
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=232027&r1=232026&r2=232027&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
> (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Thu
> Mar 12 06:00:48 2015
> @@ -6598,8 +6598,14 @@ void SelectionDAGBuilder::visitInlineAsm
> // Memory output, or 'other' output (e.g. 'X' constraint).
> assert(OpInfo.isIndirect && "Memory output must be indirect
> operand");
>
> + unsigned ConstraintID =
> + TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
> + assert(ConstraintID != InlineAsm::Constraint_Unknown &&
> + "Failed to convert memory constraint code to
> constraint id.");
> +
> // Add information to the INLINEASM node to know about this
> output.
> unsigned OpFlags =
> InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
> + OpFlags = InlineAsm::getFlagWordForMem(OpFlags,
> ConstraintID);
> AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags,
> MVT::i32));
> AsmNodeOperands.push_back(OpInfo.CallOperand);
> break;
> @@ -6743,8 +6749,14 @@ void SelectionDAGBuilder::visitInlineAsm
> assert(InOperandVal.getValueType() == TLI.getPointerTy() &&
> "Memory operands expect pointer values");
>
> + unsigned ConstraintID =
> + TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
> + assert(ConstraintID != InlineAsm::Constraint_Unknown &&
> + "Failed to convert memory constraint code to
> constraint id.");
> +
> // Add information to the INLINEASM node to know about this
> input.
> unsigned ResOpType =
> InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
> + ResOpType = InlineAsm::getFlagWordForMem(ResOpType,
> ConstraintID);
> AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
> MVT::i32));
> AsmNodeOperands.push_back(InOperandVal);
> break;
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=232027&r1=232026&r2=232027&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
> (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Thu Mar
> 12 06:00:48 2015
> @@ -1781,7 +1781,9 @@ SelectInlineAsmMemoryOperands(std::vecto
> "Memory operand with multiple values?");
> // Otherwise, this is a memory operand. Ask the target to
> select it.
> std::vector<SDValue> SelOps;
> - if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps))
> + if (SelectInlineAsmMemoryOperand(InOps[i+1],
> +
> InlineAsm::getMemoryConstraintID(Flags),
> + SelOps))
> report_fatal_error("Could not match memory address. Inline
> asm"
> " failure!");
>
>
> Modified: llvm/trunk/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp?rev=232027&r1=232026&r2=232027&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp (original)
> +++ llvm/trunk/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp Thu Mar 12
> 06:00:48 2015
> @@ -65,7 +65,7 @@ public:
> /// SelectInlineAsmMemoryOperand - Implement addressing mode
> selection for
> /// inline asm expressions.
> bool SelectInlineAsmMemoryOperand(const SDValue &Op,
> - char ConstraintCode,
> + unsigned ConstraintID,
> std::vector<SDValue> &OutOps)
> override;
>
> SDNode *SelectMLAV64LaneV128(SDNode *N);
> @@ -211,8 +211,9 @@ static bool isOpcWithIntImmediate(const
> }
>
> bool AArch64DAGToDAGISel::SelectInlineAsmMemoryOperand(
> - const SDValue &Op, char ConstraintCode, std::vector<SDValue>
> &OutOps) {
> - assert(ConstraintCode == 'm' && "unexpected asm memory
> constraint");
> + const SDValue &Op, unsigned ConstraintID, std::vector<SDValue>
> &OutOps) {
> + assert(ConstraintID == InlineAsm::Constraint_m &&
> + "unexpected asm memory constraint");
> // Require the address to be in a register. That is safe for all
> AArch64
> // variants and it is hard to do anything much smarter without
> knowing
> // how the operand is used.
>
> Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp?rev=232027&r1=232026&r2=232027&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Thu Mar 12 06:00:48
> 2015
> @@ -257,7 +257,7 @@ private:
>
> /// SelectInlineAsmMemoryOperand - Implement addressing mode
> selection for
> /// inline asm expressions.
> - bool SelectInlineAsmMemoryOperand(const SDValue &Op, char
> ConstraintCode,
> + bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned
> ConstraintID,
> std::vector<SDValue> &OutOps)
> override;
>
> // Form pairs of consecutive R, S, D, or Q registers.
> @@ -3472,9 +3472,10 @@ SDNode *ARMDAGToDAGISel::SelectInlineAsm
>
>
> bool ARMDAGToDAGISel::
> -SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
> +SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned
> ConstraintID,
> std::vector<SDValue> &OutOps) {
> - assert(ConstraintCode == 'm' && "unexpected asm memory
> constraint");
> + assert(ConstraintID == InlineAsm::Constraint_m &&
> + "unexpected asm memory constraint");
> // Require the address to be in a register. That is safe for all
> ARM
> // variants and it is hard to do anything much smarter without
> knowing
> // how the operand is used.
>
> Modified: llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp?rev=232027&r1=232026&r2=232027&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp (original)
> +++ llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp Thu Mar 12
> 06:00:48 2015
> @@ -93,7 +93,7 @@ public:
> /// SelectInlineAsmMemoryOperand - Implement addressing mode
> selection for
> /// inline asm expressions.
> bool SelectInlineAsmMemoryOperand(const SDValue &Op,
> - char ConstraintCode,
> + unsigned ConstraintID,
> std::vector<SDValue> &OutOps)
> override;
> bool SelectAddr(SDNode *Op, SDValue Addr, SDValue &Base, SDValue
> &Offset);
>
> @@ -1405,15 +1405,15 @@ bool HexagonDAGToDAGISel::SelectAddr(SDN
>
>
> bool HexagonDAGToDAGISel::
> -SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
> +SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned
> ConstraintID,
> std::vector<SDValue> &OutOps) {
> SDValue Op0, Op1;
>
> - switch (ConstraintCode) {
> - case 'o': // Offsetable.
> - case 'v': // Not offsetable.
> + switch (ConstraintID) {
> + case InlineAsm::Constraint_o: // Offsetable.
> + case InlineAsm::Constraint_v: // Not offsetable.
> default: return true;
> - case 'm': // Memory.
> + case InlineAsm::Constraint_m: // Memory.
> if (!SelectAddr(Op.getNode(), Op, Op0, Op1))
> return true;
> break;
>
> Modified: llvm/trunk/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp?rev=232027&r1=232026&r2=232027&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp (original)
> +++ llvm/trunk/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp Thu Mar 12
> 06:00:48 2015
> @@ -104,7 +104,7 @@ namespace {
> bool MatchWrapper(SDValue N, MSP430ISelAddressMode &AM);
> bool MatchAddressBase(SDValue N, MSP430ISelAddressMode &AM);
>
> - bool SelectInlineAsmMemoryOperand(const SDValue &Op, char
> ConstraintCode,
> + bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned
> ConstraintID,
> std::vector<SDValue> &OutOps)
> override;
>
> // Include the pieces autogenerated from the target description.
> @@ -280,12 +280,12 @@ bool MSP430DAGToDAGISel::SelectAddr(SDVa
> }
>
> bool MSP430DAGToDAGISel::
> -SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
> +SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned
> ConstraintID,
> std::vector<SDValue> &OutOps) {
> SDValue Op0, Op1;
> - switch (ConstraintCode) {
> + switch (ConstraintID) {
> default: return true;
> - case 'm': // memory
> + case InlineAsm::Constraint_m: // memory
> if (!SelectAddr(Op, Op0, Op1))
> return true;
> break;
>
> Modified: llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp?rev=232027&r1=232026&r2=232027&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp (original)
> +++ llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp Thu Mar 12
> 06:00:48 2015
> @@ -230,9 +230,10 @@ SDNode* MipsDAGToDAGISel::Select(SDNode
> }
>
> bool MipsDAGToDAGISel::
> -SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
> +SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned
> ConstraintID,
> std::vector<SDValue> &OutOps) {
> - assert(ConstraintCode == 'm' && "unexpected asm memory
> constraint");
> + assert(ConstraintID == InlineAsm::Constraint_m &&
> + "unexpected asm memory constraint");
> OutOps.push_back(Op);
> return false;
> }
>
> Modified: llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.h
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.h?rev=232027&r1=232026&r2=232027&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.h (original)
> +++ llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.h Thu Mar 12 06:00:48
> 2015
> @@ -125,7 +125,7 @@ private:
> virtual void processFunctionAfterISel(MachineFunction &MF) = 0;
>
> bool SelectInlineAsmMemoryOperand(const SDValue &Op,
> - char ConstraintCode,
> + unsigned ConstraintID,
> std::vector<SDValue> &OutOps)
> override;
> };
> }
>
> Modified: llvm/trunk/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp?rev=232027&r1=232026&r2=232027&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp (original)
> +++ llvm/trunk/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp Thu Mar 12
> 06:00:48 2015
> @@ -5044,12 +5044,12 @@ bool NVPTXDAGToDAGISel::ChkMemSDNodeAddr
> /// SelectInlineAsmMemoryOperand - Implement addressing mode
> selection for
> /// inline asm expressions.
> bool NVPTXDAGToDAGISel::SelectInlineAsmMemoryOperand(
> - const SDValue &Op, char ConstraintCode, std::vector<SDValue>
> &OutOps) {
> + const SDValue &Op, unsigned ConstraintID, std::vector<SDValue>
> &OutOps) {
> SDValue Op0, Op1;
> - switch (ConstraintCode) {
> + switch (ConstraintID) {
> default:
> return true;
> - case 'm': // memory
> + case InlineAsm::Constraint_m: // memory
> if (SelectDirectAddr(Op, Op0)) {
> OutOps.push_back(Op0);
> OutOps.push_back(CurDAG->getTargetConstant(0, MVT::i32));
>
> Modified: llvm/trunk/lib/Target/NVPTX/NVPTXISelDAGToDAG.h
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/NVPTXISelDAGToDAG.h?rev=232027&r1=232026&r2=232027&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/NVPTX/NVPTXISelDAGToDAG.h (original)
> +++ llvm/trunk/lib/Target/NVPTX/NVPTXISelDAGToDAG.h Thu Mar 12
> 06:00:48 2015
> @@ -48,7 +48,7 @@ public:
> const NVPTXSubtarget *Subtarget;
>
> bool SelectInlineAsmMemoryOperand(const SDValue &Op,
> - char ConstraintCode,
> + unsigned ConstraintID,
> std::vector<SDValue> &OutOps)
> override;
> private:
> // Include the pieces autogenerated from the target description.
>
> Modified: llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp?rev=232027&r1=232026&r2=232027&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp (original)
> +++ llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Thu Mar 12
> 06:00:48 2015
> @@ -186,7 +186,7 @@ namespace {
> /// register can be improved, but it is wrong to substitute
> Reg+Reg for
> /// Reg in an asm, because the load or store opcode would have
> to change.
> bool SelectInlineAsmMemoryOperand(const SDValue &Op,
> - char ConstraintCode,
> + unsigned ConstraintID,
> std::vector<SDValue> &OutOps)
> override {
> // We need to make sure that this one operand does not end up
> in r0
> // (because we might end up lowering this as 0(%op)).
>
> Modified: llvm/trunk/lib/Target/Sparc/SparcISelDAGToDAG.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcISelDAGToDAG.cpp?rev=232027&r1=232026&r2=232027&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Sparc/SparcISelDAGToDAG.cpp (original)
> +++ llvm/trunk/lib/Target/Sparc/SparcISelDAGToDAG.cpp Thu Mar 12
> 06:00:48 2015
> @@ -50,7 +50,7 @@ public:
> /// SelectInlineAsmMemoryOperand - Implement addressing mode
> selection for
> /// inline asm expressions.
> bool SelectInlineAsmMemoryOperand(const SDValue &Op,
> - char ConstraintCode,
> + unsigned ConstraintID,
> std::vector<SDValue> &OutOps)
> override;
>
> const char *getPassName() const override {
> @@ -195,12 +195,12 @@ SDNode *SparcDAGToDAGISel::Select(SDNode
> /// inline asm expressions.
> bool
> SparcDAGToDAGISel::SelectInlineAsmMemoryOperand(const SDValue &Op,
> - char ConstraintCode,
> + unsigned
> ConstraintID,
> std::vector<SDValue>
> &OutOps) {
> SDValue Op0, Op1;
> - switch (ConstraintCode) {
> + switch (ConstraintID) {
> default: return true;
> - case 'm': // memory
> + case InlineAsm::Constraint_m: // memory
> if (!SelectADDRrr(Op, Op0, Op1))
> SelectADDRri(Op, Op0, Op1);
> break;
>
> Modified: llvm/trunk/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp?rev=232027&r1=232026&r2=232027&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp (original)
> +++ llvm/trunk/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp Thu Mar 12
> 06:00:48 2015
> @@ -328,7 +328,7 @@ public:
>
> // Override SelectionDAGISel.
> SDNode *Select(SDNode *Node) override;
> - bool SelectInlineAsmMemoryOperand(const SDValue &Op, char
> ConstraintCode,
> + bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned
> ConstraintID,
> std::vector<SDValue> &OutOps)
> override;
>
> // Include the pieces autogenerated from the target description.
> @@ -1129,9 +1129,10 @@ SDNode *SystemZDAGToDAGISel::Select(SDNo
>
> bool SystemZDAGToDAGISel::
> SelectInlineAsmMemoryOperand(const SDValue &Op,
> - char ConstraintCode,
> + unsigned ConstraintID,
> std::vector<SDValue> &OutOps) {
> - assert(ConstraintCode == 'm' && "Unexpected constraint code");
> + assert(ConstraintID == InlineAsm::Constraint_m &&
> + "Unexpected constraint code");
> // Accept addresses with short displacements, which are compatible
> // with Q, R, S and T. But keep the index operand for future
> expansion.
> SDValue Base, Disp, Index;
>
> Modified: llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp?rev=232027&r1=232026&r2=232027&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp Thu Mar 12 06:00:48
> 2015
> @@ -228,7 +228,7 @@ namespace {
> /// SelectInlineAsmMemoryOperand - Implement addressing mode
> selection for
> /// inline asm expressions.
> bool SelectInlineAsmMemoryOperand(const SDValue &Op,
> - char ConstraintCode,
> + unsigned ConstraintID,
> std::vector<SDValue> &OutOps)
> override;
>
> void EmitSpecialCodeForMain();
> @@ -2814,14 +2814,14 @@ SDNode *X86DAGToDAGISel::Select(SDNode *
> }
>
> bool X86DAGToDAGISel::
> -SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
> +SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned
> ConstraintID,
> std::vector<SDValue> &OutOps) {
> SDValue Op0, Op1, Op2, Op3, Op4;
> - switch (ConstraintCode) {
> - case 'o': // offsetable ??
> - case 'v': // not offsetable ??
> + switch (ConstraintID) {
> + case InlineAsm::Constraint_o: // offsetable ??
> + case InlineAsm::Constraint_v: // not offsetable ??
> default: return true;
> - case 'm': // memory
> + case InlineAsm::Constraint_m: // memory
> if (!SelectAddr(nullptr, Op, Op0, Op1, Op2, Op3, Op4))
> return true;
> break;
>
> Modified: llvm/trunk/lib/Target/XCore/XCoreISelDAGToDAG.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreISelDAGToDAG.cpp?rev=232027&r1=232026&r2=232027&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/XCore/XCoreISelDAGToDAG.cpp (original)
> +++ llvm/trunk/lib/Target/XCore/XCoreISelDAGToDAG.cpp Thu Mar 12
> 06:00:48 2015
> @@ -65,7 +65,7 @@ namespace {
> // Complex Pattern Selectors.
> bool SelectADDRspii(SDValue Addr, SDValue &Base, SDValue
> &Offset);
>
> - bool SelectInlineAsmMemoryOperand(const SDValue &Op, char
> ConstraintCode,
> + bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned
> ConstraintID,
> std::vector<SDValue> &OutOps)
> override;
>
> const char *getPassName() const override {
> @@ -108,12 +108,12 @@ bool XCoreDAGToDAGISel::SelectADDRspii(S
> }
>
> bool XCoreDAGToDAGISel::
> -SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
> +SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned
> ConstraintID,
> std::vector<SDValue> &OutOps) {
> SDValue Reg;
> - switch (ConstraintCode) {
> + switch (ConstraintID) {
> default: return true;
> - case 'm': // Memory.
> + case InlineAsm::Constraint_m: // Memory.
> switch (Op.getOpcode()) {
> default: return true;
> case XCoreISD::CPRelativeWrapper:
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>
--
Hal Finkel
Assistant Computational Scientist
Leadership Computing Facility
Argonne National Laboratory
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