[PATCH] [TableGen] Do not link Predicate conditions if the 1st one wasn't emitted.

[Toma Tabacu]

When generating the Predicate checks for the Disassembler, do not try to logically link together
the 1st and 2nd generated Predicate conditions, if for the 1st Predicate we didn't actually emit anything.

This will enable us to have Predicates in any order we want.

http://reviews.llvm.org/D8294

Files:
  test/TableGen/PredicateOrderDisasm.td
  utils/TableGen/FixedLenDecoderEmitter.cpp

Index: test/TableGen/PredicateOrderDisasm.td
===================================================================
--- /dev/null
+++ test/TableGen/PredicateOrderDisasm.td
@@ -0,0 +1,37 @@
+// RUN: llvm-tblgen -gen-disassembler -I %p/../../include %s | FileCheck %s
+
+// Check that we don't try to logically link together the 1st and 2nd generated
+// Predicate conditions if for the 1st Predicate we didn't actually emit
+// anything.
+
+// In the example below, Pred1 is not an AssemblerPredicate, while Pred2 is.
+// When doing -gen-disassembler, we only care about AssemblerPredicate's, so
+// we don't emit the condition for Pred1, but we would still try to link the
+// condition for Pred2 with the (inexistent) one for Pred1 by emitting "&&".
+// This would result in invalid code being generated.
+
+include "llvm/Target/Target.td"
+
+def archInstrInfo : InstrInfo { }
+
+def arch : Target {
+  let InstructionSet = archInstrInfo;
+}
+
+def Pred1 : Predicate<"Condition1">;
+def Pred2 : Predicate<"Condition2">,
+            AssemblerPredicate<"AssemblerCondition2">;
+
+def foo : Instruction {
+  let Size = 2;
+  let OutOperandList = (outs);
+  let InOperandList = (ins);
+  field bits<16> Inst;
+  let Inst = 0xAAAA;
+  let AsmString = "foo";
+  field bits<16> SoftFail = 0;
+  // This is the important bit:
+  let Predicates = [Pred1, Pred2];
+}
+
+// CHECK-NOT: ( && (Bits & arch::AssemblerCondition2))
Index: utils/TableGen/FixedLenDecoderEmitter.cpp
===================================================================
--- utils/TableGen/FixedLenDecoderEmitter.cpp
+++ utils/TableGen/FixedLenDecoderEmitter.cpp
@@ -1112,6 +1112,7 @@
                                        unsigned Opc) const {
   ListInit *Predicates =
     AllInstructions[Opc]->TheDef->getValueAsListInit("Predicates");
+  bool IsFirstEmission = true;
   for (unsigned i = 0; i < Predicates->getSize(); ++i) {
     Record *Pred = Predicates->getElementAsRecord(i);
     if (!Pred->getValue("AssemblerMatcherPredicate"))
@@ -1122,7 +1123,7 @@
     if (!P.length())
       continue;
 
-    if (i != 0)
+    if (!IsFirstEmission)
       o << " && ";
 
     StringRef SR(P);
@@ -1133,6 +1134,7 @@
       pairs = pairs.second.split(',');
     }
     emitSinglePredicateMatch(o, pairs.first, Emitter->PredicateNamespace);
+    IsFirstEmission = false;
   }
   return Predicates->getSize() > 0;
 }

EMAIL PREFERENCES
  http://reviews.llvm.org/settings/panel/emailpreferences/
-------------- next part --------------
A non-text attachment was scrubbed...
Name: D8294.21839.patch
Type: text/x-patch
Size: 2373 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20150312/5f6b49f6/attachment.bin>