[PATCH] Add infrastructure for support of multiple memory constraints.

[hfinkel at anl.gov]

Thanks for working on this!


================
Comment at: include/llvm/Target/TargetLowering.h:2597
@@ -2596,1 +2596,3 @@
 
+  virtual unsigned getInlineAsmMemConstraint(const std::string ConstraintCode) const {
+    // FIXME: Actually look at the constraint code.
----------------
Line is too long.

================
Comment at: include/llvm/Target/TargetLowering.h:2599
@@ +2598,3 @@
+    // FIXME: Actually look at the constraint code.
+    //        This currently matches the existing behaviour to keep this change
+    //        non-functional.
----------------
Once this lands, references to "this change" don't make sense. I'd say,

  // Once all targets have been updated, we can use the constraint code.

================
Comment at: lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp:6598
@@ +6597,3 @@
+        if (ConstraintID == InlineAsm::Constraint_Unknown)
+          llvm_unreachable("Failed to convert memory constraint code to constraint id.");
+
----------------
Line too long. Also, why not write?

  assert(ConstraintID != InlineAsm::Constraint_Unknown &&
         "Failed to convert memory constraint code to constraint id.");

(same below too)

================
Comment at: lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp:6749
@@ +6748,3 @@
+        if (ConstraintID == InlineAsm::Constraint_Unknown)
+          llvm_unreachable("Failed to convert memory constraint code to constraint id.");
+
----------------
Line is too long.

================
Comment at: lib/Target/AArch64/AArch64ISelDAGToDAG.cpp:215
@@ -216,1 +214,3 @@
+    const SDValue &Op, unsigned ConstraintID, std::vector<SDValue> &OutOps) {
+  assert(ConstraintID == InlineAsm::Constraint_m && "unexpected asm memory constraint");
   // Require the address to be in a register.  That is safe for all AArch64
----------------
Line too long. (same with this assert in some of the other files too).

http://reviews.llvm.org/D8171

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