[PATCH] CodeGenPrepare: Avoid and/or i1 in select conditions.

[hfinkel at anl.gov]

REPOSITORY
  rL LLVM

================
Comment at: include/llvm/Target/TargetLowering.h:1113
@@ +1112,3 @@
+    // Only do the transform if the value fits into one register.
+    return getNumRegisters(Context, VT) <= 1;
+  }
----------------
MatzeB wrote:
> hfinkel wrote:
> > > Tweak the callback to not cover types that need multiple registers as those will typically be broken down into multiple select-like instructions.
> > 
> > Normally, to check this condition, we'd just use:
> >   isTypeLegal(VT)
> > 
> But that will report false for types like i8 and i16 on many target even though we will end up with a single select like instruction. What about?
> 
>     LegalizeTypeAction Action = getTypeAction(Context, VT);
>     return Action != TypeExpandInteger && Action != TYpeExpandFloat &&
>       Action != TypeSplitVector
> 
Sure; seems reasonable to me. Go ahead whenever you're ready.

http://reviews.llvm.org/D7622

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