[PATCH] CodeGenPrepare: Avoid and/or i1 in select conditions.
hfinkel at anl.gov
hfinkel at anl.gov
Wed Mar 4 10:54:50 PST 2015
In http://reviews.llvm.org/D7622#134397, @MatzeB wrote:
> Thanks for the review Hal, the new version uses hasMultipleConditionRegisters() as default.
>
> > ================
>
> > Comment at: lib/CodeGen/SelectionDAG/DAGCombiner.cpp:4714
>
> > @@ +4713,3 @@
>
> > + const SDNode *Node = Value.getNode();
>
> > + for (auto I = Node->use_begin(), E = Node->use_end(); I != E; ++I) {
>
> > + const SDUse &Use = I.getUse();
>
> >
>
> > - Range-based for?
>
>
> A range based for prohibits me from doing I.getUse() above as I can't access the iterator anymore.
Ah, alright.
REPOSITORY
rL LLVM
================
Comment at: include/llvm/Target/TargetLowering.h:1094
@@ +1093,3 @@
+ virtual bool shouldNormalizeToSelectSequence() const {
+ // If SELECTs are expensive then we should not do this.
+ return !hasMultipleConditionRegisters();
----------------
You should update the comment also. I'd say:
// If a target has multiple condition registers, then it likely has logical operations on those registers.
================
Comment at: lib/CodeGen/SelectionDAG/DAGCombiner.cpp:4716
@@ +4715,3 @@
+ const SDUse &Use = I.getUse();
+ if (Use != Value)
+ continue;
----------------
Don't you want to check that it is used as the condition operand of the select?
http://reviews.llvm.org/D7622
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