[PATCH] [DagCombiner] Allow shuffles to merge through bitcasts

[Quentin Colombet]

REPOSITORY
  rL LLVM

================
Comment at: lib/CodeGen/SelectionDAG/DAGCombiner.cpp:11923
@@ +11922,3 @@
+      if (SVT.bitsLT(InnerSVT)) {
+        assert(0 == (InnerSVT.getSizeInBits() % SVT.getSizeInBits()) &&
+               "Illegal Shuffle Mask Scale");
----------------
I don’t think this assert stands in a pre legalization world.
This is perfectly legal AFAIK to do something like this:
bitcast <4 x i48> %a to <6 x i32>

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Comment at: test/CodeGen/X86/vector-shuffle-128-v16.ll:1352
@@ +1351,3 @@
+  %bitcast32 = bitcast <16 x i8> %shuffle8 to <4 x float>
+  %shuffle32 = shufflevector <4 x float> %bitcast32, <4 x float> zeroinitializer, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
+  %bitcast16 = bitcast <4 x float> %shuffle32 to <8 x i16>
----------------
Do you actually need the zero initializer here?
“undef" should do the trick and would make more obvious why you patch apply.

================
Comment at: test/CodeGen/X86/vector-shuffle-128-v2.ll:827
@@ +826,3 @@
+  %bitcast32 = bitcast <2 x double> %shuffle64 to <4 x float>
+  %shuffle32 = shufflevector <4 x float> %bitcast32, <4 x float> zeroinitializer, <4 x i32> <i32 2, i32 3, i32 0, i32 1>
+  %bitcast64 = bitcast <4 x float> %shuffle32 to <2 x double>
----------------
Ditto.

================
Comment at: test/CodeGen/X86/vector-shuffle-128-v4.ll:1589
@@ +1588,3 @@
+  %bitcast64 = bitcast <4 x i32> %shuffle32 to <2 x double>
+  %shuffle64 = shufflevector <2 x double> %bitcast64, <2 x double> zeroinitializer, <2 x i32> <i32 1, i32 0>
+  %bitcast32 = bitcast <2 x double> %shuffle64 to <4 x i32>
----------------
Ditto.

http://reviews.llvm.org/D7939

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