[PATCH] Add logical ops to Mips fast-isel

[reed kotler]

================
Comment at: test/CodeGen/Mips/Fast-ISel/logopm.ll:582
@@ +581,3 @@
+; CHECK:        addu    $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
+; CHECK-DAG:    lw      $[[US_ADDR:[0-9]+]], %got(us)($[[REG_GP]])
+; CHECK-DAG:    lw      $[[US1_ADDR:[0-9]+]], %got(us1)($[[REG_GP]])
----------------
echristo wrote:
> Any reason for the CHECK-DAG here? Are you seeing ordering issues between mips32 and mip32r2 here?
The problem is that the load of US1_ADDR could be moved ahead of the load to US_ADDR. It's not happening today but there is no reason why the reordering could not occur and then it will create an unnecessary make check failure. I try and make heavy use of CHECK-DAG in order to ensure that only changes to the Mips target code generator will affect these tests and not changes to target independent code passes.

http://reviews.llvm.org/D6599

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