[PATCH] [mips] Remove redundant periods from -mattr=help descriptions for MIPS.

[Toma Tabacu]

Hi dsanders,

Also fixes an infringement of the 80-column limit rule.

http://reviews.llvm.org/D7910

Files:
  lib/Target/Mips/Mips.td

Index: lib/Target/Mips/Mips.td
===================================================================
--- lib/Target/Mips/Mips.td
+++ lib/Target/Mips/Mips.td
@@ -58,22 +58,22 @@
 //===----------------------------------------------------------------------===//
 
 def FeatureNoABICalls  : SubtargetFeature<"noabicalls", "NoABICalls", "true",
-                                "Disable SVR4-style position-independent code.">;
+                                "Disable SVR4-style position-independent code">;
 def FeatureGP64Bit     : SubtargetFeature<"gp64", "IsGP64bit", "true",
-                                "General Purpose Registers are 64-bit wide.">;
+                                "General Purpose Registers are 64-bit wide">;
 def FeatureFP64Bit     : SubtargetFeature<"fp64", "IsFP64bit", "true",
-                                "Support 64-bit FP registers.">;
+                                "Support 64-bit FP registers">;
 def FeatureFPXX        : SubtargetFeature<"fpxx", "IsFPXX", "true",
-                                "Support for FPXX.">;
+                                "Support for FPXX">;
 def FeatureNaN2008     : SubtargetFeature<"nan2008", "IsNaN2008bit", "true",
-                                "IEEE 754-2008 NaN encoding.">;
+                                "IEEE 754-2008 NaN encoding">;
 def FeatureSingleFloat : SubtargetFeature<"single-float", "IsSingleFloat",
                                 "true", "Only supports single precision float">;
 def FeatureNoOddSPReg  : SubtargetFeature<"nooddspreg", "UseOddSPReg", "false",
                               "Disable odd numbered single-precision "
                               "registers">;
 def FeatureVFPU        : SubtargetFeature<"vfpu", "HasVFPU",
-                                "true", "Enable vector FPU instructions.">;
+                                "true", "Enable vector FPU instructions">;
 def FeatureMips1       : SubtargetFeature<"mips1", "MipsArchVersion", "Mips1",
                                 "Mips I ISA Support [highly experimental]">;
 def FeatureMips2       : SubtargetFeature<"mips2", "MipsArchVersion", "Mips2",

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