[llvm] r230634 - [X86][Haswell][SchedModel] Fix WriteMULm latency.

Michael Kuperstein michael.m.kuperstein at intel.com
Thu Feb 26 06:30:09 PST 2015


Author: mkuper
Date: Thu Feb 26 08:30:09 2015
New Revision: 230634

URL: http://llvm.org/viewvc/llvm-project?rev=230634&view=rev
Log:
[X86][Haswell][SchedModel] Fix WriteMULm latency.

The latency for the WriteMULm class was set to 4, which is actually lower than the latency for WriteMULr (5). 
A better estimate would be 4 added to WriteMULr, that is, 9.

Modified:
    llvm/trunk/lib/Target/X86/X86SchedHaswell.td

Modified: llvm/trunk/lib/Target/X86/X86SchedHaswell.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedHaswell.td?rev=230634&r1=230633&r2=230634&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedHaswell.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedHaswell.td Thu Feb 26 08:30:09 2015
@@ -1895,7 +1895,7 @@ def : InstRW<[WriteMULr], (instregex "(V
 
 // x,m / v,v,m.
 def WriteMULm : SchedWriteRes<[HWPort01, HWPort23]> {
-  let Latency = 4;
+  let Latency = 9;
   let NumMicroOps = 2;
   let ResourceCycles = [1, 1];
 }





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