[llvm] r230334 - [x32] x32 should use ebx as the base pointer.

[H.J. Lu]

Hi Michael,

You also need to update X86RegisterInfo::getReservedRegs

  // Set the base-pointer register and its aliases as reserved if needed.
  if (hasBasePointer(MF)) {
    CallingConv::ID CC = MF.getFunction()->getCallingConv();
    const uint32_t* RegMask = getCallPreservedMask(CC);
    if (MachineOperand::clobbersPhysReg(RegMask, getBaseRegister()))
      report_fatal_error(
        "Stack realignment in presence of dynamic allocas is not supported with"
        "this calling convention.");

    for (MCSubRegIterator I(getBaseRegister(), this, /*IncludeSelf=*/true);
         I.isValid(); ++I)
      Reserved.set(*I);
  }

Otherwise, RBX won't be reserved when EBX is used as  the base-pointer
register for x32.  You can either check EBX explicilly or use
getX86SubSuperRegister.

Thanks.


H.J.

On Tue, Feb 24, 2015 at 7:27 AM, Michael Kuperstein
<michael.m.kuperstein at intel.com> wrote:
> Author: mkuper
> Date: Tue Feb 24 09:27:13 2015
> New Revision: 230334
>
> URL: http://llvm.org/viewvc/llvm-project?rev=230334&view=rev
> Log:
> [x32] x32 should use ebx as the base pointer.
>
> This fixes the original issue in PR22655, but not the secondary one.
>
> Added:
>     llvm/trunk/test/CodeGen/X86/x86-64-baseptr.ll
> Modified:
>     llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp
>
> Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp?rev=230334&r1=230333&r2=230334&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp Tue Feb 24 09:27:13 2015
> @@ -66,21 +66,22 @@ X86RegisterInfo::X86RegisterInfo(const X
>    Is64Bit = Subtarget.is64Bit();
>    IsWin64 = Subtarget.isTargetWin64();
>
> +  // Use a callee-saved register as the base pointer.  These registers must
> +  // not conflict with any ABI requirements.  For example, in 32-bit mode PIC
> +  // requires GOT in the EBX register before function calls via PLT GOT pointer.
>    if (Is64Bit) {
>      SlotSize = 8;
> -    StackPtr = (Subtarget.isTarget64BitLP64() || Subtarget.isTargetNaCl64()) ?
> -        X86::RSP : X86::ESP;
> -    FramePtr = (Subtarget.isTarget64BitLP64() || Subtarget.isTargetNaCl64()) ?
> -        X86::RBP : X86::EBP;
> +    bool Use64BitReg =
> +      Subtarget.isTarget64BitLP64() || Subtarget.isTargetNaCl64();
> +    StackPtr = Use64BitReg ? X86::RSP : X86::ESP;
> +    FramePtr = Use64BitReg ? X86::RBP : X86::EBP;
> +    BasePtr = Use64BitReg ? X86::RBX : X86::EBX;
>    } else {
>      SlotSize = 4;
>      StackPtr = X86::ESP;
>      FramePtr = X86::EBP;
> +    BasePtr = X86::ESI;
>    }
> -  // Use a callee-saved register as the base pointer.  These registers must
> -  // not conflict with any ABI requirements.  For example, in 32-bit mode PIC
> -  // requires GOT in the EBX register before function calls via PLT GOT pointer.
> -  BasePtr = Is64Bit ? X86::RBX : X86::ESI;
>  }
>
>  bool
>
> Added: llvm/trunk/test/CodeGen/X86/x86-64-baseptr.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/x86-64-baseptr.ll?rev=230334&view=auto
> ==============================================================================
> --- llvm/trunk/test/CodeGen/X86/x86-64-baseptr.ll (added)
> +++ llvm/trunk/test/CodeGen/X86/x86-64-baseptr.ll Tue Feb 24 09:27:13 2015
> @@ -0,0 +1,26 @@
> +; RUN: llc -mtriple=x86_64-pc-linux -force-align-stack -stack-alignment=32 < %s | FileCheck %s
> +; RUN: llc -mtriple=x86_64-pc-linux-gnux32 -force-align-stack -stack-alignment=32 < %s | FileCheck -check-prefix=X32ABI %s
> +; This should run with NaCl as well ( -mtriple=x86_64-pc-nacl ) but currently doesn't due to PR22655
> +
> +; Make sure the correct register gets set up as the base pointer
> +; This should be rbx for x64 and 64-bit NaCl and ebx for x32
> +; CHECK-LABEL: base
> +; CHECK: subq $32, %rsp
> +; CHECK: movq %rsp, %rbx
> +; X32ABI-LABEL: base
> +; X32ABI: subl $32, %esp
> +; X32ABI: movl %esp, %ebx
> +; NACL-LABEL: base
> +; NACL: subq $32, %rsp
> +; NACL: movq %rsp, %rbx
> +
> +declare i32 @helper() nounwind
> +define void @base() #0 {
> +entry:
> +  %k = call i32 @helper()
> +  %a = alloca i32, i32 %k, align 4
> +  store i32 0, i32* %a, align 4
> +  ret void
> +}
> +
> +attributes #0 = { nounwind uwtable "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"}
>
>
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-- 
H.J.