[PATCH] [Mips][Assembler]Enable multiple and add instructions for mips64 target
Daniel Sanders
daniel.sanders at imgtec.com
Tue Feb 24 07:00:11 PST 2015
> Multiple and add instructions for Mips have been defined to request mips32r2 platform, although they
> are request on mips64, which makes them available for mips4 and mips5 as well. Assembly of those
> instructions currently reports error for mips64platforms. This patch fixes the requested features and
> updates the corresponding test files.
The English here is quite difficult to understand but if I understand correctly then these instructions are currently available in mips32r2/mips64r2 and later but should also be available in mips4, mips5, and mips64. Looking at the docs, I agree.
<hr class="remarkup-hr" />
LGTM with the test cases sorted properly and the missing 64-NONAN case added.
One thing to mention is that we can't use madd.[ds] or msub.[ds] for the R8000 series without fast-math being enabled. This is because these processors do a fused multiply add/sub instead of rounding the intermediate as per IEEE754. Given that we only support a generic MIPS-IV this isn't a problem for now but we should note this with a FIXME somewhere.
================
Comment at: test/CodeGen/Mips/fmadd1.ll:166-168
@@ -166,6 +165,5 @@
-; 64-DAG: mul.s $[[T1:f[0-9]+]], $f12, $f13
-; 64-DAG: sub.s $[[T2:f[0-9]+]], $[[T1]], $f14
-; 64-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
-; 64-DAG: sub.s $f0, $[[T2]], $[[T1]]
+; 64-NAN: msub.s $[[T0:f[0-9]+]], $f14, $f12, $f13
+; 64-NAN: mtc1 $zero, $[[T1:f[0-9]+]]
+; 64-NAN: sub.s $f0, $[[T1]], $[[T0]]
----------------
You need to add the 64-NONAN case too.
================
Comment at: test/MC/Mips/mips4/valid.s:141-149
@@ -140,3 +140,11 @@
mflo $s1
+ madd.d $f18, $f22, $f26, $f20 # encoding: [0x4e,0xd4,0xd4,0xa1]
+ madd.s $f2, $f30, $f18, $f24 # encoding: [0x4f,0xd8,0x90,0xa0]
+ msub.d $f10, $f2, $f30, $f18 # encoding: [0x4c,0x52,0xf2,0xa9]
+ msub.s $f12, $f18, $f10, $f16 # encoding: [0x4e,0x50,0x53,0x28]
+ nmadd.d $f18, $f8, $f14, $f20 # encoding: [0x4d,0x14,0x74,0xb1]
+ nmadd.s $f0, $f4, $f24, $f12 # encoding: [0x4c,0x8c,0xc0,0x30]
+ nmsub.d $f30, $f8, $f16, $f30 # encoding: [0x4d,0x1e,0x87,0xb9]
+ nmsub.s $f0, $f24, $f20, $f4 # encoding: [0x4f,0x04,0xa0,0x38]
mov.d $f20,$f14
mov.s $f2,$f27
----------------
The instructions in this file should be sorted alphabetically.
================
Comment at: test/MC/Mips/mips5/valid.s:142-149
@@ -141,2 +141,10 @@
mflo $s1
+ madd.d $f18, $f22, $f26, $f20 # encoding: [0x4e,0xd4,0xd4,0xa1]
+ madd.s $f2, $f30, $f18, $f24 # encoding: [0x4f,0xd8,0x90,0xa0]
+ msub.d $f10, $f2, $f30, $f18 # encoding: [0x4c,0x52,0xf2,0xa9]
+ msub.s $f12, $f18, $f10, $f16 # encoding: [0x4e,0x50,0x53,0x28]
+ nmadd.d $f18, $f8, $f14, $f20 # encoding: [0x4d,0x14,0x74,0xb1]
+ nmadd.s $f0, $f4, $f24, $f12 # encoding: [0x4c,0x8c,0xc0,0x30]
+ nmsub.d $f30, $f8, $f16, $f30 # encoding: [0x4d,0x1e,0x87,0xb9]
+ nmsub.s $f0, $f24, $f20, $f4 # encoding: [0x4f,0x04,0xa0,0x38]
mov.d $f20,$f14
----------------
The instructions in this file should be sorted alphabetically.
================
Comment at: test/MC/Mips/mips64/valid.s:147-154
@@ -146,2 +146,10 @@
maddu $24,$s2
+ madd.d $f18, $f22, $f26, $f20 # encoding: [0x4e,0xd4,0xd4,0xa1]
+ madd.s $f2, $f30, $f18, $f24 # encoding: [0x4f,0xd8,0x90,0xa0]
+ msub.d $f10, $f2, $f30, $f18 # encoding: [0x4c,0x52,0xf2,0xa9]
+ msub.s $f12, $f18, $f10, $f16 # encoding: [0x4e,0x50,0x53,0x28]
+ nmadd.d $f18, $f8, $f14, $f20 # encoding: [0x4d,0x14,0x74,0xb1]
+ nmadd.s $f0, $f4, $f24, $f12 # encoding: [0x4c,0x8c,0xc0,0x30]
+ nmsub.d $f30, $f8, $f16, $f30 # encoding: [0x4d,0x1e,0x87,0xb9]
+ nmsub.s $f0, $f24, $f20, $f4 # encoding: [0x4f,0x04,0xa0,0x38]
mfc0 $a2,$14,1
----------------
The instructions in this file should be sorted alphabetically.
http://reviews.llvm.org/D7749
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