[llvm] r229841 - Reverting r229831 due to multiple ARM/PPC/MIPS build-bot failures.

Kuperstein, Michael M michael.m.kuperstein at intel.com
Mon Feb 23 06:38:29 PST 2015


It was an out-of-memory error during compilation.

Don't remember which file, unfortunately, and I didn't save the log.
It may have been lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp (this was the file that caused the AArch64 miscompile), but I'm not entirely sure.

-----Original Message-----
From: Daniel Sanders [mailto:Daniel.Sanders at imgtec.com] 
Sent: Monday, February 23, 2015 16:05
To: Kuperstein, Michael M; llvm-commits at cs.uiuc.edu
Subject: RE: [llvm] r229841 - Reverting r229831 due to multiple ARM/PPC/MIPS build-bot failures.

> MIPS also had a stage1 miscompile:
> http://lab.llvm.org:8011/builders/clang-cmake-
> mips/builds/2924/steps/build%20stage%201/logs/stdio
> It's not clear from the log what the host compiler is, but I'm guessing it's also
> GCC.

The buildslave information at http://lab.llvm.org:8011/buildslaves/mips-kl-m001 has the version numbers for the main tools. It's gcc 4.9.1-1 from the Debian Jessie (mips) repositories.

Unfortunately, the buildbot has already purged the logs for this build. Do you happen to know what the miscompile was?

> -----Original Message-----
> From: llvm-commits-bounces at cs.uiuc.edu [mailto:llvm-commits-
> bounces at cs.uiuc.edu] On Behalf Of Kuperstein, Michael M
> Sent: 19 February 2015 11:52
> To: llvm-commits at cs.uiuc.edu
> Subject: RE: [llvm] r229841 - Reverting r229831 due to multiple
> ARM/PPC/MIPS build-bot failures.
> 
> It looks like r229831 caused some rather unexpected failures on several
> platforms.
> 
> On AArch64, it looks like it has exposed a gcc bug:
> http://lab.llvm.org:8011/builders/llvm-aarch64-
> linux/builds/6789/steps/compile/logs/stdio
> 
> MIPS also had a stage1 miscompile:
> http://lab.llvm.org:8011/builders/clang-cmake-
> mips/builds/2924/steps/build%20stage%201/logs/stdio
> It's not clear from the log what the host compiler is, but I'm guessing it's also
> GCC.
> 
> PPC and ARMv7 had timeout stage2 failures:
> http://lab.llvm.org:8011/builders/clang-cmake-armv7-a15-selfhost-
> neon/builds/255/steps/build%20stage%202/logs/stdio
> http://lab.llvm.org:8011/builders/ppc64le-
> clang/builds/824/steps/compile.llvm.stage2/logs/stdio
> 
> Unfortunately, I don't have arm or ppc machines so I can't debug this, and so
> far I haven't seen any failures on x86.
> Could anyone help with solving these?
> 
> Thanks,
>    Michael
> 
> -----Original Message-----
> From: llvm-commits-bounces at cs.uiuc.edu [mailto:llvm-commits-
> bounces at cs.uiuc.edu] On Behalf Of Michael Kuperstein
> Sent: Thursday, February 19, 2015 13:38
> To: llvm-commits at cs.uiuc.edu
> Subject: [llvm] r229841 - Reverting r229831 due to multiple ARM/PPC/MIPS
> build-bot failures.
> 
> Author: mkuper
> Date: Thu Feb 19 05:38:11 2015
> New Revision: 229841
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=229841&view=rev
> Log:
> Reverting r229831 due to multiple ARM/PPC/MIPS build-bot failures.
> 
> Modified:
>     llvm/trunk/include/llvm/MC/MCInstPrinter.h
>     llvm/trunk/include/llvm/MC/MCInstrDesc.h
>     llvm/trunk/include/llvm/MC/MCSubtargetInfo.h
>     llvm/trunk/include/llvm/MC/SubtargetFeature.h
>     llvm/trunk/lib/MC/MCSubtargetInfo.cpp
>     llvm/trunk/lib/MC/SubtargetFeature.cpp
>     llvm/trunk/lib/Target/AArch64/Utils/AArch64BaseInfo.cpp
>     llvm/trunk/lib/Target/AArch64/Utils/AArch64BaseInfo.h
>     llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
>     llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
>     llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp
>     llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
>     llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
>     llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
>     llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.h
>     llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
>     llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
>     llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
>     llvm/trunk/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
>     llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
>     llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp
>     llvm/trunk/lib/Target/R600/MCTargetDesc/AMDGPUMCTargetDesc.cpp
>     llvm/trunk/lib/Target/R600/MCTargetDesc/R600MCCodeEmitter.cpp
>     llvm/trunk/lib/Target/Sparc/InstPrinter/SparcInstPrinter.cpp
>     llvm/trunk/lib/Target/X86/AsmParser/X86AsmInstrumentation.cpp
>     llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp
>     llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.cpp
>     llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp
>     llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
>     llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp
>     llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.cpp
>     llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp
>     llvm/trunk/utils/TableGen/SubtargetEmitter.cpp
> 
> Modified: llvm/trunk/include/llvm/MC/MCInstPrinter.h
> URL: http://llvm.org/viewvc/llvm-
> project/llvm/trunk/include/llvm/MC/MCInstPrinter.h?rev=229841&r1=22984
> 0&r2=229841&view=diff
> ==========================================================
> ====================
> --- llvm/trunk/include/llvm/MC/MCInstPrinter.h (original)
> +++ llvm/trunk/include/llvm/MC/MCInstPrinter.h Thu Feb 19 05:38:11 2015
> @@ -10,7 +10,6 @@
>  #ifndef LLVM_MC_MCINSTPRINTER_H
>  #define LLVM_MC_MCINSTPRINTER_H
> 
> -#include "llvm/MC/SubtargetFeature.h"
>  #include "llvm/Support/DataTypes.h"
>  #include "llvm/Support/Format.h"
> 
> @@ -42,7 +41,7 @@ protected:
>    const MCRegisterInfo &MRI;
> 
>    /// The current set of available features.
> -  FeatureBitset AvailableFeatures;
> +  uint64_t AvailableFeatures;
> 
>    /// True if we are printing marked up assembly.
>    bool UseMarkup;
> @@ -59,7 +58,7 @@ public:
>    MCInstPrinter(const MCAsmInfo &mai, const MCInstrInfo &mii,
>                  const MCRegisterInfo &mri)
>      : CommentStream(nullptr), MAI(mai), MII(mii), MRI(mri),
> -      AvailableFeatures(), UseMarkup(0), PrintImmHex(0),
> +      AvailableFeatures(0), UseMarkup(0), PrintImmHex(0),
>        PrintHexStyle(HexStyle::C) {}
> 
>    virtual ~MCInstPrinter();
> @@ -79,8 +78,8 @@ public:
>    /// printRegName - Print the assembler register name.
>    virtual void printRegName(raw_ostream &OS, unsigned RegNo) const;
> 
> -  const FeatureBitset& getAvailableFeatures() const { return
> AvailableFeatures; }
> -  void setAvailableFeatures(const FeatureBitset& Value) { AvailableFeatures
> = Value; }
> +  uint64_t getAvailableFeatures() const { return AvailableFeatures; }
> +  void setAvailableFeatures(uint64_t Value) { AvailableFeatures = Value; }
> 
>    bool getUseMarkup() const { return UseMarkup; }
>    void setUseMarkup(bool Value) { UseMarkup = Value; }
> 
> Modified: llvm/trunk/include/llvm/MC/MCInstrDesc.h
> URL: http://llvm.org/viewvc/llvm-
> project/llvm/trunk/include/llvm/MC/MCInstrDesc.h?rev=229841&r1=229840
> &r2=229841&view=diff
> ==========================================================
> ====================
> --- llvm/trunk/include/llvm/MC/MCInstrDesc.h (original)
> +++ llvm/trunk/include/llvm/MC/MCInstrDesc.h Thu Feb 19 05:38:11 2015
> @@ -150,7 +150,7 @@ public:
>    const uint16_t *ImplicitUses;  // Registers implicitly read by this instr
>    const uint16_t *ImplicitDefs;  // Registers implicitly defined by this instr
>    const MCOperandInfo *OpInfo;   // 'NumOperands' entries about operands
> -  FeatureBitset   DeprecatedFeatureMask; // Feature bits that this is
> deprecated on, if any
> +  uint64_t DeprecatedFeatureMask;// Feature bits that this is deprecated
> on, if any
>    // A complex method to determine is a certain is deprecated or not, and
> return
>    // the reason for deprecation.
>    bool (*ComplexDeprecationInfo)(MCInst &, MCSubtargetInfo &, std::string
> &);
> @@ -173,7 +173,7 @@ public:
>                           std::string &Info) const {
>      if (ComplexDeprecationInfo)
>        return ComplexDeprecationInfo(MI, STI, Info);
> -    if ((STI.getFeatureBits() & DeprecatedFeatureMask).any()) {
> +    if ((DeprecatedFeatureMask & STI.getFeatureBits()) != 0) {
>        // FIXME: it would be nice to include the subtarget feature here.
>        Info = "deprecated";
>        return true;
> 
> Modified: llvm/trunk/include/llvm/MC/MCSubtargetInfo.h
> URL: http://llvm.org/viewvc/llvm-
> project/llvm/trunk/include/llvm/MC/MCSubtargetInfo.h?rev=229841&r1=22
> 9840&r2=229841&view=diff
> ==========================================================
> ====================
> --- llvm/trunk/include/llvm/MC/MCSubtargetInfo.h (original)
> +++ llvm/trunk/include/llvm/MC/MCSubtargetInfo.h Thu Feb 19 05:38:11
> 2015
> @@ -42,7 +42,7 @@ class MCSubtargetInfo {
>    const InstrStage *Stages;            // Instruction itinerary stages
>    const unsigned *OperandCycles;       // Itinerary operand cycles
>    const unsigned *ForwardingPaths;     // Forwarding paths
> -  FeatureBitset FeatureBits;           // Feature bits for current CPU + FS
> +  uint64_t FeatureBits;                // Feature bits for current CPU + FS
> 
>  public:
>    void InitMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS,
> @@ -67,13 +67,13 @@ public:
> 
>    /// getFeatureBits - Return the feature bits.
>    ///
> -  const FeatureBitset& getFeatureBits() const {
> +  uint64_t getFeatureBits() const {
>      return FeatureBits;
>    }
> 
>    /// setFeatureBits - Set the feature bits.
>    ///
> -  void setFeatureBits(FeatureBitset& FeatureBits_) { FeatureBits =
> FeatureBits_; }
> +  void setFeatureBits(uint64_t FeatureBits_) { FeatureBits = FeatureBits_; }
> 
>    /// InitMCProcessorInfo - Set or change the CPU (optionally supplemented
> with
>    /// feature string). Recompute feature bits and scheduling model.
> @@ -84,15 +84,11 @@ public:
> 
>    /// ToggleFeature - Toggle a feature and returns the re-computed feature
>    /// bits. This version does not change the implied bits.
> -  FeatureBitset ToggleFeature(uint64_t FB);
> +  uint64_t ToggleFeature(uint64_t FB);
> 
>    /// ToggleFeature - Toggle a feature and returns the re-computed feature
> -  /// bits. This version does not change the implied bits.
> -  FeatureBitset ToggleFeature(const FeatureBitset& FB);
> -
> -  /// ToggleFeature - Toggle a set of features and returns the re-computed
> -  /// feature bits. This version will also change all implied bits.
> -  FeatureBitset ToggleFeature(StringRef FS);
> +  /// bits. This version will also change all implied bits.
> +  uint64_t ToggleFeature(StringRef FS);
> 
>    /// getSchedModelForCPU - Get the machine model of a CPU.
>    ///
> 
> Modified: llvm/trunk/include/llvm/MC/SubtargetFeature.h
> URL: http://llvm.org/viewvc/llvm-
> project/llvm/trunk/include/llvm/MC/SubtargetFeature.h?rev=229841&r1=22
> 9840&r2=229841&view=diff
> ==========================================================
> ====================
> --- llvm/trunk/include/llvm/MC/SubtargetFeature.h (original)
> +++ llvm/trunk/include/llvm/MC/SubtargetFeature.h Thu Feb 19 05:38:11
> 2015
> @@ -21,29 +21,11 @@
>  #include "llvm/ADT/ArrayRef.h"
>  #include "llvm/ADT/Triple.h"
>  #include "llvm/Support/DataTypes.h"
> -#include <bitset>
> 
>  namespace llvm {
>    class raw_ostream;
>    class StringRef;
> 
> -// A container class for subtarget features.
> -// This is convenient because std::bitset does not have a constructor
> -// with an initializer list of set bits.
> -const unsigned MAX_SUBTARGET_FEATURES = 64;
> -class FeatureBitset : public std::bitset<MAX_SUBTARGET_FEATURES> {
> -public:
> -  // Cannot inherit constructors because it's not supported by VC++..
> -  FeatureBitset() : bitset() {}
> -
> -  FeatureBitset(const bitset<MAX_SUBTARGET_FEATURES>& B) : bitset(B) {}
> -
> -  FeatureBitset(std::initializer_list<unsigned> Init) : bitset() {
> -    for (auto I = Init.begin() , E = Init.end(); I != E; ++I)
> -      set(*I);
> -  }
> -};
> -
>  //===----------------------------------------------------------------------===//
>  ///
>  /// SubtargetFeatureKV - Used to provide key value pairs for feature and
> @@ -52,8 +34,8 @@ public:
>  struct SubtargetFeatureKV {
>    const char *Key;                      // K-V key string
>    const char *Desc;                     // Help descriptor
> -  FeatureBitset Value;                  // K-V integer value
> -  FeatureBitset Implies;                // K-V bit mask
> +  uint64_t Value;                       // K-V integer value
> +  uint64_t Implies;                     // K-V bit mask
> 
>    // Compare routine for std::lower_bound
>    bool operator<(StringRef S) const {
> @@ -100,11 +82,11 @@ public:
> 
>    /// ToggleFeature - Toggle a feature and returns the newly updated feature
>    /// bits.
> -  FeatureBitset ToggleFeature(FeatureBitset Bits, StringRef String,
> +  uint64_t ToggleFeature(uint64_t Bits, StringRef String,
>                           ArrayRef<SubtargetFeatureKV> FeatureTable);
> 
>    /// Get feature bits of a CPU.
> -  FeatureBitset getFeatureBits(StringRef CPU,
> +  uint64_t getFeatureBits(StringRef CPU,
>                            ArrayRef<SubtargetFeatureKV> CPUTable,
>                            ArrayRef<SubtargetFeatureKV> FeatureTable);
> 
> 
> Modified: llvm/trunk/lib/MC/MCSubtargetInfo.cpp
> URL: http://llvm.org/viewvc/llvm-
> project/llvm/trunk/lib/MC/MCSubtargetInfo.cpp?rev=229841&r1=229840&r2
> =229841&view=diff
> ==========================================================
> ====================
> --- llvm/trunk/lib/MC/MCSubtargetInfo.cpp (original)
> +++ llvm/trunk/lib/MC/MCSubtargetInfo.cpp Thu Feb 19 05:38:11 2015
> @@ -63,19 +63,14 @@ MCSubtargetInfo::InitMCSubtargetInfo(Str
> 
>  /// ToggleFeature - Toggle a feature and returns the re-computed feature
>  /// bits. This version does not change the implied bits.
> -FeatureBitset MCSubtargetInfo::ToggleFeature(uint64_t FB) {
> -  FeatureBits.flip(FB);
> -  return FeatureBits;
> -}
> -
> -FeatureBitset MCSubtargetInfo::ToggleFeature(const FeatureBitset &FB) {
> +uint64_t MCSubtargetInfo::ToggleFeature(uint64_t FB) {
>    FeatureBits ^= FB;
>    return FeatureBits;
>  }
> 
>  /// ToggleFeature - Toggle a feature and returns the re-computed feature
>  /// bits. This version will also change all implied bits.
> -FeatureBitset MCSubtargetInfo::ToggleFeature(StringRef FS) {
> +uint64_t MCSubtargetInfo::ToggleFeature(StringRef FS) {
>    SubtargetFeatures Features;
>    FeatureBits = Features.ToggleFeature(FeatureBits, FS, ProcFeatures);
>    return FeatureBits;
> 
> Modified: llvm/trunk/lib/MC/SubtargetFeature.cpp
> URL: http://llvm.org/viewvc/llvm-
> project/llvm/trunk/lib/MC/SubtargetFeature.cpp?rev=229841&r1=229840&r
> 2=229841&view=diff
> ==========================================================
> ====================
> --- llvm/trunk/lib/MC/SubtargetFeature.cpp (original)
> +++ llvm/trunk/lib/MC/SubtargetFeature.cpp Thu Feb 19 05:38:11 2015
> @@ -150,12 +150,12 @@ std::string SubtargetFeatures::getString
>  /// feature, set it.
>  ///
>  static
> -void SetImpliedBits(FeatureBitset &Bits, const SubtargetFeatureKV
> *FeatureEntry,
> +void SetImpliedBits(uint64_t &Bits, const SubtargetFeatureKV
> *FeatureEntry,
>                      ArrayRef<SubtargetFeatureKV> FeatureTable) {
>    for (auto &FE : FeatureTable) {
>      if (FeatureEntry->Value == FE.Value) continue;
> 
> -    if ((FeatureEntry->Implies & FE.Value).any()) {
> +    if (FeatureEntry->Implies & FE.Value) {
>        Bits |= FE.Value;
>        SetImpliedBits(Bits, &FE, FeatureTable);
>      }
> @@ -166,13 +166,12 @@ void SetImpliedBits(FeatureBitset &Bits,
>  /// feature, clear it.
>  ///
>  static
> -void ClearImpliedBits(FeatureBitset &Bits,
> -                      const SubtargetFeatureKV *FeatureEntry,
> +void ClearImpliedBits(uint64_t &Bits, const SubtargetFeatureKV
> *FeatureEntry,
>                        ArrayRef<SubtargetFeatureKV> FeatureTable) {
>    for (auto &FE : FeatureTable) {
>      if (FeatureEntry->Value == FE.Value) continue;
> 
> -    if ((FE.Implies & FeatureEntry->Value).any()) {
> +    if (FE.Implies & FeatureEntry->Value) {
>        Bits &= ~FE.Value;
>        ClearImpliedBits(Bits, &FE, FeatureTable);
>      }
> @@ -181,8 +180,8 @@ void ClearImpliedBits(FeatureBitset &Bit
> 
>  /// ToggleFeature - Toggle a feature and returns the newly updated feature
>  /// bits.
> -FeatureBitset
> -SubtargetFeatures::ToggleFeature(FeatureBitset Bits, StringRef Feature,
> +uint64_t
> +SubtargetFeatures::ToggleFeature(uint64_t Bits, StringRef Feature,
>                                   ArrayRef<SubtargetFeatureKV> FeatureTable) {
> 
>    // Find feature in table.
> @@ -192,6 +191,7 @@ SubtargetFeatures::ToggleFeature(Feature
>    if (FeatureEntry) {
>      if ((Bits & FeatureEntry->Value) == FeatureEntry->Value) {
>        Bits &= ~FeatureEntry->Value;
> +
>        // For each feature that implies this, clear it.
>        ClearImpliedBits(Bits, FeatureEntry, FeatureTable);
>      } else {
> @@ -212,13 +212,13 @@ SubtargetFeatures::ToggleFeature(Feature
> 
>  /// getFeatureBits - Get feature bits a CPU.
>  ///
> -FeatureBitset
> +uint64_t
>  SubtargetFeatures::getFeatureBits(StringRef CPU,
>                                    ArrayRef<SubtargetFeatureKV> CPUTable,
>                                    ArrayRef<SubtargetFeatureKV> FeatureTable) {
> 
>    if (CPUTable.empty() || FeatureTable.empty())
> -    return FeatureBitset();
> +    return 0;
> 
>  #ifndef NDEBUG
>    for (size_t i = 1, e = CPUTable.size(); i != e; ++i) {
> @@ -230,8 +230,7 @@ SubtargetFeatures::getFeatureBits(String
>            "CPU features table is not sorted");
>    }
>  #endif
> -  // Resulting bits
> -  FeatureBitset Bits;
> +  uint64_t Bits = 0;                    // Resulting bits
> 
>    // Check if help is needed
>    if (CPU == "help")
> @@ -248,7 +247,7 @@ SubtargetFeatures::getFeatureBits(String
> 
>        // Set the feature implied by this CPU feature, if any.
>        for (auto &FE : FeatureTable) {
> -        if ((CPUEntry->Value & FE.Value).any())
> +        if (CPUEntry->Value & FE.Value)
>            SetImpliedBits(Bits, &FE, FeatureTable);
>        }
>      } else {
> 
> Modified: llvm/trunk/lib/Target/AArch64/Utils/AArch64BaseInfo.cpp
> URL: http://llvm.org/viewvc/llvm-
> project/llvm/trunk/lib/Target/AArch64/Utils/AArch64BaseInfo.cpp?rev=2298
> 41&r1=229840&r2=229841&view=diff
> ==========================================================
> ====================
> --- llvm/trunk/lib/Target/AArch64/Utils/AArch64BaseInfo.cpp (original)
> +++ llvm/trunk/lib/Target/AArch64/Utils/AArch64BaseInfo.cpp Thu Feb 19
> 05:38:11 2015
> @@ -14,7 +14,6 @@
>  #include "llvm/ADT/APFloat.h"
>  #include "llvm/ADT/SmallVector.h"
>  #include "llvm/ADT/StringExtras.h"
> -#include "llvm/MC/SubtargetFeature.h"
>  #include "llvm/Support/Regex.h"
> 
>  using namespace llvm;
> @@ -246,7 +245,7 @@ const AArch64NamedImmMapper::Mapping AAr
>    {"ich_elsr_el2", ICH_ELSR_EL2}
>  };
> 
> -AArch64SysReg::MRSMapper::MRSMapper(const FeatureBitset
> &FeatureBits)
> +AArch64SysReg::MRSMapper::MRSMapper(uint64_t FeatureBits)
>    : SysRegMapper(FeatureBits) {
>      InstPairs = &MRSPairs[0];
>      NumInstPairs = llvm::array_lengthof(MRSPairs);
> @@ -270,7 +269,7 @@ const AArch64NamedImmMapper::Mapping AAr
>    {"icc_sgi0r_el1", ICC_SGI0R_EL1}
>  };
> 
> -AArch64SysReg::MSRMapper::MSRMapper(const FeatureBitset
> &FeatureBits)
> +AArch64SysReg::MSRMapper::MSRMapper(uint64_t FeatureBits)
>    : SysRegMapper(FeatureBits) {
>      InstPairs = &MSRPairs[0];
>      NumInstPairs = llvm::array_lengthof(MSRPairs);
> @@ -774,7 +773,7 @@ AArch64SysReg::SysRegMapper::fromString(
>    }
> 
>    // Next search for target specific registers
> -  if (FeatureBits[AArch64::ProcCyclone]) {
> +  if (FeatureBits & AArch64::ProcCyclone) {
>      for (unsigned i = 0; i < array_lengthof(CycloneSysRegPairs); ++i) {
>        if (CycloneSysRegPairs[i].Name == NameLower) {
>          Valid = true;
> @@ -824,7 +823,7 @@ AArch64SysReg::SysRegMapper::toString(ui
>    }
> 
>    // Next search for target specific registers
> -  if (FeatureBits[AArch64::ProcCyclone]) {
> +  if (FeatureBits & AArch64::ProcCyclone) {
>      for (unsigned i = 0; i < array_lengthof(CycloneSysRegPairs); ++i) {
>        if (CycloneSysRegPairs[i].Value == Bits) {
>          return CycloneSysRegPairs[i].Name;
> 
> Modified: llvm/trunk/lib/Target/AArch64/Utils/AArch64BaseInfo.h
> URL: http://llvm.org/viewvc/llvm-
> project/llvm/trunk/lib/Target/AArch64/Utils/AArch64BaseInfo.h?rev=229841
> &r1=229840&r2=229841&view=diff
> ==========================================================
> ====================
> --- llvm/trunk/lib/Target/AArch64/Utils/AArch64BaseInfo.h (original)
> +++ llvm/trunk/lib/Target/AArch64/Utils/AArch64BaseInfo.h Thu Feb 19
> 05:38:11 2015
> @@ -26,8 +26,6 @@
> 
>  namespace llvm {
> 
> -class FeatureBitset;
> -
>  inline static unsigned getWRegFromXReg(unsigned Reg) {
>    switch (Reg) {
>    case AArch64::X0: return AArch64::W0;
> @@ -1141,21 +1139,21 @@ namespace AArch64SysReg {
> 
>      const AArch64NamedImmMapper::Mapping *InstPairs;
>      size_t NumInstPairs;
> -    const FeatureBitset &FeatureBits;
> +    uint64_t FeatureBits;
> 
> -    SysRegMapper(const FeatureBitset &FeatureBits) :
> FeatureBits(FeatureBits) { }
> +    SysRegMapper(uint64_t FeatureBits) : FeatureBits(FeatureBits) { }
>      uint32_t fromString(StringRef Name, bool &Valid) const;
>      std::string toString(uint32_t Bits) const;
>    };
> 
>    struct MSRMapper : SysRegMapper {
>      static const AArch64NamedImmMapper::Mapping MSRPairs[];
> -    MSRMapper(const FeatureBitset &FeatureBits);
> +    MSRMapper(uint64_t FeatureBits);
>    };
> 
>    struct MRSMapper : SysRegMapper {
>      static const AArch64NamedImmMapper::Mapping MRSPairs[];
> -    MRSMapper(const FeatureBitset &FeatureBits);
> +    MRSMapper(uint64_t FeatureBits);
>    };
> 
>    uint32_t ParseGenericRegister(StringRef Name, bool &Valid);
> 
> Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
> URL: http://llvm.org/viewvc/llvm-
> project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=229841&r1=22
> 9840&r2=229841&view=diff
> ==========================================================
> ====================
> --- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Thu Feb 19 05:38:11
> 2015
> @@ -422,7 +422,7 @@ bool ARMAsmPrinter::PrintAsmMemoryOperan
>  }
> 
>  static bool isThumb(const MCSubtargetInfo& STI) {
> -  return STI.getFeatureBits()[ARM::ModeThumb];
> +  return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
>  }
> 
>  void ARMAsmPrinter::emitInlineAsmEnd(const MCSubtargetInfo &StartInfo,
> 
> Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
> URL: http://llvm.org/viewvc/llvm-
> project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=229841&r1=
> 229840&r2=229841&view=diff
> ==========================================================
> ====================
> --- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Thu Feb 19 05:38:11
> 2015
> @@ -4507,7 +4507,7 @@ breakPartialRegDependency(MachineBasicBl
>  }
> 
>  bool ARMBaseInstrInfo::hasNOP() const {
> -  return Subtarget.getFeatureBits()[ARM::HasV6T2Ops];
> +  return (Subtarget.getFeatureBits() & ARM::HasV6T2Ops) != 0;
>  }
> 
>  bool ARMBaseInstrInfo::isSwiftFastImmShift(const MachineInstr *MI) const
> {
> 
> Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp
> URL: http://llvm.org/viewvc/llvm-
> project/llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp?rev=229841&r1=229
> 840&r2=229841&view=diff
> ==========================================================
> ====================
> --- llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp Thu Feb 19 05:38:11 2015
> @@ -262,8 +262,8 @@ void ARMSubtarget::initSubtargetFeatures
>    }
> 
>    // NEON f32 ops are non-IEEE 754 compliant. Darwin is ok with it by default.
> -  const FeatureBitset &Bits = getFeatureBits();
> -  if ((Bits[ARM::ProcA5] || Bits[ARM::ProcA8]) && // Where this matters
> +  uint64_t Bits = getFeatureBits();
> +  if ((Bits & ARM::ProcA5 || Bits & ARM::ProcA8) && // Where this matters
>        (Options.UnsafeFPMath || isTargetDarwin()))
>      UseNEONForSinglePrecisionFP = true;
>  }
> 
> Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
> URL: http://llvm.org/viewvc/llvm-
> project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=22
> 9841&r1=229840&r2=229841&view=diff
> ==========================================================
> ====================
> --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Thu Feb 19
> 05:38:11 2015
> @@ -244,37 +244,37 @@ class ARMAsmParser : public MCTargetAsmP
> 
>    bool isThumb() const {
>      // FIXME: Can tablegen auto-generate this?
> -    return STI.getFeatureBits()[ARM::ModeThumb];
> +    return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
>    }
>    bool isThumbOne() const {
> -    return isThumb() && !STI.getFeatureBits()[ARM::FeatureThumb2];
> +    return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0;
>    }
>    bool isThumbTwo() const {
> -    return isThumb() && STI.getFeatureBits()[ARM::FeatureThumb2];
> +    return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2);
>    }
>    bool hasThumb() const {
> -    return STI.getFeatureBits()[ARM::HasV4TOps];
> +    return STI.getFeatureBits() & ARM::HasV4TOps;
>    }
>    bool hasV6Ops() const {
> -    return STI.getFeatureBits()[ARM::HasV6Ops];
> +    return STI.getFeatureBits() & ARM::HasV6Ops;
>    }
>    bool hasV6MOps() const {
> -    return STI.getFeatureBits()[ARM::HasV6MOps];
> +    return STI.getFeatureBits() & ARM::HasV6MOps;
>    }
>    bool hasV7Ops() const {
> -    return STI.getFeatureBits()[ARM::HasV7Ops];
> +    return STI.getFeatureBits() & ARM::HasV7Ops;
>    }
>    bool hasV8Ops() const {
> -    return STI.getFeatureBits()[ARM::HasV8Ops];
> +    return STI.getFeatureBits() & ARM::HasV8Ops;
>    }
>    bool hasARM() const {
> -    return !STI.getFeatureBits()[ARM::FeatureNoARM];
> +    return !(STI.getFeatureBits() & ARM::FeatureNoARM);
>    }
>    bool hasThumb2DSP() const {
> -    return STI.getFeatureBits()[ARM::FeatureDSPThumb2];
> +    return STI.getFeatureBits() & ARM::FeatureDSPThumb2;
>    }
>    bool hasD16() const {
> -    return STI.getFeatureBits()[ARM::FeatureD16];
> +    return STI.getFeatureBits() & ARM::FeatureD16;
>    }
> 
>    void SwitchMode() {
> @@ -282,7 +282,7 @@ class ARMAsmParser : public MCTargetAsmP
>      setAvailableFeatures(FB);
>    }
>    bool isMClass() const {
> -    return STI.getFeatureBits()[ARM::FeatureMClass];
> +    return STI.getFeatureBits() & ARM::FeatureMClass;
>    }
> 
>    /// @name Auto-generated Match Functions
> @@ -9186,53 +9186,52 @@ bool ARMAsmParser::parseDirectiveCPU(SML
>  // tools/clang/lib/Driver/Tools.cpp
>  static const struct {
>    const unsigned ID;
> -  const FeatureBitset Enabled;
> -  const FeatureBitset Disabled;
> +  const uint64_t Enabled;
> +  const uint64_t Disabled;
>  } FPUs[] = {
> -      {/* ID */ ARM::VFP,
> -       /* Enabled */ {ARM::FeatureVFP2},
> -       /* Disabled */ {ARM::FeatureNEON}},
> -      {/* ID */ ARM::VFPV2,
> -       /* Enabled */ {ARM::FeatureVFP2},
> -       /* Disabled */ {ARM::FeatureNEON}},
> -      {/* ID */ ARM::VFPV3,
> -       /* Enabled */ {ARM::FeatureVFP2, ARM::FeatureVFP3},
> -       /* Disabled */ {ARM::FeatureNEON, ARM::FeatureD16}},
> -      {/* ID */ ARM::VFPV3_D16,
> -       /* Enabled */ {ARM::FeatureVFP2, ARM::FeatureVFP3,
> ARM::FeatureD16},
> -       /* Disabled */ {ARM::FeatureNEON}},
> -      {/* ID */ ARM::VFPV4,
> -       /* Enabled */ {ARM::FeatureVFP2, ARM::FeatureVFP3,
> ARM::FeatureVFP4},
> -       /* Disabled */ {ARM::FeatureNEON, ARM::FeatureD16}},
> -      {/* ID */ ARM::VFPV4_D16,
> -       /* Enabled */ {ARM::FeatureVFP2, ARM::FeatureVFP3,
> ARM::FeatureVFP4,
> -                      ARM::FeatureD16},
> -       /* Disabled */ {ARM::FeatureNEON}},
> -      {/* ID */ ARM::FPV5_D16,
> -       /* Enabled */ {ARM::FeatureVFP2, ARM::FeatureVFP3,
> ARM::FeatureVFP4,
> -                      ARM::FeatureFPARMv8, ARM::FeatureD16},
> -       /* Disabled */ {ARM::FeatureNEON, ARM::FeatureCrypto}},
> -      {/* ID */ ARM::FP_ARMV8,
> -       /* Enabled */ {ARM::FeatureVFP2, ARM::FeatureVFP3,
> ARM::FeatureVFP4,
> -                      ARM::FeatureFPARMv8},
> -       /* Disabled */ {ARM::FeatureNEON, ARM::FeatureCrypto,
> ARM::FeatureD16}},
> -      {/* ID */ ARM::NEON,
> -       /* Enabled */ {ARM::FeatureVFP2, ARM::FeatureVFP3,
> ARM::FeatureNEON},
> -       /* Disabled */ {ARM::FeatureD16}},
> -      {/* ID */ ARM::NEON_VFPV4,
> -       /* Enabled */ {ARM::FeatureVFP2, ARM::FeatureVFP3,
> ARM::FeatureVFP4,
> -                      ARM::FeatureNEON},
> -       /* Disabled */ {ARM::FeatureD16}},
> -      {/* ID */ ARM::NEON_FP_ARMV8,
> -       /* Enabled */ {ARM::FeatureVFP2, ARM::FeatureVFP3,
> ARM::FeatureVFP4,
> -                      ARM::FeatureFPARMv8, ARM::FeatureNEON},
> -       /* Disabled */ {ARM::FeatureCrypto, ARM::FeatureD16}},
> -      {/* ID */ ARM::CRYPTO_NEON_FP_ARMV8,
> -       /* Enabled */ {ARM::FeatureVFP2, ARM::FeatureVFP3,
> ARM::FeatureVFP4,
> -                      ARM::FeatureFPARMv8, ARM::FeatureNEON,
> -                      ARM::FeatureCrypto},
> -       /* Disabled */ {ARM::FeatureD16}},
> -      {ARM::SOFTVFP, {}, {}},
> +    {/* ID */ ARM::VFP,
> +     /* Enabled */ ARM::FeatureVFP2,
> +     /* Disabled */ ARM::FeatureNEON},
> +    {/* ID */ ARM::VFPV2,
> +     /* Enabled */ ARM::FeatureVFP2,
> +     /* Disabled */ ARM::FeatureNEON},
> +    {/* ID */ ARM::VFPV3,
> +     /* Enabled */ ARM::FeatureVFP2 | ARM::FeatureVFP3,
> +     /* Disabled */ ARM::FeatureNEON | ARM::FeatureD16},
> +    {/* ID */ ARM::VFPV3_D16,
> +     /* Enable */ ARM::FeatureVFP2 | ARM::FeatureVFP3 |
> ARM::FeatureD16,
> +     /* Disabled */ ARM::FeatureNEON},
> +    {/* ID */ ARM::VFPV4,
> +     /* Enabled */ ARM::FeatureVFP2 | ARM::FeatureVFP3 |
> ARM::FeatureVFP4,
> +     /* Disabled */ ARM::FeatureNEON | ARM::FeatureD16},
> +    {/* ID */ ARM::VFPV4_D16,
> +     /* Enabled */ ARM::FeatureVFP2 | ARM::FeatureVFP3 |
> ARM::FeatureVFP4 |
> +         ARM::FeatureD16,
> +     /* Disabled */ ARM::FeatureNEON},
> +    {/* ID */ ARM::FPV5_D16,
> +     /* Enabled */ ARM::FeatureVFP2 | ARM::FeatureVFP3 |
> ARM::FeatureVFP4 |
> +         ARM::FeatureFPARMv8 | ARM::FeatureD16,
> +     /* Disabled */ ARM::FeatureNEON | ARM::FeatureCrypto},
> +    {/* ID */ ARM::FP_ARMV8,
> +     /* Enabled */ ARM::FeatureVFP2 | ARM::FeatureVFP3 |
> ARM::FeatureVFP4 |
> +         ARM::FeatureFPARMv8,
> +     /* Disabled */ ARM::FeatureNEON | ARM::FeatureCrypto |
> ARM::FeatureD16},
> +    {/* ID */ ARM::NEON,
> +     /* Enabled */ ARM::FeatureVFP2 | ARM::FeatureVFP3 |
> ARM::FeatureNEON,
> +     /* Disabled */ ARM::FeatureD16},
> +    {/* ID */ ARM::NEON_VFPV4,
> +     /* Enabled */ ARM::FeatureVFP2 | ARM::FeatureVFP3 |
> ARM::FeatureVFP4 |
> +         ARM::FeatureNEON,
> +     /* Disabled */ ARM::FeatureD16},
> +    {/* ID */ ARM::NEON_FP_ARMV8,
> +     /* Enabled */ ARM::FeatureVFP2 | ARM::FeatureVFP3 |
> ARM::FeatureVFP4 |
> +         ARM::FeatureFPARMv8 | ARM::FeatureNEON,
> +     /* Disabled */ ARM::FeatureCrypto | ARM::FeatureD16},
> +    {/* ID */ ARM::CRYPTO_NEON_FP_ARMV8,
> +     /* Enabled */ ARM::FeatureVFP2 | ARM::FeatureVFP3 |
> ARM::FeatureVFP4 |
> +         ARM::FeatureFPARMv8 | ARM::FeatureNEON | ARM::FeatureCrypto,
> +     /* Disabled */ ARM::FeatureD16},
> +    {ARM::SOFTVFP, 0, 0},
>  };
> 
>  /// parseDirectiveFPU
> @@ -9257,8 +9256,8 @@ bool ARMAsmParser::parseDirectiveFPU(SML
> 
>      // Need to toggle features that should be on but are off and that
>      // should off but are on.
> -    FeatureBitset Toggle = (Entry.Enabled & ~STI.getFeatureBits()) |
> -                           (Entry.Disabled & STI.getFeatureBits());
> +    uint64_t Toggle = (Entry.Enabled & ~STI.getFeatureBits()) |
> +                      (Entry.Disabled & STI.getFeatureBits());
> 
> setAvailableFeatures(ComputeAvailableFeatures(STI.ToggleFeature(Toggle))
> );
>      break;
>    }
> @@ -9995,30 +9994,30 @@ extern "C" void LLVMInitializeARMAsmPars
>  static const struct {
>    const char *Name;
>    const unsigned ArchCheck;
> -  const FeatureBitset Features;
> +  const uint64_t Features;
>  } Extensions[] = {
> -  { "crc", Feature_HasV8, {ARM::FeatureCRC} },
> +  { "crc", Feature_HasV8, ARM::FeatureCRC },
>    { "crypto",  Feature_HasV8,
> -    {ARM::FeatureCrypto, ARM::FeatureNEON, ARM::FeatureFPARMv8} },
> -  { "fp", Feature_HasV8, {ARM::FeatureFPARMv8} },
> +    ARM::FeatureCrypto | ARM::FeatureNEON | ARM::FeatureFPARMv8 },
> +  { "fp", Feature_HasV8, ARM::FeatureFPARMv8 },
>    { "idiv", Feature_HasV7 | Feature_IsNotMClass,
> -    {ARM::FeatureHWDiv, ARM::FeatureHWDivARM} },
> +    ARM::FeatureHWDiv | ARM::FeatureHWDivARM },
>    // FIXME: iWMMXT not supported
> -  { "iwmmxt", Feature_None, {} },
> +  { "iwmmxt", Feature_None, 0 },
>    // FIXME: iWMMXT2 not supported
> -  { "iwmmxt2", Feature_None, {} },
> +  { "iwmmxt2", Feature_None, 0 },
>    // FIXME: Maverick not supported
> -  { "maverick", Feature_None, {} },
> -  { "mp", Feature_HasV7 | Feature_IsNotMClass, {ARM::FeatureMP} },
> +  { "maverick", Feature_None, 0 },
> +  { "mp", Feature_HasV7 | Feature_IsNotMClass, ARM::FeatureMP },
>    // FIXME: ARMv6-m OS Extensions feature not checked
> -  { "os", Feature_None, {} },
> +  { "os", Feature_None, 0 },
>    // FIXME: Also available in ARMv6-K
> -  { "sec", Feature_HasV7, {ARM::FeatureTrustZone} },
> -  { "simd", Feature_HasV8, {ARM::FeatureNEON, ARM::FeatureFPARMv8} },
> +  { "sec", Feature_HasV7, ARM::FeatureTrustZone },
> +  { "simd", Feature_HasV8, ARM::FeatureNEON | ARM::FeatureFPARMv8 },
>    // FIXME: Only available in A-class, isel not predicated
> -  { "virt", Feature_HasV7, {ARM::FeatureVirtualization} },
> +  { "virt", Feature_HasV7, ARM::FeatureVirtualization },
>    // FIXME: xscale not supported
> -  { "xscale", Feature_None, {} },
> +  { "xscale", Feature_None, 0 },
>  };
> 
>  /// parseDirectiveArchExtension
> @@ -10046,7 +10045,7 @@ bool ARMAsmParser::parseDirectiveArchExt
>      if (Extension.Name != Name)
>        continue;
> 
> -    if (Extension.Features.none())
> +    if (!Extension.Features)
>        report_fatal_error("unsupported architectural extension: " + Name);
> 
>      if ((getAvailableFeatures() & Extension.ArchCheck) !=
> Extension.ArchCheck) {
> @@ -10055,10 +10054,9 @@ bool ARMAsmParser::parseDirectiveArchExt
>        return false;
>      }
> 
> -    FeatureBitset ToggleFeatures = EnableFeature
> -      ? (~STI.getFeatureBits() & Extension.Features)
> -      : ( STI.getFeatureBits() & Extension.Features);
> -
> +    uint64_t ToggleFeatures = EnableFeature
> +                                  ? (~STI.getFeatureBits() & Extension.Features)
> +                                  : ( STI.getFeatureBits() & Extension.Features);
>      uint64_t Features =
>          ComputeAvailableFeatures(STI.ToggleFeature(ToggleFeatures));
>      setAvailableFeatures(Features);
> 
> Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
> URL: http://llvm.org/viewvc/llvm-
> project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp?re
> v=229841&r1=229840&r2=229841&view=diff
> ==========================================================
> ====================
> --- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Thu
> Feb 19 05:38:11 2015
> @@ -431,7 +431,7 @@ DecodeStatus ARMDisassembler::getInstruc
>                                               raw_ostream &CS) const {
>    CommentStream = &CS;
> 
> -  assert(!STI.getFeatureBits()[ARM::ModeThumb] &&
> +  assert(!(STI.getFeatureBits() & ARM::ModeThumb) &&
>           "Asked to disassemble an ARM instruction but Subtarget is in Thumb "
>           "mode!");
> 
> @@ -696,7 +696,7 @@ DecodeStatus ThumbDisassembler::getInstr
>                                                 raw_ostream &CS) const {
>    CommentStream = &CS;
> 
> -  assert(STI.getFeatureBits()[ARM::ModeThumb] &&
> +  assert((STI.getFeatureBits() & ARM::ModeThumb) &&
>           "Asked to disassemble in Thumb mode but Subtarget is in ARM
> mode!");
> 
>    // We want to read exactly 2 bytes of data.
> @@ -1022,10 +1022,9 @@ static const uint16_t DPRDecoderTable[]
> 
>  static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned
> RegNo,
>                                     uint64_t Address, const void *Decoder) {
> -  const FeatureBitset &featureBits =
> -    ((const MCDisassembler*)Decoder)-
> >getSubtargetInfo().getFeatureBits();
> -
> -  bool hasD16 = featureBits[ARM::FeatureD16];
> +  uint64_t featureBits = ((const MCDisassembler*)Decoder)-
> >getSubtargetInfo()
> +                                                          .getFeatureBits();
> +  bool hasD16 = featureBits & ARM::FeatureD16;
> 
>    if (RegNo > 31 || (hasD16 && RegNo > 15))
>      return MCDisassembler::Fail;
> @@ -1370,9 +1369,9 @@ static DecodeStatus DecodeCopMemInstruct
>        break;
>    }
> 
> -  const FeatureBitset &featureBits =
> -    ((const MCDisassembler*)Decoder)-
> >getSubtargetInfo().getFeatureBits();
> -  if (featureBits[ARM::HasV8Ops] && (coproc != 14))
> +  uint64_t featureBits = ((const MCDisassembler*)Decoder)-
> >getSubtargetInfo()
> +                                                          .getFeatureBits();
> +  if ((featureBits & ARM::HasV8Ops) && (coproc != 14))
>      return MCDisassembler::Fail;
> 
>    Inst.addOperand(MCOperand::CreateImm(coproc));
> @@ -3268,11 +3267,10 @@ static DecodeStatus DecodeT2LoadShift(MC
>    unsigned Rt = fieldFromInstruction(Insn, 12, 4);
>    unsigned Rn = fieldFromInstruction(Insn, 16, 4);
> 
> -  const FeatureBitset &featureBits =
> -    ((const MCDisassembler*)Decoder)-
> >getSubtargetInfo().getFeatureBits();
> -
> -  bool hasMP = featureBits[ARM::FeatureMP];
> -  bool hasV7Ops = featureBits[ARM::HasV7Ops];
> +  uint64_t featureBits = ((const MCDisassembler*)Decoder)-
> >getSubtargetInfo()
> +                                                          .getFeatureBits();
> +  bool hasMP = featureBits & ARM::FeatureMP;
> +  bool hasV7Ops = featureBits & ARM::HasV7Ops;
> 
>    if (Rn == 15) {
>      switch (Inst.getOpcode()) {
> @@ -3355,11 +3353,10 @@ static DecodeStatus DecodeT2LoadImm8(MCI
>    imm |= (Rn << 9);
>    unsigned add = fieldFromInstruction(Insn, 9, 1);
> 
> -  const FeatureBitset &featureBits =
> -    ((const MCDisassembler*)Decoder)-
> >getSubtargetInfo().getFeatureBits();
> -
> -  bool hasMP = featureBits[ARM::FeatureMP];
> -  bool hasV7Ops = featureBits[ARM::HasV7Ops];
> +  uint64_t featureBits = ((const MCDisassembler*)Decoder)-
> >getSubtargetInfo()
> +                                                          .getFeatureBits();
> +  bool hasMP = featureBits & ARM::FeatureMP;
> +  bool hasV7Ops = featureBits & ARM::HasV7Ops;
> 
>    if (Rn == 15) {
>      switch (Inst.getOpcode()) {
> @@ -3436,11 +3433,10 @@ static DecodeStatus DecodeT2LoadImm12(MC
>    unsigned imm = fieldFromInstruction(Insn, 0, 12);
>    imm |= (Rn << 13);
> 
> -  const FeatureBitset &featureBits =
> -    ((const MCDisassembler*)Decoder)-
> >getSubtargetInfo().getFeatureBits();
> -
> -  bool hasMP = featureBits[ARM::FeatureMP];
> -  bool hasV7Ops = featureBits[ARM::HasV7Ops];
> +  uint64_t featureBits = ((const MCDisassembler*)Decoder)-
> >getSubtargetInfo()
> +                                                          .getFeatureBits();
> +  bool hasMP = (featureBits & ARM::FeatureMP);
> +  bool hasV7Ops = (featureBits & ARM::HasV7Ops);
> 
>    if (Rn == 15) {
>      switch (Inst.getOpcode()) {
> @@ -3554,10 +3550,9 @@ static DecodeStatus DecodeT2LoadLabel(MC
>    unsigned U = fieldFromInstruction(Insn, 23, 1);
>    int imm = fieldFromInstruction(Insn, 0, 12);
> 
> -  const FeatureBitset &featureBits =
> -    ((const MCDisassembler*)Decoder)-
> >getSubtargetInfo().getFeatureBits();
> -
> -  bool hasV7Ops = featureBits[ARM::HasV7Ops];
> +  uint64_t featureBits = ((const MCDisassembler*)Decoder)-
> >getSubtargetInfo()
> +                                                          .getFeatureBits();
> +  bool hasV7Ops = (featureBits & ARM::HasV7Ops);
> 
>    if (Rt == 15) {
>      switch (Inst.getOpcode()) {
> @@ -3878,10 +3873,9 @@ static DecodeStatus DecodeCoprocessor(MC
>    if (Val == 0xA || Val == 0xB)
>      return MCDisassembler::Fail;
> 
> -  const FeatureBitset &featureBits =
> -    ((const MCDisassembler*)Decoder)-
> >getSubtargetInfo().getFeatureBits();
> -
> -  if (featureBits[ARM::HasV8Ops] && !(Val == 14 || Val == 15))
> +  uint64_t featureBits = ((const MCDisassembler*)Decoder)-
> >getSubtargetInfo()
> +                                                          .getFeatureBits();
> +  if ((featureBits & ARM::HasV8Ops) && !(Val == 14 || Val == 15))
>      return MCDisassembler::Fail;
> 
>    Inst.addOperand(MCOperand::CreateImm(Val));
> @@ -4031,10 +4025,9 @@ static DecodeStatus DecodeInstSyncBarrie
>  static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val,
>                            uint64_t Address, const void *Decoder) {
>    DecodeStatus S = MCDisassembler::Success;
> -  const FeatureBitset &FeatureBits =
> -    ((const MCDisassembler*)Decoder)-
> >getSubtargetInfo().getFeatureBits();
> -
> -  if (FeatureBits[ARM::FeatureMClass]) {
> +  uint64_t FeatureBits = ((const MCDisassembler*)Decoder)-
> >getSubtargetInfo()
> +                                                          .getFeatureBits();
> +  if (FeatureBits & ARM::FeatureMClass) {
>      unsigned ValLow = Val & 0xff;
> 
>      // Validate the SYSm value first.
> @@ -4054,7 +4047,7 @@ static DecodeStatus DecodeMSRMask(MCInst
>      case 17: // basepri
>      case 18: // basepri_max
>      case 19: // faultmask
> -      if (!(FeatureBits[ARM::HasV7Ops]))
> +      if (!(FeatureBits & ARM::HasV7Ops))
>          // Values basepri, basepri_max and faultmask are only valid for v7m.
>          return MCDisassembler::Fail;
>        break;
> @@ -4064,7 +4057,7 @@ static DecodeStatus DecodeMSRMask(MCInst
> 
>      if (Inst.getOpcode() == ARM::t2MSR_M) {
>        unsigned Mask = fieldFromInstruction(Val, 10, 2);
> -      if (!(FeatureBits[ARM::HasV7Ops])) {
> +      if (!(FeatureBits & ARM::HasV7Ops)) {
>          // The ARMv6-M MSR bits {11-10} can be only 0b10, other values are
>          // unpredictable.
>          if (Mask != 2)
> @@ -4078,7 +4071,7 @@ static DecodeStatus DecodeMSRMask(MCInst
>          // indicates the move for the GE{3:0} bits, the mask{0} bit can be set
>          // only if the processor includes the DSP extension.
>          if (Mask == 0 || (Mask != 2 && ValLow > 3) ||
> -            (!(FeatureBits[ARM::FeatureDSPThumb2]) && (Mask & 1)))
> +            (!(FeatureBits & ARM::FeatureDSPThumb2) && (Mask & 1)))
>            S = MCDisassembler::SoftFail;
>        }
>      }
> 
> Modified: llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
> URL: http://llvm.org/viewvc/llvm-
> project/llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp?rev=229
> 841&r1=229840&r2=229841&view=diff
> ==========================================================
> ====================
> --- llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp Thu Feb 19
> 05:38:11 2015
> @@ -90,7 +90,7 @@ void ARMInstPrinter::printInst(const MCI
>      case 3: O << "\twfi"; break;
>      case 4: O << "\tsev"; break;
>      case 5:
> -      if (getAvailableFeatures()[ARM::HasV8Ops]) {
> +      if ((getAvailableFeatures() & ARM::HasV8Ops)) {
>          O << "\tsevl";
>          break;
>        } // Fallthrough for non-v8
> @@ -299,7 +299,7 @@ void ARMInstPrinter::printInst(const MCI
>      if (MI->getNumOperands() == 3 &&
>          MI->getOperand(0).isImm() &&
>          MI->getOperand(0).getImm() == 0 &&
> -        getAvailableFeatures()[ARM::FeatureVirtualization]) {
> +        (getAvailableFeatures() & ARM::FeatureVirtualization)) {
>        O << "\teret";
>        printPredicateOperand(MI, 1, O);
>        printAnnotation(O, Annot);
> @@ -698,7 +698,7 @@ void ARMInstPrinter::printBitfieldInvMas
>  void ARMInstPrinter::printMemBOption(const MCInst *MI, unsigned
> OpNum,
>                                       raw_ostream &O) {
>    unsigned val = MI->getOperand(OpNum).getImm();
> -  O << ARM_MB::MemBOptToString(val,
> getAvailableFeatures()[ARM::HasV8Ops]);
> +  O << ARM_MB::MemBOptToString(val, (getAvailableFeatures() &
> ARM::HasV8Ops));
>  }
> 
>  void ARMInstPrinter::printInstSyncBOption(const MCInst *MI, unsigned
> OpNum,
> @@ -796,14 +796,14 @@ void ARMInstPrinter::printMSRMaskOperand
>    const MCOperand &Op = MI->getOperand(OpNum);
>    unsigned SpecRegRBit = Op.getImm() >> 4;
>    unsigned Mask = Op.getImm() & 0xf;
> -  const FeatureBitset &FeatureBits = getAvailableFeatures();
> +  uint64_t FeatureBits = getAvailableFeatures();
> 
> -  if (FeatureBits[ARM::FeatureMClass]) {
> +  if (FeatureBits & ARM::FeatureMClass) {
>      unsigned SYSm = Op.getImm();
>      unsigned Opcode = MI->getOpcode();
> 
>      // For writes, handle extended mask bits if the DSP extension is present.
> -    if (Opcode == ARM::t2MSR_M &&
> FeatureBits[ARM::FeatureDSPThumb2]) {
> +    if (Opcode == ARM::t2MSR_M && (FeatureBits &
> ARM::FeatureDSPThumb2)) {
>        switch (SYSm) {
>        case 0x400: O << "apsr_g"; return;
>        case 0xc00: O << "apsr_nzcvqg"; return;
> @@ -819,7 +819,7 @@ void ARMInstPrinter::printMSRMaskOperand
>      // Handle the basic 8-bit mask.
>      SYSm &= 0xff;
> 
> -    if (Opcode == ARM::t2MSR_M && FeatureBits [ARM::HasV7Ops]) {
> +    if (Opcode == ARM::t2MSR_M && (FeatureBits & ARM::HasV7Ops)) {
>        // ARMv7-M deprecates using MSR APSR without a _<bits> qualifier as an
>        // alias for MSR APSR_nzcvq.
>        switch (SYSm) {
> 
> Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.h
> URL: http://llvm.org/viewvc/llvm-
> project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.h?rev
> =229841&r1=229840&r2=229841&view=diff
> ==========================================================
> ====================
> --- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.h (original)
> +++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.h Thu Feb
> 19 05:38:11 2015
> @@ -33,7 +33,7 @@ public:
>      return ARM::NumTargetFixupKinds;
>    }
> 
> -  bool hasNOP() const { return STI->getFeatureBits()[ARM::HasV6T2Ops]; }
> +  bool hasNOP() const { return (STI->getFeatureBits() & ARM::HasV6T2Ops)
> != 0; }
> 
>    const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const
> override;
> 
> 
> Modified:
> llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
> URL: http://llvm.org/viewvc/llvm-
> project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
> ?rev=229841&r1=229840&r2=229841&view=diff
> ==========================================================
> ====================
> --- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
> (original)
> +++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
> Thu Feb 19 05:38:11 2015
> @@ -51,10 +51,10 @@ public:
>    ~ARMMCCodeEmitter() {}
> 
>    bool isThumb(const MCSubtargetInfo &STI) const {
> -    return STI.getFeatureBits()[ARM::ModeThumb];
> +    return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
>    }
>    bool isThumb2(const MCSubtargetInfo &STI) const {
> -    return isThumb(STI) && STI.getFeatureBits()[ARM::FeatureThumb2];
> +    return isThumb(STI) && (STI.getFeatureBits() & ARM::FeatureThumb2) !=
> 0;
>    }
>    bool isTargetMachO(const MCSubtargetInfo &STI) const {
>      Triple TT(STI.getTargetTriple());
> 
> Modified:
> llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
> URL: http://llvm.org/viewvc/llvm-
> project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp?
> rev=229841&r1=229840&r2=229841&view=diff
> ==========================================================
> ====================
> --- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
> (original)
> +++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp Thu
> Feb 19 05:38:11 2015
> @@ -33,7 +33,7 @@ using namespace llvm;
> 
>  static bool getMCRDeprecationInfo(MCInst &MI, MCSubtargetInfo &STI,
>                                    std::string &Info) {
> -  if (STI.getFeatureBits()[llvm::ARM::HasV7Ops] &&
> +  if (STI.getFeatureBits() & llvm::ARM::HasV7Ops &&
>        (MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 15) &&
>        (MI.getOperand(1).isImm() && MI.getOperand(1).getImm() == 0) &&
>        // Checks for the deprecated CP15ISB encoding:
> @@ -65,7 +65,7 @@ static bool getMCRDeprecationInfo(MCInst
> 
>  static bool getITDeprecationInfo(MCInst &MI, MCSubtargetInfo &STI,
>                                   std::string &Info) {
> -  if (STI.getFeatureBits()[llvm::ARM::HasV8Ops] &&
> MI.getOperand(1).isImm() &&
> +  if (STI.getFeatureBits() & llvm::ARM::HasV8Ops &&
> MI.getOperand(1).isImm() &&
>        MI.getOperand(1).getImm() != 8) {
>      Info = "applying IT instruction to more than one subsequent instruction is "
>             "deprecated";
> @@ -77,7 +77,7 @@ static bool getITDeprecationInfo(MCInst
> 
>  static bool getARMStoreDeprecationInfo(MCInst &MI, MCSubtargetInfo
> &STI,
>                                         std::string &Info) {
> -  assert(!STI.getFeatureBits()[llvm::ARM::ModeThumb] &&
> +  assert((~STI.getFeatureBits() & llvm::ARM::ModeThumb) &&
>           "cannot predicate thumb instructions");
> 
>    assert(MI.getNumOperands() >= 4 && "expected >= 4 arguments");
> @@ -94,7 +94,7 @@ static bool getARMStoreDeprecationInfo(M
> 
>  static bool getARMLoadDeprecationInfo(MCInst &MI, MCSubtargetInfo
> &STI,
>                                        std::string &Info) {
> -  assert(!STI.getFeatureBits()[llvm::ARM::ModeThumb] &&
> +  assert((~STI.getFeatureBits() & llvm::ARM::ModeThumb) &&
>           "cannot predicate thumb instructions");
> 
>    assert(MI.getNumOperands() >= 4 && "expected >= 4 arguments");
> 
> Modified: llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
> URL: http://llvm.org/viewvc/llvm-
> project/llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp?rev=22
> 9841&r1=229840&r2=229841&view=diff
> ==========================================================
> ====================
> --- llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp (original)
> +++ llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp Thu Feb 19
> 05:38:11 2015
> @@ -71,7 +71,15 @@ public:
>    // The full table can be found in MipsGenSubtargetInfo.inc
> (MipsFeatureKV[]).
>    // The reason we need this mask is explained in the selectArch function.
>    // FIXME: Ideally we would like TableGen to generate this information.
> -  static const FeatureBitset AllArchRelatedMask;
> +  static const uint64_t AllArchRelatedMask =
> +      Mips::FeatureMips1 | Mips::FeatureMips2 | Mips::FeatureMips3 |
> +      Mips::FeatureMips3_32 | Mips::FeatureMips3_32r2 |
> Mips::FeatureMips4 |
> +      Mips::FeatureMips4_32 | Mips::FeatureMips4_32r2 |
> Mips::FeatureMips5 |
> +      Mips::FeatureMips5_32r2 | Mips::FeatureMips32 |
> Mips::FeatureMips32r2 |
> +      Mips::FeatureMips32r3 | Mips::FeatureMips32r5 |
> Mips::FeatureMips32r6 |
> +      Mips::FeatureMips64 | Mips::FeatureMips64r2 | Mips::FeatureMips64r3
> |
> +      Mips::FeatureMips64r5 | Mips::FeatureMips64r6 | Mips::FeatureCnMips
> |
> +      Mips::FeatureFP64Bit | Mips::FeatureGP64Bit | Mips::FeatureNaN2008;
> 
>  private:
>    unsigned ATReg;
> @@ -81,17 +89,6 @@ private:
>  };
>  }
> 
> -const FeatureBitset MipsAssemblerOptions::AllArchRelatedMask = {
> -    Mips::FeatureMips1, Mips::FeatureMips2, Mips::FeatureMips3,
> -    Mips::FeatureMips3_32, Mips::FeatureMips3_32r2, Mips::FeatureMips4,
> -    Mips::FeatureMips4_32, Mips::FeatureMips4_32r2, Mips::FeatureMips5,
> -    Mips::FeatureMips5_32r2, Mips::FeatureMips32, Mips::FeatureMips32r2,
> -    Mips::FeatureMips32r3, Mips::FeatureMips32r5, Mips::FeatureMips32r6,
> -    Mips::FeatureMips64, Mips::FeatureMips64r2, Mips::FeatureMips64r3,
> -    Mips::FeatureMips64r5, Mips::FeatureMips64r6, Mips::FeatureCnMips,
> -    Mips::FeatureFP64Bit, Mips::FeatureGP64Bit, Mips::FeatureNaN2008
> -};
> -
>  namespace {
>  class MipsAsmParser : public MCTargetAsmParser {
>    MipsTargetStreamer &getTargetStreamer() {
> @@ -296,7 +293,7 @@ class MipsAsmParser : public MCTargetAsm
>    // FeatureMipsGP64 | FeatureMips1)
>    // Clearing Mips3 is equivalent to clear (FeatureMips3 | FeatureMips4).
>    void selectArch(StringRef ArchFeature) {
> -    FeatureBitset FeatureBits = STI.getFeatureBits();
> +    uint64_t FeatureBits = STI.getFeatureBits();
>      FeatureBits &= ~MipsAssemblerOptions::AllArchRelatedMask;
>      STI.setFeatureBits(FeatureBits);
>      setAvailableFeatures(
> @@ -305,7 +302,7 @@ class MipsAsmParser : public MCTargetAsm
>    }
> 
>    void setFeatureBits(uint64_t Feature, StringRef FeatureString) {
> -    if (!(STI.getFeatureBits()[Feature])) {
> +    if (!(STI.getFeatureBits() & Feature)) {
>        setAvailableFeatures(
>            ComputeAvailableFeatures(STI.ToggleFeature(FeatureString)));
>      }
> @@ -313,7 +310,7 @@ class MipsAsmParser : public MCTargetAsm
>    }
> 
>    void clearFeatureBits(uint64_t Feature, StringRef FeatureString) {
> -    if (STI.getFeatureBits()[Feature]) {
> +    if (STI.getFeatureBits() & Feature) {
>        setAvailableFeatures(
>            ComputeAvailableFeatures(STI.ToggleFeature(FeatureString)));
>      }
> @@ -358,66 +355,65 @@ public:
>    /// True if all of $fcc0 - $fcc7 exist for the current ISA.
>    bool hasEightFccRegisters() const { return hasMips4() || hasMips32(); }
> 
> -  bool isGP64bit() const { return STI.getFeatureBits()[Mips::FeatureGP64Bit];
> }
> -  bool isFP64bit() const { return STI.getFeatureBits()[Mips::FeatureFP64Bit]; }
> +  bool isGP64bit() const { return STI.getFeatureBits() &
> Mips::FeatureGP64Bit; }
> +  bool isFP64bit() const { return STI.getFeatureBits() & Mips::FeatureFP64Bit;
> }
>    const MipsABIInfo &getABI() const { return ABI; }
>    bool isABI_N32() const { return ABI.IsN32(); }
>    bool isABI_N64() const { return ABI.IsN64(); }
>    bool isABI_O32() const { return ABI.IsO32(); }
> -  bool isABI_FPXX() const { return STI.getFeatureBits()[Mips::FeatureFPXX]; }
> +  bool isABI_FPXX() const { return STI.getFeatureBits() &
> Mips::FeatureFPXX; }
> 
>    bool useOddSPReg() const {
> -    return !(STI.getFeatureBits()[Mips::FeatureNoOddSPReg]);
> +    return !(STI.getFeatureBits() & Mips::FeatureNoOddSPReg);
>    }
> 
>    bool inMicroMipsMode() const {
> -    return STI.getFeatureBits()[Mips::FeatureMicroMips];
> +    return STI.getFeatureBits() & Mips::FeatureMicroMips;
>    }
> -  bool hasMips1() const { return STI.getFeatureBits()[Mips::FeatureMips1]; }
> -  bool hasMips2() const { return STI.getFeatureBits()[Mips::FeatureMips2]; }
> -  bool hasMips3() const { return STI.getFeatureBits()[Mips::FeatureMips3]; }
> -  bool hasMips4() const { return STI.getFeatureBits()[Mips::FeatureMips4]; }
> -  bool hasMips5() const { return STI.getFeatureBits()[Mips::FeatureMips5]; }
> +  bool hasMips1() const { return STI.getFeatureBits() & Mips::FeatureMips1;
> }
> +  bool hasMips2() const { return STI.getFeatureBits() & Mips::FeatureMips2;
> }
> +  bool hasMips3() const { return STI.getFeatureBits() & Mips::FeatureMips3;
> }
> +  bool hasMips4() const { return STI.getFeatureBits() & Mips::FeatureMips4;
> }
> +  bool hasMips5() const { return STI.getFeatureBits() & Mips::FeatureMips5;
> }
>    bool hasMips32() const {
> -    return STI.getFeatureBits()[Mips::FeatureMips32];
> +    return (STI.getFeatureBits() & Mips::FeatureMips32);
>    }
>    bool hasMips64() const {
> -    return STI.getFeatureBits()[Mips::FeatureMips64];
> +    return (STI.getFeatureBits() & Mips::FeatureMips64);
>    }
>    bool hasMips32r2() const {
> -    return STI.getFeatureBits()[Mips::FeatureMips32r2];
> +    return (STI.getFeatureBits() & Mips::FeatureMips32r2);
>    }
>    bool hasMips64r2() const {
> -    return STI.getFeatureBits()[Mips::FeatureMips64r2];
> +    return (STI.getFeatureBits() & Mips::FeatureMips64r2);
>    }
>    bool hasMips32r3() const {
> -    return (STI.getFeatureBits()[Mips::FeatureMips32r3]);
> +    return (STI.getFeatureBits() & Mips::FeatureMips32r3);
>    }
>    bool hasMips64r3() const {
> -    return (STI.getFeatureBits()[Mips::FeatureMips64r3]);
> +    return (STI.getFeatureBits() & Mips::FeatureMips64r3);
>    }
>    bool hasMips32r5() const {
> -    return (STI.getFeatureBits()[Mips::FeatureMips32r5]);
> +    return (STI.getFeatureBits() & Mips::FeatureMips32r5);
>    }
>    bool hasMips64r5() const {
> -    return (STI.getFeatureBits()[Mips::FeatureMips64r5]);
> +    return (STI.getFeatureBits() & Mips::FeatureMips64r5);
>    }
>    bool hasMips32r6() const {
> -    return STI.getFeatureBits()[Mips::FeatureMips32r6];
> +    return (STI.getFeatureBits() & Mips::FeatureMips32r6);
>    }
>    bool hasMips64r6() const {
> -    return STI.getFeatureBits()[Mips::FeatureMips64r6];
> +    return (STI.getFeatureBits() & Mips::FeatureMips64r6);
>    }
> -
> -  bool hasDSP() const { return STI.getFeatureBits()[Mips::FeatureDSP]; }
> -  bool hasDSPR2() const { return STI.getFeatureBits()[Mips::FeatureDSPR2]; }
> -  bool hasMSA() const { return STI.getFeatureBits()[Mips::FeatureMSA]; }
>    bool hasCnMips() const {
> -    return (STI.getFeatureBits()[Mips::FeatureCnMips]);
> +    return (STI.getFeatureBits() & Mips::FeatureCnMips);
>    }
> +  bool hasDSP() const { return (STI.getFeatureBits() & Mips::FeatureDSP); }
> +  bool hasDSPR2() const { return (STI.getFeatureBits() &
> Mips::FeatureDSPR2); }
> +  bool hasMSA() const { return (STI.getFeatureBits() & Mips::FeatureMSA); }
> 
>    bool inMips16Mode() const {
> -    return STI.getFeatureBits()[Mips::FeatureMips16];
> +    return STI.getFeatureBits() & Mips::FeatureMips16;
>    }
>    // TODO: see how can we get this info.
>    bool abiUsesSoftFloat() const { return false; }
> 
> Modified: llvm/trunk/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
> URL: http://llvm.org/viewvc/llvm-
> project/llvm/trunk/lib/Target/Mips/Disassembler/MipsDisassembler.cpp?re
> v=229841&r1=229840&r2=229841&view=diff
> ==========================================================
> ====================
> --- llvm/trunk/lib/Target/Mips/Disassembler/MipsDisassembler.cpp (original)
> +++ llvm/trunk/lib/Target/Mips/Disassembler/MipsDisassembler.cpp Thu
> Feb 19 05:38:11 2015
> @@ -36,16 +36,16 @@ class MipsDisassembler : public MCDisass
>  public:
>    MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, bool
> IsBigEndian)
>        : MCDisassembler(STI, Ctx),
> -        IsMicroMips(STI.getFeatureBits()[Mips::FeatureMicroMips]),
> +        IsMicroMips(STI.getFeatureBits() & Mips::FeatureMicroMips),
>          IsBigEndian(IsBigEndian) {}
> 
> -  bool hasMips3() const { return STI.getFeatureBits()[Mips::FeatureMips3]; }
> -  bool hasMips32() const { return
> STI.getFeatureBits()[Mips::FeatureMips32]; }
> +  bool hasMips3() const { return STI.getFeatureBits() & Mips::FeatureMips3;
> }
> +  bool hasMips32() const { return STI.getFeatureBits() &
> Mips::FeatureMips32; }
>    bool hasMips32r6() const {
> -    return STI.getFeatureBits()[Mips::FeatureMips32r6];
> +    return STI.getFeatureBits() & Mips::FeatureMips32r6;
>    }
> 
> -  bool isGP64() const { return STI.getFeatureBits()[Mips::FeatureGP64Bit]; }
> +  bool isGP64() const { return STI.getFeatureBits() & Mips::FeatureGP64Bit; }
> 
>    bool hasCOP3() const {
>      // Only present in MIPS-I and MIPS-II
> 
> Modified:
> llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
> URL: http://llvm.org/viewvc/llvm-
> project/llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
> ?rev=229841&r1=229840&r2=229841&view=diff
> ==========================================================
> ====================
> --- llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
> (original)
> +++ llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
> Thu Feb 19 05:38:11 2015
> @@ -114,7 +114,7 @@ static void LowerDextDins(MCInst& InstIn
>  }
> 
>  bool MipsMCCodeEmitter::isMicroMips(const MCSubtargetInfo &STI) const {
> -  return STI.getFeatureBits()[Mips::FeatureMicroMips];
> +  return STI.getFeatureBits() & Mips::FeatureMicroMips;
>  }
> 
>  void MipsMCCodeEmitter::EmitByte(unsigned char C, raw_ostream &OS)
> const {
> @@ -177,7 +177,7 @@ EncodeInstruction(const MCInst &MI, raw_
>        (Opcode != Mips::SLL_MM) && !Binary)
>      llvm_unreachable("unimplemented opcode in EncodeInstruction()");
> 
> -  if (STI.getFeatureBits()[Mips::FeatureMicroMips]) {
> +  if (STI.getFeatureBits() & Mips::FeatureMicroMips) {
>      int NewOpcode = Mips::Std2MicroMips (Opcode, Mips::Arch_micromips);
>      if (NewOpcode != -1) {
>        if (Fixups.size() > N)
> 
> Modified:
> llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp
> URL: http://llvm.org/viewvc/llvm-
> project/llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp
> ?rev=229841&r1=229840&r2=229841&view=diff
> ==========================================================
> ====================
> --- llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp
> (original)
> +++ llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp
> Thu Feb 19 05:38:11 2015
> @@ -367,13 +367,12 @@ MipsTargetELFStreamer::MipsTargetELFStre
>                                               const MCSubtargetInfo &STI)
>      : MipsTargetStreamer(S), MicroMipsEnabled(false), STI(STI) {
>    MCAssembler &MCA = getStreamer().getAssembler();
> -
>    Triple T(STI.getTargetTriple());
>    Pic = (MCA.getContext().getObjectFileInfo()->getRelocM() == Reloc::PIC_)
>              ? true
>              : false;
> 
> -  const FeatureBitset &Features = STI.getFeatureBits();
> +  uint64_t Features = STI.getFeatureBits();
> 
>    // Set the header flags that we can in the constructor.
>    // FIXME: This is a fairly terrible hack. We set the rest
> @@ -389,35 +388,35 @@ MipsTargetELFStreamer::MipsTargetELFStre
>    unsigned EFlags = MCA.getELFHeaderEFlags();
> 
>    // Architecture
> -  if (Features[Mips::FeatureMips64r6])
> +  if (Features & Mips::FeatureMips64r6)
>      EFlags |= ELF::EF_MIPS_ARCH_64R6;
> -  else if (Features[Mips::FeatureMips64r2] ||
> -           Features[Mips::FeatureMips64r3] ||
> -           Features[Mips::FeatureMips64r5])
> +  else if (Features & Mips::FeatureMips64r2 ||
> +           Features & Mips::FeatureMips64r3 ||
> +           Features & Mips::FeatureMips64r5)
>      EFlags |= ELF::EF_MIPS_ARCH_64R2;
> -  else if (Features[Mips::FeatureMips64])
> +  else if (Features & Mips::FeatureMips64)
>      EFlags |= ELF::EF_MIPS_ARCH_64;
> -  else if (Features[Mips::FeatureMips5])
> +  else if (Features & Mips::FeatureMips5)
>      EFlags |= ELF::EF_MIPS_ARCH_5;
> -  else if (Features[Mips::FeatureMips4])
> +  else if (Features & Mips::FeatureMips4)
>      EFlags |= ELF::EF_MIPS_ARCH_4;
> -  else if (Features[Mips::FeatureMips3])
> +  else if (Features & Mips::FeatureMips3)
>      EFlags |= ELF::EF_MIPS_ARCH_3;
> -  else if (Features[Mips::FeatureMips32r6])
> +  else if (Features & Mips::FeatureMips32r6)
>      EFlags |= ELF::EF_MIPS_ARCH_32R6;
> -  else if (Features[Mips::FeatureMips32r2] ||
> -           Features[Mips::FeatureMips32r3] ||
> -           Features[Mips::FeatureMips32r5])
> +  else if (Features & Mips::FeatureMips32r2 ||
> +           Features & Mips::FeatureMips32r3 ||
> +           Features & Mips::FeatureMips32r5)
>      EFlags |= ELF::EF_MIPS_ARCH_32R2;
> -  else if (Features[Mips::FeatureMips32])
> +  else if (Features & Mips::FeatureMips32)
>      EFlags |= ELF::EF_MIPS_ARCH_32;
> -  else if (Features[Mips::FeatureMips2])
> +  else if (Features & Mips::FeatureMips2)
>      EFlags |= ELF::EF_MIPS_ARCH_2;
>    else
>      EFlags |= ELF::EF_MIPS_ARCH_1;
> 
>    // Other options.
> -  if (Features[Mips::FeatureNaN2008])
> +  if (Features & Mips::FeatureNaN2008)
>      EFlags |= ELF::EF_MIPS_NAN2008;
> 
>    // -mabicalls and -mplt are not implemented but we should act as if they
> were
> @@ -457,7 +456,7 @@ void MipsTargetELFStreamer::finish() {
>    DataSectionData.setAlignment(std::max(16u,
> DataSectionData.getAlignment()));
>    BSSSectionData.setAlignment(std::max(16u,
> BSSSectionData.getAlignment()));
> 
> -  const FeatureBitset &Features = STI.getFeatureBits();
> +  uint64_t Features = STI.getFeatureBits();
> 
>    // Update e_header flags. See the FIXME and comment above in
>    // the constructor for a full rundown on this.
> @@ -470,10 +469,10 @@ void MipsTargetELFStreamer::finish() {
>    else if (getABI().IsN32())
>      EFlags |= ELF::EF_MIPS_ABI2;
> 
> -  if (Features[Mips::FeatureGP64Bit]) {
> +  if (Features & Mips::FeatureGP64Bit) {
>      if (getABI().IsO32())
>        EFlags |= ELF::EF_MIPS_32BITMODE; /* Compatibility Mode */
> -  } else if (Features[Mips::FeatureMips64r2] ||
> Features[Mips::FeatureMips64])
> +  } else if (Features & Mips::FeatureMips64r2 || Features &
> Mips::FeatureMips64)
>      EFlags |= ELF::EF_MIPS_32BITMODE;
> 
>    // If we've set the cpic eflag and we're n64, go ahead and set the pic
> 
> Modified:
> llvm/trunk/lib/Target/R600/MCTargetDesc/AMDGPUMCTargetDesc.cpp
> URL: http://llvm.org/viewvc/llvm-
> project/llvm/trunk/lib/Target/R600/MCTargetDesc/AMDGPUMCTargetDesc.
> cpp?rev=229841&r1=229840&r2=229841&view=diff
> ==========================================================
> ====================
> --- llvm/trunk/lib/Target/R600/MCTargetDesc/AMDGPUMCTargetDesc.cpp
> (original)
> +++ llvm/trunk/lib/Target/R600/MCTargetDesc/AMDGPUMCTargetDesc.cpp
> Thu Feb 19 05:38:11 2015
> @@ -76,7 +76,7 @@ static MCCodeEmitter *createAMDGPUMCCode
>                                                  const MCRegisterInfo &MRI,
>                                                  const MCSubtargetInfo &STI,
>                                                  MCContext &Ctx) {
> -  if (STI.getFeatureBits()[AMDGPU::Feature64BitPtr]) {
> +  if (STI.getFeatureBits() & AMDGPU::Feature64BitPtr) {
>      return createSIMCCodeEmitter(MCII, MRI, STI, Ctx);
>    } else {
>      return createR600MCCodeEmitter(MCII, MRI, STI);
> 
> Modified:
> llvm/trunk/lib/Target/R600/MCTargetDesc/R600MCCodeEmitter.cpp
> URL: http://llvm.org/viewvc/llvm-
> project/llvm/trunk/lib/Target/R600/MCTargetDesc/R600MCCodeEmitter.cpp
> ?rev=229841&r1=229840&r2=229841&view=diff
> ==========================================================
> ====================
> --- llvm/trunk/lib/Target/R600/MCTargetDesc/R600MCCodeEmitter.cpp
> (original)
> +++ llvm/trunk/lib/Target/R600/MCTargetDesc/R600MCCodeEmitter.cpp
> Thu Feb 19 05:38:11 2015
> @@ -99,7 +99,7 @@ void R600MCCodeEmitter::EncodeInstructio
>    } else if (IS_VTX(Desc)) {
>      uint64_t InstWord01 = getBinaryCodeForInstr(MI, Fixups, STI);
>      uint32_t InstWord2 = MI.getOperand(2).getImm(); // Offset
> -    if (!(STI.getFeatureBits()[AMDGPU::FeatureCaymanISA])) {
> +    if (!(STI.getFeatureBits() & AMDGPU::FeatureCaymanISA)) {
>        InstWord2 |= 1 << 19; // Mega-Fetch bit
>      }
> 
> @@ -132,7 +132,7 @@ void R600MCCodeEmitter::EncodeInstructio
>        Emit((uint32_t) 0, OS);
>    } else {
>      uint64_t Inst = getBinaryCodeForInstr(MI, Fixups, STI);
> -    if ((STI.getFeatureBits()[AMDGPU::FeatureR600ALUInst]) &&
> +    if ((STI.getFeatureBits() & AMDGPU::FeatureR600ALUInst) &&
>         ((Desc.TSFlags & R600_InstFlag::OP1) ||
>           Desc.TSFlags & R600_InstFlag::OP2)) {
>        uint64_t ISAOpCode = Inst & (0x3FFULL << 39);
> 
> Modified: llvm/trunk/lib/Target/Sparc/InstPrinter/SparcInstPrinter.cpp
> URL: http://llvm.org/viewvc/llvm-
> project/llvm/trunk/lib/Target/Sparc/InstPrinter/SparcInstPrinter.cpp?rev=22
> 9841&r1=229840&r2=229841&view=diff
> ==========================================================
> ====================
> --- llvm/trunk/lib/Target/Sparc/InstPrinter/SparcInstPrinter.cpp (original)
> +++ llvm/trunk/lib/Target/Sparc/InstPrinter/SparcInstPrinter.cpp Thu Feb 19
> 05:38:11 2015
> @@ -35,7 +35,7 @@ namespace Sparc {
>  #include "SparcGenAsmWriter.inc"
> 
>  bool SparcInstPrinter::isV9() const {
> -  return (STI.getFeatureBits()[Sparc::FeatureV9]) != 0;
> +  return (STI.getFeatureBits() & Sparc::FeatureV9) != 0;
>  }
> 
>  void SparcInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo)
> const
> 
> Modified:
> llvm/trunk/lib/Target/X86/AsmParser/X86AsmInstrumentation.cpp
> URL: http://llvm.org/viewvc/llvm-
> project/llvm/trunk/lib/Target/X86/AsmParser/X86AsmInstrumentation.cpp?
> rev=229841&r1=229840&r2=229841&view=diff
> ==========================================================
> ====================
> --- llvm/trunk/lib/Target/X86/AsmParser/X86AsmInstrumentation.cpp
> (original)
> +++ llvm/trunk/lib/Target/X86/AsmParser/X86AsmInstrumentation.cpp Thu
> Feb 19 05:38:11 2015
> @@ -262,13 +262,13 @@ protected:
>                                                MCContext &Ctx, int64_t *Residue);
> 
>    bool is64BitMode() const {
> -    return STI.getFeatureBits()[X86::Mode64Bit];
> +    return (STI.getFeatureBits() & X86::Mode64Bit) != 0;
>    }
>    bool is32BitMode() const {
> -    return STI.getFeatureBits()[X86::Mode32Bit];
> +    return (STI.getFeatureBits() & X86::Mode32Bit) != 0;
>    }
>    bool is16BitMode() const {
> -    return STI.getFeatureBits()[X86::Mode16Bit];
> +    return (STI.getFeatureBits() & X86::Mode16Bit) != 0;
>    }
> 
>    unsigned getPointerWidth() {
> @@ -1073,9 +1073,9 @@ CreateX86AsmInstrumentation(const MCTarg
>    const bool hasCompilerRTSupport = T.isOSLinux();
>    if (ClAsanInstrumentAssembly && hasCompilerRTSupport &&
>        MCOptions.SanitizeAddress) {
> -    if (STI.getFeatureBits()[X86::Mode32Bit] != 0)
> +    if ((STI.getFeatureBits() & X86::Mode32Bit) != 0)
>        return new X86AddressSanitizer32(STI);
> -    if (STI.getFeatureBits()[X86::Mode64Bit] != 0)
> +    if ((STI.getFeatureBits() & X86::Mode64Bit) != 0)
>        return new X86AddressSanitizer64(STI);
>    }
>    return new X86AsmInstrumentation(STI);
> 
> Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp
> URL: http://llvm.org/viewvc/llvm-
> project/llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp?rev=22984
> 1&r1=229840&r2=229841&view=diff
> ==========================================================
> ====================
> --- llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp (original)
> +++ llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp Thu Feb 19
> 05:38:11 2015
> @@ -727,24 +727,23 @@ private:
> 
>    bool is64BitMode() const {
>      // FIXME: Can tablegen auto-generate this?
> -    return STI.getFeatureBits()[X86::Mode64Bit];
> +    return (STI.getFeatureBits() & X86::Mode64Bit) != 0;
>    }
>    bool is32BitMode() const {
>      // FIXME: Can tablegen auto-generate this?
> -    return STI.getFeatureBits()[X86::Mode32Bit];
> +    return (STI.getFeatureBits() & X86::Mode32Bit) != 0;
>    }
>    bool is16BitMode() const {
>      // FIXME: Can tablegen auto-generate this?
> -    return STI.getFeatureBits()[X86::Mode16Bit];
> +    return (STI.getFeatureBits() & X86::Mode16Bit) != 0;
>    }
> -  void SwitchMode(unsigned mode) {
> -    FeatureBitset AllModes({X86::Mode64Bit, X86::Mode32Bit,
> X86::Mode16Bit});
> -    FeatureBitset OldMode = STI.getFeatureBits() & AllModes;
> -    unsigned FB = ComputeAvailableFeatures(
> -      STI.ToggleFeature(OldMode.flip(mode)));
> +  void SwitchMode(uint64_t mode) {
> +    uint64_t oldMode = STI.getFeatureBits() &
> +        (X86::Mode64Bit | X86::Mode32Bit | X86::Mode16Bit);
> +    unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(oldMode |
> mode));
>      setAvailableFeatures(FB);
> -
> -    assert(FeatureBitset({mode}) == (STI.getFeatureBits() & AllModes));
> +    assert(mode == (STI.getFeatureBits() &
> +                    (X86::Mode64Bit | X86::Mode32Bit | X86::Mode16Bit)));
>    }
> 
>    unsigned getPointerWidth() {
> @@ -1715,7 +1714,7 @@ std::unique_ptr<X86Operand> X86AsmParser
>  bool X86AsmParser::HandleAVX512Operand(OperandVector &Operands,
>                                         const MCParsedAsmOperand &Op) {
>    MCAsmParser &Parser = getParser();
> -  if(STI.getFeatureBits()[X86::FeatureAVX512]) {
> +  if(STI.getFeatureBits() & X86::FeatureAVX512) {
>      if (getLexer().is(AsmToken::LCurly)) {
>        // Eat "{" and mark the current place.
>        const SMLoc consumedToken = consumeToken();
> 
> Modified: llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.cpp
> URL: http://llvm.org/viewvc/llvm-
> project/llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.cpp?rev=
> 229841&r1=229840&r2=229841&view=diff
> ==========================================================
> ====================
> --- llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.cpp (original)
> +++ llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.cpp Thu Feb
> 19 05:38:11 2015
> @@ -80,19 +80,20 @@ X86GenericDisassembler::X86GenericDisass
>                                           MCContext &Ctx,
>                                           std::unique_ptr<const MCInstrInfo> MII)
>    : MCDisassembler(STI, Ctx), MII(std::move(MII)) {
> -  const FeatureBitset &FB = STI.getFeatureBits();
> -  if (FB[X86::Mode16Bit]) {
> +  switch (STI.getFeatureBits() &
> +          (X86::Mode16Bit | X86::Mode32Bit | X86::Mode64Bit)) {
> +  case X86::Mode16Bit:
>      fMode = MODE_16BIT;
> -    return;
> -  } else if (FB[X86::Mode32Bit]) {
> +    break;
> +  case X86::Mode32Bit:
>      fMode = MODE_32BIT;
> -    return;
> -  } else if (FB[X86::Mode64Bit]) {
> +    break;
> +  case X86::Mode64Bit:
>      fMode = MODE_64BIT;
> -    return;
> +    break;
> +  default:
> +    llvm_unreachable("Invalid CPU mode");
>    }
> -
> -  llvm_unreachable("Invalid CPU mode");
>  }
> 
>  struct Region {
> 
> Modified: llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp
> URL: http://llvm.org/viewvc/llvm-
> project/llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp?rev=22
> 9841&r1=229840&r2=229841&view=diff
> ==========================================================
> ====================
> --- llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp (original)
> +++ llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp Thu Feb 19
> 05:38:11 2015
> @@ -60,7 +60,7 @@ void X86ATTInstPrinter::printInst(const
>    // InstrInfo.td as soon as Requires clause is supported properly
>    // for InstAlias.
>    if (MI->getOpcode() == X86::CALLpcrel32 &&
> -      getAvailableFeatures()[X86::Mode64Bit]) {
> +      (getAvailableFeatures() & X86::Mode64Bit) != 0) {
>      OS << "\tcallq\t";
>      printPCRelImm(MI, 0, OS);
>    }
> 
> Modified: llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
> URL: http://llvm.org/viewvc/llvm-
> project/llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp?r
> ev=229841&r1=229840&r2=229841&view=diff
> ==========================================================
> ====================
> --- llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
> (original)
> +++ llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp Thu
> Feb 19 05:38:11 2015
> @@ -42,15 +42,15 @@ public:
>    ~X86MCCodeEmitter() {}
> 
>    bool is64BitMode(const MCSubtargetInfo &STI) const {
> -    return STI.getFeatureBits()[X86::Mode64Bit];
> +    return (STI.getFeatureBits() & X86::Mode64Bit) != 0;
>    }
> 
>    bool is32BitMode(const MCSubtargetInfo &STI) const {
> -    return STI.getFeatureBits()[X86::Mode32Bit];
> +    return (STI.getFeatureBits() & X86::Mode32Bit) != 0;
>    }
> 
>    bool is16BitMode(const MCSubtargetInfo &STI) const {
> -    return STI.getFeatureBits()[X86::Mode16Bit];
> +    return (STI.getFeatureBits() & X86::Mode16Bit) != 0;
>    }
> 
>    /// Is16BitMemOperand - Return true if the specified instruction has
> 
> Modified: llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp
> URL: http://llvm.org/viewvc/llvm-
> project/llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp?rev=229841&r1
> =229840&r2=229841&view=diff
> ==========================================================
> ====================
> --- llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp (original)
> +++ llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Thu Feb 19 05:38:11
> 2015
> @@ -2242,7 +2242,7 @@ static void emitComputeAvailableFeatures
>      Info.AsmParser->getValueAsString("AsmParserClassName");
> 
>    OS << "uint64_t " << Info.Target.getName() << ClassName << "::\n"
> -     << "ComputeAvailableFeatures(const FeatureBitset& FB) const {\n";
> +     << "ComputeAvailableFeatures(uint64_t FB) const {\n";
>    OS << "  uint64_t Features = 0;\n";
>    for (const auto &SF : Info.SubtargetFeatures) {
>      const SubtargetFeatureInfo &SFI = SF.second;
> @@ -2264,10 +2264,12 @@ static void emitComputeAvailableFeatures
>          Cond = Cond.substr(1);
>        }
> 
> -      OS << "(";
> +      OS << "((FB & " << Info.Target.getName() << "::" << Cond << ")";
>        if (Neg)
> -        OS << "!";
> -      OS << "FB[" << Info.Target.getName() << "::" << Cond << "])";
> +        OS << " == 0";
> +      else
> +        OS << " != 0";
> +      OS << ")";
> 
>        if (Comma.second.empty())
>          break;
> @@ -2637,7 +2639,7 @@ void AsmMatcherEmitter::run(raw_ostream
>    OS << "#undef GET_ASSEMBLER_HEADER\n";
>    OS << "  // This should be included into the middle of the declaration of\n";
>    OS << "  // your subclasses implementation of MCTargetAsmParser.\n";
> -  OS << "  uint64_t ComputeAvailableFeatures(const FeatureBitset& FB)
> const;\n";
> +  OS << "  uint64_t ComputeAvailableFeatures(uint64_t FeatureBits)
> const;\n";
>    OS << "  void convertToMCInst(unsigned Kind, MCInst &Inst, "
>       << "unsigned Opcode,\n"
>       << "                       const OperandVector "
> 
> Modified: llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.cpp
> URL: http://llvm.org/viewvc/llvm-
> project/llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.cpp?rev=22984
> 1&r1=229840&r2=229841&view=diff
> ==========================================================
> ====================
> --- llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.cpp (original)
> +++ llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.cpp Thu Feb 19
> 05:38:11 2015
> @@ -848,7 +848,7 @@ emitPredicateFunction(formatted_raw_ostr
>    // The predicate function is just a big switch statement based on the
>    // input predicate index.
>    OS.indent(Indentation) << "static bool checkDecoderPredicate(unsigned
> Idx, "
> -    << "const FeatureBitset& Bits) {\n";
> +    << "uint64_t Bits) {\n";
>    Indentation += 2;
>    if (!Predicates.empty()) {
>      OS.indent(Indentation) << "switch (Idx) {\n";
> @@ -1102,10 +1102,10 @@ unsigned FilterChooser::getDecoderIndex(
>  static void emitSinglePredicateMatch(raw_ostream &o, StringRef str,
>                                       const std::string &PredicateNamespace) {
>    if (str[0] == '!')
> -    o << "!Bits[" << PredicateNamespace << "::"
> -      << str.slice(1,str.size()) << "]";
> +    o << "!(Bits & " << PredicateNamespace << "::"
> +      << str.slice(1,str.size()) << ")";
>    else
> -    o << "Bits[" << PredicateNamespace << "::" << str << "]";
> +    o << "(Bits & " << PredicateNamespace << "::" << str << ")";
>  }
> 
>  bool FilterChooser::emitPredicateMatch(raw_ostream &o, unsigned
> &Indentation,
> @@ -2010,7 +2010,7 @@ static void emitDecodeInstruction(format
>       << "                                      InsnType insn, uint64_t Address,\n"
>       << "                                      const void *DisAsm,\n"
>       << "                                      const MCSubtargetInfo &STI) {\n"
> -     << "  const FeatureBitset& Bits = STI.getFeatureBits();\n"
> +     << "  uint64_t Bits = STI.getFeatureBits();\n"
>       << "\n"
>       << "  const uint8_t *Ptr = DecodeTable;\n"
>       << "  uint32_t CurFieldValue = 0;\n"
> 
> Modified: llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp
> URL: http://llvm.org/viewvc/llvm-
> project/llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp?rev=229841&r1=229
> 840&r2=229841&view=diff
> ==========================================================
> ====================
> --- llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp (original)
> +++ llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp Thu Feb 19 05:38:11 2015
> @@ -547,15 +547,15 @@ void InstrInfoEmitter::emitRecord(const
>    CodeGenTarget &Target = CDP.getTargetInfo();
>    if (Inst.HasComplexDeprecationPredicate)
>      // Emit a function pointer to the complex predicate method.
> -    OS << ", { } "
> +    OS << ",0"
>         << ",&get" << Inst.DeprecatedReason << "DeprecationInfo";
>    else if (!Inst.DeprecatedReason.empty())
>      // Emit the Subtarget feature.
> -    OS << ", { " << Target.getInstNamespace() << "::" <<
> Inst.DeprecatedReason
> -       << "} ,nullptr";
> +    OS << "," << Target.getInstNamespace() << "::" <<
> Inst.DeprecatedReason
> +       << ",nullptr";
>    else
>      // Instruction isn't deprecated.
> -    OS << ", { } ,nullptr";
> +    OS << ",0,nullptr";
> 
>    OS << " },  // Inst #" << Num << " = " << Inst.TheDef->getName() << "\n";
>  }
> 
> Modified: llvm/trunk/utils/TableGen/SubtargetEmitter.cpp
> URL: http://llvm.org/viewvc/llvm-
> project/llvm/trunk/utils/TableGen/SubtargetEmitter.cpp?rev=229841&r1=22
> 9840&r2=229841&view=diff
> ==========================================================
> ====================
> --- llvm/trunk/utils/TableGen/SubtargetEmitter.cpp (original)
> +++ llvm/trunk/utils/TableGen/SubtargetEmitter.cpp Thu Feb 19 05:38:11
> 2015
> @@ -16,7 +16,6 @@
>  #include "llvm/ADT/STLExtras.h"
>  #include "llvm/ADT/StringExtras.h"
>  #include "llvm/MC/MCInstrItineraries.h"
> -#include "llvm/MC/SubtargetFeature.h"
>  #include "llvm/Support/Debug.h"
>  #include "llvm/Support/Format.h"
>  #include "llvm/TableGen/Error.h"
> @@ -63,7 +62,7 @@ class SubtargetEmitter {
>    CodeGenSchedModels &SchedModels;
>    std::string Target;
> 
> -  void Enumeration(raw_ostream &OS, const char *ClassName);
> +  void Enumeration(raw_ostream &OS, const char *ClassName, bool isBits);
>    unsigned FeatureKeyValues(raw_ostream &OS);
>    unsigned CPUKeyValues(raw_ostream &OS);
>    void FormItineraryStageString(const std::string &Names,
> @@ -113,7 +112,8 @@ public:
>  // Enumeration - Emit the specified class as an enumeration.
>  //
>  void SubtargetEmitter::Enumeration(raw_ostream &OS,
> -                                   const char *ClassName) {
> +                                   const char *ClassName,
> +                                   bool isBits) {
>    // Get all records of class and sort
>    std::vector<Record*> DefList =
> Records.getAllDerivedDefinitions(ClassName);
>    std::sort(DefList.begin(), DefList.end(), LessRecord());
> @@ -121,30 +121,50 @@ void SubtargetEmitter::Enumeration(raw_o
>    unsigned N = DefList.size();
>    if (N == 0)
>      return;
> -  if (N > MAX_SUBTARGET_FEATURES) {
> -    errs() << "Too many subtarget features! Bump
> MAX_SUBTARGET_FEATURES.";
> +  if (N > 64) {
> +    errs() << "Too many (> 64) subtarget features!\n";
>      exit(1);
>    }
> 
>    OS << "namespace " << Target << " {\n";
> 
> -  // Open enumeration
> -  OS << "enum {\n";
> +  // For bit flag enumerations with more than 32 items, emit constants.
> +  // Emit an enum for everything else.
> +  if (isBits && N > 32) {
> +    // For each record
> +    for (unsigned i = 0; i < N; i++) {
> +      // Next record
> +      Record *Def = DefList[i];
> 
> -  // For each record
> -  for (unsigned i = 0; i < N;) {
> -    // Next record
> -    Record *Def = DefList[i];
> +      // Get and emit name and expression (1 << i)
> +      OS << "  const uint64_t " << Def->getName() << " = 1ULL << " << i <<
> ";\n";
> +    }
> +  } else {
> +    // Open enumeration
> +    OS << "enum {\n";
> 
> -    // Get and emit name
> -    OS << "  " << Def->getName() << " = " << i;
> -    if (++i < N) OS << ",";
> +    // For each record
> +    for (unsigned i = 0; i < N;) {
> +      // Next record
> +      Record *Def = DefList[i];
> 
> -    OS << "\n";
> +      // Get and emit name
> +      OS << "  " << Def->getName();
> +
> +      // If bit flags then emit expression (1 << i)
> +      if (isBits)  OS << " = " << " 1ULL << " << i;
> +
> +      // Depending on 'if more in the list' emit comma
> +      if (++i < N) OS << ",";
> +
> +      OS << "\n";
> +    }
> +
> +    // Close enumeration
> +    OS << "};\n";
>    }
> 
> -  // Close enumeration and namespace
> -  OS << "};\n}\n";
> +  OS << "}\n";
>  }
> 
>  //
> @@ -178,24 +198,22 @@ unsigned SubtargetEmitter::FeatureKeyVal
> 
>      if (CommandLineName.empty()) continue;
> 
> -    // Emit as { "feature", "description", { featureEnum }, { i1 , i2 , ... , in } }
> +    // Emit as { "feature", "description", featureEnum, i1 | i2 | ... | in }
>      OS << "  { "
>         << "\"" << CommandLineName << "\", "
>         << "\"" << Desc << "\", "
> -       << "{ " << Target << "::" << Name << " }, ";
> +       << Target << "::" << Name << ", ";
> 
>      const std::vector<Record*> &ImpliesList =
>        Feature->getValueAsListOfDefs("Implies");
> 
>      if (ImpliesList.empty()) {
> -      OS << "{ }";
> +      OS << "0ULL";
>      } else {
> -      OS << "{ ";
>        for (unsigned j = 0, M = ImpliesList.size(); j < M;) {
>          OS << Target << "::" << ImpliesList[j]->getName();
> -        if (++j < M) OS << ", ";
> +        if (++j < M) OS << " | ";
>        }
> -      OS << " }";
>      }
> 
>      OS << " }";
> @@ -237,24 +255,22 @@ unsigned SubtargetEmitter::CPUKeyValues(
>      const std::vector<Record*> &FeatureList =
>        Processor->getValueAsListOfDefs("Features");
> 
> -    // Emit as { "cpu", "description", { f1 , f2 , ... fn } },
> +    // Emit as { "cpu", "description", f1 | f2 | ... fn },
>      OS << "  { "
>         << "\"" << Name << "\", "
>         << "\"Select the " << Name << " processor\", ";
> 
>      if (FeatureList.empty()) {
> -      OS << "{ }";
> +      OS << "0ULL";
>      } else {
> -      OS << "{ ";
>        for (unsigned j = 0, M = FeatureList.size(); j < M;) {
>          OS << Target << "::" << FeatureList[j]->getName();
> -        if (++j < M) OS << ", ";
> +        if (++j < M) OS << " | ";
>        }
> -      OS << " }";
>      }
> 
> -    // The { } is for the "implies" section of this data structure.
> -    OS << ", { } }";
> +    // The "0" is for the "implies" section of this data structure.
> +    OS << ", 0ULL }";
> 
>      // Depending on 'if more in the list' emit comma
>      if (++i < N) OS << ",";
> @@ -1382,7 +1398,7 @@ void SubtargetEmitter::ParseFeaturesFunc
>    }
> 
>    OS << "  InitMCProcessorInfo(CPU, FS);\n"
> -     << "  const FeatureBitset& Bits = getFeatureBits();\n";
> +     << "  uint64_t Bits = getFeatureBits();\n";
> 
>    for (unsigned i = 0; i < Features.size(); i++) {
>      // Next record
> @@ -1392,12 +1408,12 @@ void SubtargetEmitter::ParseFeaturesFunc
>      const std::string &Attribute = R->getValueAsString("Attribute");
> 
>      if (Value=="true" || Value=="false")
> -      OS << "  if (Bits[" << Target << "::"
> -         << Instance << "]) "
> +      OS << "  if ((Bits & " << Target << "::"
> +         << Instance << ") != 0) "
>           << Attribute << " = " << Value << ";\n";
>      else
> -      OS << "  if (Bits[" << Target << "::"
> -         << Instance << "] && "
> +      OS << "  if ((Bits & " << Target << "::"
> +         << Instance << ") != 0 && "
>           << Attribute << " < " << Value << ") "
>           << Attribute << " = " << Value << ";\n";
>    }
> @@ -1415,7 +1431,7 @@ void SubtargetEmitter::run(raw_ostream &
>    OS << "#undef GET_SUBTARGETINFO_ENUM\n";
> 
>    OS << "namespace llvm {\n";
> -  Enumeration(OS, "SubtargetFeature");
> +  Enumeration(OS, "SubtargetFeature", true);
>    OS << "} // End llvm namespace \n";
>    OS << "#endif // GET_SUBTARGETINFO_ENUM\n\n";
> 
> 
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
> ---------------------------------------------------------------------
> Intel Israel (74) Limited
> 
> This e-mail and any attachments may contain confidential material for
> the sole use of the intended recipient(s). Any review or distribution
> by others is strictly prohibited. If you are not the intended
> recipient, please contact the sender and delete all copies.
> 
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
---------------------------------------------------------------------
Intel Israel (74) Limited

This e-mail and any attachments may contain confidential material for
the sole use of the intended recipient(s). Any review or distribution
by others is strictly prohibited. If you are not the intended
recipient, please contact the sender and delete all copies.





More information about the llvm-commits mailing list