[llvm] r229999 - Get the cached subtarget off the MachineFunction rather than
Eric Christopher
echristo at gmail.com
Fri Feb 20 00:24:37 PST 2015
Author: echristo
Date: Fri Feb 20 02:24:37 2015
New Revision: 229999
URL: http://llvm.org/viewvc/llvm-project?rev=229999&view=rev
Log:
Get the cached subtarget off the MachineFunction rather than
inquiring for a new one from the TargetMachine.
Modified:
llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp
llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp
llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp
llvm/trunk/lib/Target/ARM/ARMMachineFunctionInfo.cpp
llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td
llvm/trunk/lib/Target/ARM/ARMSelectionDAGInfo.cpp
llvm/trunk/lib/Target/ARM/MLxExpansionPass.cpp
llvm/trunk/lib/Target/ARM/Thumb1InstrInfo.cpp
Modified: llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp?rev=229999&r1=229998&r2=229999&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp Fri Feb 20 02:24:37 2015
@@ -1864,7 +1864,7 @@ static const uint64_t kSplitStackAvailab
void ARMFrameLowering::adjustForSegmentedStacks(MachineFunction &MF) const {
unsigned Opcode;
unsigned CFIIndex;
- const ARMSubtarget *ST = &MF.getTarget().getSubtarget<ARMSubtarget>();
+ const ARMSubtarget *ST = &MF.getSubtarget<ARMSubtarget>();
bool Thumb = ST->isThumb();
// Sadly, this currently doesn't support varargs, platforms other than
Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp?rev=229999&r1=229998&r2=229999&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Fri Feb 20 02:24:37 2015
@@ -70,7 +70,7 @@ public:
bool runOnMachineFunction(MachineFunction &MF) override {
// Reset the subtarget each time through.
- Subtarget = &MF.getTarget().getSubtarget<ARMSubtarget>();
+ Subtarget = &MF.getSubtarget<ARMSubtarget>();
SelectionDAGISel::runOnMachineFunction(MF);
return true;
}
Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp?rev=229999&r1=229998&r2=229999&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp Fri Feb 20 02:24:37 2015
@@ -93,7 +93,7 @@ unsigned ARMInstrInfo::getUnindexedOpcod
void ARMInstrInfo::expandLoadStackGuard(MachineBasicBlock::iterator MI,
Reloc::Model RM) const {
MachineFunction &MF = *MI->getParent()->getParent();
- const ARMSubtarget &Subtarget = MF.getTarget().getSubtarget<ARMSubtarget>();
+ const ARMSubtarget &Subtarget = MF.getSubtarget<ARMSubtarget>();
if (!Subtarget.useMovt(MF)) {
if (RM == Reloc::PIC_)
Modified: llvm/trunk/lib/Target/ARM/ARMMachineFunctionInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMachineFunctionInfo.cpp?rev=229999&r1=229998&r2=229999&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMMachineFunctionInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMMachineFunctionInfo.cpp Fri Feb 20 02:24:37 2015
@@ -14,8 +14,8 @@ using namespace llvm;
void ARMFunctionInfo::anchor() { }
ARMFunctionInfo::ARMFunctionInfo(MachineFunction &MF)
- : isThumb(MF.getTarget().getSubtarget<ARMSubtarget>().isThumb()),
- hasThumb2(MF.getTarget().getSubtarget<ARMSubtarget>().hasThumb2()),
+ : isThumb(MF.getSubtarget<ARMSubtarget>().isThumb()),
+ hasThumb2(MF.getSubtarget<ARMSubtarget>().hasThumb2()),
StByValParamsPadding(0), ArgRegsSaveSize(0), HasStackFrame(false),
RestoreSPFromFP(false), LRSpilledForFarJump(false),
FramePtrSpillOffset(0), GPRCS1Offset(0), GPRCS2Offset(0), DPRCSOffset(0),
Modified: llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td?rev=229999&r1=229998&r2=229999&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td Fri Feb 20 02:24:37 2015
@@ -199,7 +199,7 @@ def GPR : RegisterClass<"ARM", [i32], 32
// Thumb1 instructions that know how to use hi regs.
let AltOrders = [(add LR, GPR), (trunc GPR, 8)];
let AltOrderSelect = [{
- return 1 + MF.getTarget().getSubtarget<ARMSubtarget>().isThumb1Only();
+ return 1 + MF.getSubtarget<ARMSubtarget>().isThumb1Only();
}];
}
@@ -209,7 +209,7 @@ def GPR : RegisterClass<"ARM", [i32], 32
def GPRnopc : RegisterClass<"ARM", [i32], 32, (sub GPR, PC)> {
let AltOrders = [(add LR, GPRnopc), (trunc GPRnopc, 8)];
let AltOrderSelect = [{
- return 1 + MF.getTarget().getSubtarget<ARMSubtarget>().isThumb1Only();
+ return 1 + MF.getSubtarget<ARMSubtarget>().isThumb1Only();
}];
}
@@ -219,7 +219,7 @@ def GPRnopc : RegisterClass<"ARM", [i32]
def GPRwithAPSR : RegisterClass<"ARM", [i32], 32, (add (sub GPR, PC), APSR_NZCV)> {
let AltOrders = [(add LR, GPRnopc), (trunc GPRnopc, 8)];
let AltOrderSelect = [{
- return 1 + MF.getTarget().getSubtarget<ARMSubtarget>().isThumb1Only();
+ return 1 + MF.getSubtarget<ARMSubtarget>().isThumb1Only();
}];
}
@@ -237,7 +237,7 @@ def GPRsp : RegisterClass<"ARM", [i32],
def rGPR : RegisterClass<"ARM", [i32], 32, (sub GPR, SP, PC)> {
let AltOrders = [(add LR, rGPR), (trunc rGPR, 8)];
let AltOrderSelect = [{
- return 1 + MF.getTarget().getSubtarget<ARMSubtarget>().isThumb1Only();
+ return 1 + MF.getSubtarget<ARMSubtarget>().isThumb1Only();
}];
}
@@ -255,7 +255,7 @@ def hGPR : RegisterClass<"ARM", [i32], 3
def tcGPR : RegisterClass<"ARM", [i32], 32, (add R0, R1, R2, R3, R12)> {
let AltOrders = [(and tcGPR, tGPR)];
let AltOrderSelect = [{
- return MF.getTarget().getSubtarget<ARMSubtarget>().isThumb1Only();
+ return MF.getSubtarget<ARMSubtarget>().isThumb1Only();
}];
}
Modified: llvm/trunk/lib/Target/ARM/ARMSelectionDAGInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSelectionDAGInfo.cpp?rev=229999&r1=229998&r2=229999&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMSelectionDAGInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMSelectionDAGInfo.cpp Fri Feb 20 02:24:37 2015
@@ -32,7 +32,8 @@ ARMSelectionDAGInfo::EmitTargetCodeForMe
bool isVolatile, bool AlwaysInline,
MachinePointerInfo DstPtrInfo,
MachinePointerInfo SrcPtrInfo) const {
- const ARMSubtarget &Subtarget = DAG.getTarget().getSubtarget<ARMSubtarget>();
+ const ARMSubtarget &Subtarget =
+ DAG.getMachineFunction().getSubtarget<ARMSubtarget>();
// Do repeated 4-byte loads and stores. To be improved.
// This requires 4-byte alignment.
if ((Align & 3) != 0)
@@ -150,14 +151,14 @@ EmitTargetCodeForMemset(SelectionDAG &DA
SDValue Src, SDValue Size,
unsigned Align, bool isVolatile,
MachinePointerInfo DstPtrInfo) const {
- const ARMSubtarget &Subtarget = DAG.getTarget().getSubtarget<ARMSubtarget>();
+ const ARMSubtarget &Subtarget =
+ DAG.getMachineFunction().getSubtarget<ARMSubtarget>();
// Use default for non-AAPCS (or MachO) subtargets
if (!Subtarget.isAAPCS_ABI() || Subtarget.isTargetMachO() ||
Subtarget.isTargetWindows())
return SDValue();
- const ARMTargetLowering &TLI =
- *DAG.getTarget().getSubtarget<ARMSubtarget>().getTargetLowering();
+ const ARMTargetLowering &TLI = *Subtarget.getTargetLowering();
TargetLowering::ArgListTy Args;
TargetLowering::ArgListEntry Entry;
Modified: llvm/trunk/lib/Target/ARM/MLxExpansionPass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MLxExpansionPass.cpp?rev=229999&r1=229998&r2=229999&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/MLxExpansionPass.cpp (original)
+++ llvm/trunk/lib/Target/ARM/MLxExpansionPass.cpp Fri Feb 20 02:24:37 2015
@@ -381,7 +381,7 @@ bool MLxExpansion::runOnMachineFunction(
TII = static_cast<const ARMBaseInstrInfo *>(Fn.getSubtarget().getInstrInfo());
TRI = Fn.getSubtarget().getRegisterInfo();
MRI = &Fn.getRegInfo();
- const ARMSubtarget *STI = &Fn.getTarget().getSubtarget<ARMSubtarget>();
+ const ARMSubtarget *STI = &Fn.getSubtarget<ARMSubtarget>();
isLikeA9 = STI->isLikeA9() || STI->isSwift();
isSwift = STI->isSwift();
Modified: llvm/trunk/lib/Target/ARM/Thumb1InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb1InstrInfo.cpp?rev=229999&r1=229998&r2=229999&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Thumb1InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Thumb1InstrInfo.cpp Fri Feb 20 02:24:37 2015
@@ -44,7 +44,7 @@ void Thumb1InstrInfo::copyPhysReg(Machin
bool KillSrc) const {
// Need to check the arch.
MachineFunction &MF = *MBB.getParent();
- const ARMSubtarget &st = MF.getTarget().getSubtarget<ARMSubtarget>();
+ const ARMSubtarget &st = MF.getSubtarget<ARMSubtarget>();
assert(ARM::GPRRegClass.contains(DestReg, SrcReg) &&
"Thumb1 can only copy GPR registers");
More information about the llvm-commits
mailing list